WoTUG - CPA 2005 - Programme

CPA2005 Programme

The CPA2005 programme comprises two full day, one half day, and two evening sessions. Each day will begin with a keynote talk. A late bar each evening and a conference dinner will provide ample opportunity to relax, socialize, and discuss issues informally. Further details, some motivation and a welcome can be found in the Preface to the CPA2005 Proceedings.

The conference opens on Sunday evening with registration, an evening meal, and an informal evening session. Monday morning will open with a welcome address by professor Martin Rem, Director of SAI/Software Technology of Technische Universiteit Eindhoven, and the first keynote talk. The conference will close after lunch on Wednesday.

Keynote speakers

Ad Peeters, CEO of Handshake Solutions, High Tech Campus, Eindhoven.
H. Peter Hofstee, CELL Chief Architect and CELL Synergistic Processor Chief Architect at IBM Systems and Technology Group in Austin, Texas, United States of America.
Guy Broadfoot, Lead Consultant at Verum, Eindhoven.
Paul Stravers, Senior Scientist at Philips Research Laboratories, Eindhoven

Tentative Schedule

Please note that on Monday and Tuesday all presentations will be at the Blauwe Zaal (Blue Room) of the Auditorium at TU/e. On Wednesday, the presentations will be in Lecture Hall 4 of the Auditorium at TU/e.

Sunday / September 18, 2005
16:00	Early registration at Crown Hotel
18:00	Diner at Crown Hotel
20:00	Fringe Session I - Basic introduction of methods, techniques, tools, terminology associated with CPA - Christian L. Jacobsen and Damian J. Dimmich, A Transterpreter Adventure - Peter Welch, A CSP Model for Mobile Channels - Matt Hammond (BBC Research & Development), Kamaelia, an open source framework for developing highly concurrent systems.
23:00	Social Gathering
Monday / September 19, 2005
08:30	Registration / Reception at TU/e, Auditorium
08:55	Opening by professor Martin Rem
09:00	Invited Talk by Ad Peeters (CEO of Handshake Solutions, High Tech Campus, Eindhoven) entitled "Handshake Technology: High Way to Low Power" (Abstract)
10:00	Arash Saifhashemi and Peter A. Beerel, High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog (Abstract)
10:30	Coffee / Tea
11:00	Peter Welch and Fred Barnes, Mobile Barriers for occam-pi: Semantics, Implementation and Application (Abstract)
11:30	Damian J. Dimmich and Christian L. Jacobsen, A Foreign-Function Interface Generator for occam-pi (Abstract)
12:00	Fred Barnes, Interfacing C and occam-pi (Abstract)
12:30	John Markus Bjørndalen, Otto J Anshus and Brian Vinter, Interactive Computing with the Minimum intrusion Grid (MiG) (Abstract)
13:00	Lunch in TU/e, Senaatzaal
14:00	Invited Talk by H. Peter Hofstee (CELL Chief Architect at IBM Systems and Technology Group, Austin, Texas, USA) entitled "Communication and Synchronization in the Cell Processor" (Abstract)
15:00	Albert Schoute, Remco Seesink, Werner Dierssen and Niek Kooji, Fast Data Sharing within a Distributed, Multithreaded Control Framework for Robot Teams (Abstract)
15:30	Dusko S. Jovanovic, Bojan E. Orlic, and Jan F. Broenink, On Issues of Constructing an Exception Handling Mechanism for CSP-Based Process-Oriented Concurrent Software (Abstract)
16:00	Coffee / Tea
16:30	John Jakson, R16: a New Transputer Design for FPGAs (Abstract)
17:00	Brian Vinter, The Architecture of the Minimum intrusion Grid (MiG) (Abstract)
17:30	Kevin Chalmers and Jon Kerridge, jcsp.mobile: A Package Enabling Mobile Processes and Channels (Abstract)
18:00	Dinner at TU/e, University Club
20:00	Fringe Session II - John Jakson - More on R16: a New Transputer Design for FPGAs - Jon Kerridge, JCSP Game - Dusko Jovanovic, On a combination of complementary dependability approaches for process-oriented CSP-based software architectures - Mario Schweigler, pony - The occam-pi Network Environment - Eric Verhulst, On the Open License Society - Roger Gook (Celoxica), CSP by Stealth for Hardware Design
23:00	Social Gathering
Tuesday / September 20, 2005
08:30	Reception at TU/e, Auditorium
09:00	Invited Talk by Guy Broadfoot (Lead Consultant at Verum, Eindhoven) entitled "If Concurrency in Software is So Simple, Why is it So Hard?" (Abstract)
10:00	Marc L. Smith, A Unifying Theory of True Concurrency Based on CSP and Lazy Observation (Abstract)
10:30	Coffee / Tea
11:00	Adam Sampson, Peter Welch and Fred Barnes, Lazy Cellular Automata with Communicating Processes (Abstract)
11:30	Bernhard H.C. Sputh and Alastair R. Allen, JCSP-Poison: Safe Termination of CSP Process Networks (Abstract)
12:00	Vladimir Klebanov, Philipp Rümmer, Steffen Schlager and Peter H. Schmitt, Verification of JCSP Programs (Abstract)
12:30	Mihai Ivanovici, Razvan Beuran and Neil Davies, Assessing Application Performance in Degraded Network Environments: an FPGA-based Approach (Abstract)
13:00	Lunch in TU/e, Senaatzaal
14:00	Bart Rem, Ajeesh Gopalakrishnan, Tom J.H. Geelen and Herman Roebbers. Automatic Handel-C Generation from MATLAB and Simulink for Motion Control with an FPGA (Abstract)
14:30	Gerald. H. Hilderink, Exception Handling Mechanism in Communicating Threads for Java (Abstract)
15:00	Hans Henrik Happe and Brian Vinter, Improving TCP/IP Multicasting with Message Segmentation (Abstract)
15:30	Coffee / Tea
16:00	Ian East, Interfacing with Honeysuckle by Formal Contract (Abstract)
16:30	Jon Kerridge, Ken Barclay and John Savage, Groovy Parallel! A Return to the Spirit of occam? (Abstract)
17:00	W. B. Gardner, CSP++: How Faithful to CSPm? (Abstract)
17:30	Panel Session
19:30	Sherry Reception at DAF Museum
20:00	Dinner at DAF Museum
22:30	Visit to DAF Museum (Optional)
23:30	Social Gathering
Wednesday / September 21, 2005
08:30	Reception at TU/e, Auditorium
09:00	Invited Talk by Paul Stravers (Senior Scientist at Philips Research Laboratories, High Tech Campus, Eindhoven) entitled "Homogeneous Multiprocessing for Consumer Electronics" (Abstract)
10:00	Johnston Stewart, Paddy Nixon, Tim Walsh and Ian Ferguson, Towards Strong Mobility in the Shared Source CLI (Abstract)
10:30	Maarten H. Wiggers, Nikolay Kavaldjiev, Gerard J. M. Smit, Pierre G. Jansen, Architecture Design Space Exploration for Streaming Applications through Timing Analysis (Abstract)
11:00	Coffee / Tea
11:30	Marcel A. Groothuis, Geert K. Liet, Jan F. Broenink, gCSP occam Code Generation for RMoX (Abstract)
12:00	Alistair McEwan, Formally, on Guards (Abstract)
12:30	CPA2005 Best Paper Awards CPA2005 Closing WoTUG Annual General Members Meeting
13:00	Lunch at TU/e, Senaatzaal
15:00	Visit to Philips Museum (Optional) [Until 17:00]
(End of CPA2005)

Invited Talks

Handshake Technology: High Way to Low Power (Invited Talk) Ad Peeters, Handshake Solutions, High Tech Campus, Eindhoven, The Netherlands
	Abstract - Handshake Solutions is a business line of the Philips Technology Incubator that has developed a design flow that enables a fast path to exploit the benefits from self-timed circuits, such as ultra-low power consumption and reduced electromagnetic emission. The quick route is enabled by the combination of two elements: a high-level “timeless” design language and an intermediate architecture based on handshake circuits. The design language, Haste, offers a syntax similar to behavioral Verilog, and in addition has explicit constructs for parallelism, communication, and hardware sharing. Haste is a behavioral language in the sense that it supports sequential composition of actions (such as assignments and communications) without reference to their timing, and also allows for data-dependent while-loops and other data dependent execution traces. As a parallel programming language, Haste supports CSP concepts such as synchronized channel communication, both via point-to-point channels and through broadcast and narrowcast channels. In addition, Haste also allows for the design of interfaces and protocols through its support of synthesizable edge/posedge/negedge (wait for event) and wait (for state) constructs. Designers experience and have reported high productivity in Haste. It turns out that compared to synthesizable VHDL the number of code lines is more than halved, thus facilitating design-space exploration and re-use, and improving design productivity. Starting from Haste, one can compile to behavioral Verilog for functional verification, to clock-gated circuits for mapping onto FPGAs, and to clockless circuits for ultra-low-power and low-EME VLSI implementations. This compilation exploits an intermediate architecture based on handshake components, which implement language constructs of Haste using handshake protocols. Handshake components and circuits support a modular design style, and can easily be implemented both as a clocked and as a self-timed circuit. The Handshake Solutions design flow is complementary to and compatible with third party EDA tools, e.g. for logic synthesis, test-pattern generation, and placement and routing. The clockless design flow works with standard-cell libraries, does not need any special cells and has a scan-test solution implemented. The talk will highlight the expressive power of Haste, how it is implemented in handshake circuits, and how this has led to concrete IC designs on the market. Keywords - Handshake, Haste, FPGA, communication, parallel programming language, parallelism, design language, clockless, interfaces, protocols.
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Communication and Synchronization in the Cell Processor (Invited Talk) H. Peter Hofstee, IBM Systems and Technology Group, Austin, Texas, United States of America
	Abstract - This talk will first present an overview of the Cell Broadband Processor Architecture and then provide a more in-depth look at the various communication and synchronization mechanisms the architecture supports. We will look at the various types of coherent DMA commands supported in this architecture, at the asynchronous “channel” command interface between the core of the synergistic processor and its DMA processor, and at a number of other mechanisms that enable fast processor-to-processor communication for short messages. Keywords - Cell processor, architecture, communication, synchronization, channel, DMA processor, command interface
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If Concurrency in Software is So Simple, Why is it So Hard? (Invited Talk) Guy Broadfoot, Verum, Eindhoven, The Netherlands
	Abstract - Not yet available.
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Homogeneous Multiprocessing for Consumer Electronics (Invited Talk) Paul Stravers, Philips Research Laboratories, Eindhoven, The Netherlands
	Abstract - Processor architectures have reached a point where it is getting increasingly hard to improve their performance without resorting to complex and exotic measures. Polack observed in 2000 that Intel processors had been “on the wrong side of a square law” for almost a decade. Embedded processors for consumer and telecommunication chips are now confronted with the same rule of diminishing returns. To further improve their performance, the processors are getting disproportionally bigger and consume much more energy per operation than previous generations. Traditionally, embedded systems-on-chip (SoC) have been designed as heterogeneous multiprocessors, where most processors are not programmable and a single control processor synchronizes all communication. Obvious advantages of such systems include low cost and low power consumption. In high-volume products, this outweighs disadvantages like a low degree of design reuse, little software reuse, and long product lead times. Despite all the hard work and good intentions it has proved difficult to establish a platform around heterogeneous SoC architectures. With the rise of non-recurrent engineering costs and an increasingly global and competitive semiconductor market, the need for a successful SoC platform is felt stronger than ever in the industry. Next to cost, the availability of qualified engineers is often an even bigger problem. Given that it is not unusual to spend several hundreds of person-years on software development for a single product, it is easy to see that even a multinational company can only have a very limited number of products in development at any point in time. The solution we propose is to move away from heterogeneous SoC and instead embrace homogeneous embedded multiprocessors. In this talk we discuss embedded multiprocessor architectures and how they relate to programming models. We contrast heterogeneous to homogeneous architectures, and we show how the traditional efficiency gap between the two is narrowing. We also discuss issues related to hardware and software reuse, and the quest for composable systems to speed up the often lengthy process of embedded system integration. Finally, we introduce Wasabi, the Philips high-performance homogeneous multiprocessor in 65nm technology, that will be available to the research community in 2006. Keywords - Wasabi, SoC, homogeneous embedded multiprocessor, embedded multiprocessor architectures.
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Accepted Papers

Interfacing with Honeysuckle by Formal Contract Ian East, Department for Computing, Oxford Brookes University, Oxford, England, United Kingdom
	Abstract - Honeysuckle is a new programming language that allows systems to be constructed from processes which communicate under service (client-server or master-servant) protocol. The model for abstraction includes a formal definition of both service and service-network (system or component). Any interface between two components thus forms a binding contract which will be statically verified by the compiler. An account is given of how such an interface is constructed and expressed in Honeysuckle, including how it may encapsulate state, and how access may be shared and distributed. Implementation is also briefly discussed. Keywords - Client-server protocol, compositionality, interfacing, component-based software development, deadlock-freedom, programming language.
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Groovy Parallel! A Return to the Spirit of occam? Jon Kerridge, Ken Barclay and John Savage, The School of Computing, Napier University, Edinburgh, United Kingdom
	Abstract - For some years there has been much activity in developing CSP-like extensions to a number of common programming languages. In particular, a number of groups have looked at extensions to Java. Recent developments in the Java platform have resulted in groups proposing more expressive problem solving environments. Groovy is one of these developments. Four constructs are proposed that support the writing of parallel systems using the JCSP package. The use of these constructs is then demonstrated in a number of examples, both concurrent and parallel. A mechanism for writing XML descriptions of concurrent systems is described and it is shown how this is integrated into the Groovy environment. Finally conclusions are drawn relating to the use of the constructs, particularly in a teaching and learning environment. Keywords - Groovy, JCSP, Parallel and Concurrent Systems, Teaching and Learning
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On Issues of Constructing an Exception Handling Mechanism for CSP-Based Process-Oriented Concurrent Software Dusko S. Jovanovic, Bojan E. Orlic, Jan F. Broenink, Twente Embedded Systems Initiative, Drebbel Institute for Mechatronics and Control Engineering, Faculty of EE-Math-CS, University of Twente, Enschede, the Netherlands
	Abstract - This paper discusses issues, possibilities and existing approaches for fitting an exception handling mechanism (EHM) in CSP-based process-oriented software architectures. After giving a survey on properties desired for a concurrent EHM, specific problems and a few principal ideas for including exception handling facilities in CSP-designs are discussed. As one of the CSP-based frameworks for concurrent software, we extend CT (Communicating Threads) library with the exception handling facilities. The extensions result in two different EHM models whose compliance with the most important demands of concurrent EHMs (handling simultaneous exceptions, the mechanism formalization and efficient implementation) are observed.
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Automatic Handel-C Generation from MATLAB® and Simulink® for Motion Control with an FPGA Bart Rem, Ajeesh Gopalakrishnan, Tom J.H. Geelen, Technische Universiteit Eindhoven, Eindhoven, The Netherlands and Herman Roebbers, Philips TASS, Eindhoven, The Netherlands
	Abstract - In this paper, we demonstrate a structured approach to proceed from development in a high level-modeling environment to testing on the real hardware. The concept is introduced by taking an example scenario that involves automatic code generation of Handel-C for FPGAs. The entire process is substantiated with a prototype that generates Handel-C code from MATLAB®/Simulink® for most common Simulink® blocks. Furthermore, we establish the potential of the notion by generating Handel-C for an FPGA, which controls the flow of paper through the scanning section of a printer/copier. Additionally, we present another method to generate Handel-C from a state-based specification. Finally, to verify and validate the behavior of the generated code, we execute several levels of simulation, including software-in-the-loop and hardware-in-the-loop simulations. Keywords - FPGA, embedded systems, motion control, Hardware Software Co-Design, MATLAB®, Hardware-in-the-Loop, Software-in-the-Loop, Co-Simulation, Electronic Design Automation (EDA), Automatic Document Feeder (ADF).
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JCSP-Poison: Safe Termination of CSP Process Networks Bernhard H.C. Sputh and Alastair R. Allen, Department of Engineering, University of Aberdeen, Aberdeen, United Kingdom
	Abstract - This paper presents a novel technique for safe partial or complete process network termination. The idea is to have two types of termination messages / poison: LocalPoison and GlobalPoison. Injecting GlobalPoison into a process network results in a safe termination of the whole process network. In contrast, injected LocalPoison only terminates all processes until it is filtered out by Poison-Filtering Channels. This allows the creation of termination domains inside a process network. To make handling of a termination message easy, it is delivered as an exception and not as a normal message. The necessary Poisonable- and Poison-Filtering-Channels have been modelled in CSP and checked using FDR. A proof of concept implementation for Communicating Sequential Processes for Java (JCSP) has been developed and refined. Previously, JCSP offered no safe way to terminate the process network. When the user terminated the program, the Java Virtual Machine (JVM) simply stops all threads (processes), without giving the processes the chance to perform clean up operations. A similar technique is used to perform partial termination of process networks in JCSP, making it unsafe as well. The technique presented in this paper is not limited to JCSP, but can easily be ported to other CSP environments. Partial process network termination can be applied in the area of Software Defined Radio (SDR), because SDR systems need to be able to change their signal processing algorithms during runtime. Keywords - JCSP, SDR, Partial Process Network Termination, Poisoning, Poionable-Channel, Poison-Filtering-Channel, Termination Domains
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jcsp.mobile: A Package Enabling Mobile Processes and Channels Kevin Chalmers and Jon Kerridge, School of Computing, Napier University, Edinburgh, United Kingdom
	Abstract - The JCSPNet package from Quickstone provides the capability of transparently creating a network of processes that run across a TCP/IP network. The package also contains mechanisms for creating mobile processes and channels through the use of filters and the class Dynamic Class Loader, though their precise use is not well documented. The package jcsp.mobile rectifies this position and provides a set of classes and interfaces that facilitates the implementation of systems that use mobile processes and channels. In addition, the ability to migrate processes and channels from one processor to another is also implemented. The capability is demonstrated using a multi-user game running on an ad-hoc wireless network using a workstation and four PDAs. Keywords - JCSP, JCSPNET, Mobile Processes and Channels, Dynamic Class Loading, Migratable Processes and Channels, Location Aware Computing
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CSP++: How Faithful to CSPm? W. B. Gardner, Dept. of Computing & Information Science, University of Guelph, Canada
	Abstract - CSP++ is a tool that makes specifications written in CSPm executable and extensible. It is the basis for a technique called selective formalism, which allows part of a system to be designed in verifiable CSPm statements, automatically translated into C++, and linked with functions coded in C++. This paper describes in detail the subset of CSPm that can be accurately translated by CSP++, and how the CSP semantics are achieved by the runtime framework. It also explains restrictions that apply to coding in CSPm for software synthesis, and the rationale for those restrictions. Keywords - CSPm, C++, selective formalism
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Fast Data Sharing within a Distributed, Multithreaded Control Framework for Robot Teams Albert Schoute, University of Twente, Enschede, The Netherlands, Remco Seesink, Atos Origin, The Netherlands, Werner Dierssen, Triopsys, The Netherlands, and Niek Kooji, Qmagic, The Netherlands
	Abstract - In this paper a data sharing framework for multi-threaded, distributed control programs is described that is realized in C++ by means of only a few, powerful classes and templates. Fast data exchange of entire data structures is supported using sockets as communication medium. Access methods are provided that preserve data consistency and synchronize the data exchange. The framework has been successfully used to build a distributed robot soccer control system running on as many computers as needed. Keywords - robot soccer, control software, distributed design, data sharing, multithreading, sockets
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Improving TCP/IP Multicasting with Message Segmentation Hans Henrik Happe and Brian Vinter, Dept. of Mathematics & Computer Science, University of Southern Denmark, Odense M, Denmark
	Abstract - Multicasting is a very important operation in high performance parallel applications. Making this operation efficient in supercomputers has been a topic of great concern. Much effort has gone into designing special interconnects to support the operation. Today’s huge deployment of NoWs (Network of Workstations) has created a high demand for efficient software-based multicast solutions. These systems are often based on low-cost Ethernet interconnects without direct support for group communication. Basically TCP/IP is the only widely supported method of fast reliable communication, though it is possible to improve Ethernet performance at many levels – i.e., by-passing the operating system or using physical broadcasting. Low-level improvements are not likely to be accepted in production environments, which leaves TCP/IP as the best overall choice for group communication. In this paper we describe a TCP/IP based multicasting algorithm that uses message segmentation in order to lower the propagation delay. Experiments have shown that TCP is very inefficient when a node has many active connections. With this in mind we have designed the algorithm so that it has a worst-case propagation path length of O(log n) with a minimum of connections per node. We compare our algorithm with the binomial tree algorithm often used in TCP/IP MPI implementations. Keywords - Multicasting, NoW, HPC
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Lazy Cellular Automata with Communicating Processes Adam Sampson, Peter Welch and Fred Barnes, Computing Laboratory, University of Kent, Canterbury, Kent, England
	Abstract - Cellular automata (CAs) are good examples of systems in which large numbers of autonomous entities exhibit emergent behaviour.Using the occam-pi and JCSP communicating process systems, we show how to construct “lazy” and “just-in-time” models of cellular automata, which permit very efficient parallel simulation of sparse CA populations on shared-memory and distributed systems. Keywords - CSP, occam-pi, JCSP, parallel, CA, Life, lazy, just-in-time, simulation
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A Unifying Theory of True Concurrency Based on CSP and Lazy Observation Marc L. Smith, Department of Computer Science, Colby College, Waterville, Maine, USA
	Abstract - What if the CSP observer were lazy? This paper considers the consequences of altering the behavior of the CSP observer. Specifically, what implications would this new behavior have on CSP’s traces? Laziness turns out to be a useful metaphor. We show how laziness permits transforming CSP into a model of true concurrency (i.e., non-interleaved trace semantics). Furthermore, the notion of a lazy observer supports tenets of view-centric reasoning (VCR): parallel events (i.e., true concurrency), multiple observers (i.e., different views), and the possibility of imperfect observation. We know from the study of programming languages that laziness is not necessarily a negative quality; it provides the possibility of greater expression and power in the programswe write. Similarly, within the context of the Unifying Theories of Programming, a model of true concurrency— VCR — becomes possible by permitting (even encouraging) the CSP observer to be lazy. Keywords - Unifying Theories of Programming, lazy observation, true concurrency
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The Architecture of the Minimum intrusion Grid (MiG) Brian Vinter, University of Southern Denmark, Odense M, Denmark
	Abstract - This paper introduces the philosophy behind a new Grid model, the Minimum intrusion Grid, MiG. The idea behind MiG is to introduce a ‘fat’ Grid infrastructure which will allow much ‘slimmer’ Grid installations on both the user and resource side. This paper presents the ideas of MiG, some initial designs and finally a status report of the implementation.
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Verification of JCSP Programs Vladimir Klebanov, University of Koblenz-Landau, Institute for Computer Science, Koblenz, Germany Philipp Rümmer, Chalmers University of Technology, Dept. of Computer Science and Engineering, Gothenburg, Sweden Steffen Schlager and Peter H. Schmitt, Universität Karlsruhe, Institute for Theoretical Computer Science, Karlsruhe, Germany
	Abstract - We describe the first proof system for concurrent programs based on Communicating Sequential Processes for Java (JCSP). The system extends a complete calculus for the JavaCard Dynamic Logic with support for JCSP, which is modeled in terms of the CSP process algebra. Together with a novel efficient calculus for CSP, a rule system is obtained that enables JCSP programs to be executed symbolically and to be checked against temporal properties. The proof system has been implemented within the KeY tool and is publicly available. Keywords - Program verification, concurrency, Java, CSP, JCSP
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Assessing Application Performance in Degraded Network Environments: an FPGA-based Approach Mihai Ivanovici, Razvan Beuran, CERN, Geneva, Switzerland, and Neil Davies, Predictable Network Solutions, Bristol, UK
	Abstract - Network emulation is a technique that allows real-application performance assessment under controllable and reproducible conditions. We designed and implemented a hardware network emulator on an FPGA-based custom-design PCI platform. Implementation was facilitated by the use of the Handel-C programming language, that allows rapid development and fast translation into hardware and has specific constructs for developing systems with concurrent processes. We report on tests performed with web-browsing applications. Keywords - Application performance assessment, network emulation, FPGA, hardware implementation, Handel-C
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Architecture Design Space Exploration for Streaming Applications through Timing Analysis Maarten H. Wiggers, Nikolay Kavaldjiev, Gerard J. M. Smit, Pierre G. Jansen, Department of EEMCS, University of Twente, the Netherlands
	Abstract - In this paper we compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN\2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the application’s throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations.
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A Foreign-Function Interface Generator for occam-pi Damian J. Dimmich and Christian L. Jacobsen, Computing Laboratory, University of Kent, Canterbury, Kent, England
	Abstract - occam-pi is a programming language based on the CSP process algebra and the pi-calculus, and has a powerful syntax for expressing concurrency. occam-pi does not however, come with interfaces to a broad range of standard libraries (such as those used for graphics or mathematics). Programmers wishing to use these must write their own wrappers using occam-pi’s foreign function interface, which can be tedious and time consuming. SWIG offers automatic generation of wrappers for libraries written in C and C++, allowing access to these for the target languages supported by SWIG. This paper describes the occam-pi module for SWIG, which will allow automatic wrapper generation for occam-pi, and will ensure that occam-pi’s library base can be grown in a quick and efficient manner. Access to database, graphics and hardware interfacing libraries can all be provided with relative ease when using SWIG to automate the bulk of the work.
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Interfacing C and occam-pi Fred Barnes, Computing Laboratory, University of Kent, Canterbury, Kent, England
	Abstract - This paper describes an extension to the KRoC occam-pi system that allows processes programmed in C to participate in occam-pi style concurrency. The uses of this are wide-ranging, from providing low-level C processes running concurrently as part of an occam-pi network, through to concurrent systems programmed entirely in C. The easily extended API for C processes is based on the traditional Inmos C API, used also by CCSP, extended to cover new features of occam-pi. One of the motivations for this work is to ease the development of low-level network communication infrastructures. A library that provides for networking of channel-bundles over TCP/IP networks is presented, in addition to initial performance figures. Keywords - C, occam-pi, concurrency, processes, networks
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Interactive Computing with the Minimum intrusion Grid (MiG) John Markus Bjørndalen, Otto J. Anshus, University of Tromsø, Tromsø, Norway and Brian Vinter, University of Southern Denmark, Odense M, Denmark
	Abstract - Grid computing is finally starting to provide solutions for capacity computing, that is problem solving where there is a large number of independent tasks for execution. This paper describes the experiences with using Grid for capability computing, i.e. solving a single task efficiently. The chosen capability application is driving a very large display which requires enormous processing power due to its huge graphic resolution (7168 x 3072 pixels). Though we use an advanced Grid middleware, the conclusion is that new features are required to provide such coordinated calculations as the present application requires.
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High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog Arash Saifhashemi and Peter A. Beerel, University of Southern California, EE Department, Systems Division
	Abstract - In this paper we describe a method for modeling channel-based asynchronous circuits using Verilog HDL. We suggest a method to model CSP-like channels in Verilog HDL. This method also describes nonlinear pipelines and high level channel timing properties, such as forward and backward latencies, minimum cycle time, and slack. Using Verilog enables us to describe the circuit at many levels of abstraction and to use the commercially available CAD tools. Keywords - CSP, Verilog, Asynchronous Circuits, Nonlinear Pipelines
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Mobile Barriers for occam-pi: Semantics, Implementation and Application Peter Welch and Fred Barnes, Computing Laboratory, University of Kent, Canterbury, Kent, England
	Abstract - This paper introduces a safe language binding for CSP multiway events (barriers—both static and mobile) that has been built into occam-pi (an extension of the classical occam language with dynamic parallelism, mobile processes and mobile channels). Barriers provide a simple way for synchronising multiple processes and are the fundamental control mechanism underlying both CSP (Communicating Sequential Processes) and BSP (Bulk Synchronous Parallelism). Formal semantics (through modelling in classical CSP), implementation details and early performance benchmarks (16 nanoseconds per process per barrier synchronisation on a 3.2 GHz Pentium IV) are presented, along with some likely directions for future research. Applications are outlined for the fine-grained modelling of dynamic systems, where barriers are used for maintaining simulation time and the phased execution of time steps, coordinating safe and desired patterns of communication between millions (and more) of processes. This work forms part of our TUNA project, investigating emergent properties in large dynamic systems (nanite assemblies). Keywords - Barriers, events, processes, mobility, occam-pi, CSP, pi-calculus
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Exception Handling Mechanism in Communicating Threads for Java Gerald. H. Hilderink
	Abstract - The concept of exception handling is important for building reliable software. An exception construct is proposed in this paper, which implements an exception handling mechanism that is suitable for concurrent software architectures. The aim of this exception construct is to bring exception handling to a high-level of abstraction such that exception handling does scale well with the complexity of the system. This is why the exception construct supports a CSP-based software design approach. The proposed exception construct embraces informal semantics, but which are intuitive and suitable to software engineering. The exception construct is prototyped in the CSP for Java library, called CTJ. Keywords - Exception handling, CSP, concurrency, real-time, embedded software.
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R16: a New Transputer Design for FPGAs John Jakson
	Abstract - This paper describes the ongoing development of a new FPGA hosted Transputer using a Load Store RISC style Multi Threaded Architecture (MTA). The memory system throughput is emphasized as much as the processor throughput and uses the recently developed Micron 32MByte RLDRAM which can start fully random memory cycles every 3.3ns with 20ns latency when driven by an FPGA controller. The R16 shares an object oriented Memory Manager Unit (MMU) amongst multiple low cost Processor Elements (PEs) until the MMU throughput limit is reached. The PE has been placed and routed at over 300MHz in a Xilinx Virtex-II Pro device and uses around 500 FPGA basic cells and 1 Block RAM. The 15 stage pipeline uses 2 clocks per instruction to greatly simplify the hardware design which allows for twice the clock frequency of other FPGA processors. There are instruction and cycle accurate simulators as well as a C compiler in development. The compiler can now emit optimized small functions needed for further hardware development although compiling itself requires much work. Some occam and Verilog language components will be added to the C base to allow a mixed occam and event driven processing model. Eventually it is planned to allow occam or Verilog source to run as software code or be placed as synthesized co processor hardware attached to the MMU. Keywords - Transputer, FPGA, Multi Threaded Architecture, occam, RLDRAM
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Towards Strong Mobility in the Shared Source CLI Johnston Stewart, SmartLab, Dept. of Comp. and Inf. Sciences, University of Strathclyde, Glasgow Paddy Nixon, Computer Science Department, University College Dublin, Dublin 4, Ireland Tim Walsh, Department of Computer Science, University of Dublin, Trinity College, Dublin, Ireland and Ian Ferguson, SmartLab, Dept. of Comp. and Inf. Sciences, University of Strathclyde, Glasgow
	Abstract - Migrating a thread while preserving its state is a useful mechanism to have in situations where load balancing within applications with intensive data processing is required. Strong mobility systems, however, are rarely developed or implemented as they introduce a number of major challenges into the implementation of the system. This is due to the fact that the underlying infrastructure that most computers operate on was never designed to accommodate such a system, and because of this it actually impedes the development of these systems to some degree. Using a system based around a virtual machine, such as Microsoft’s Common Language Runtime (CLR), circumnavigates many of these problems by abstracting away system differences. In this paper we outline the architecture of the threading mechanism in the shared source version of the CLR known as the Shared Source Common Language Infrastructure (SSCLI). We also outline how we are porting strong mobility into the SSCLI, taking advantage of its virtual machine. Keywords - Thread Mobility, Virtual Machine, Common Language Runtime.
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gCSP occam Code Generation for RMoX Marcel A. Groothuis, Geert K. Liet, Jan F. Broenink, Twente Embedded Systems Initiative, Drebbel Institute for Mechatronics and Control Engineering,University of Twente, Enschede, the Netherlands
	Abstract - gCSP is a graphical tool for creating and editing CSP diagrams. gCSP is used in our labs to generate the embedded software framework for our control systems. As a further extension to our gCSP tool, an occam code generator has been constructed. Generating occam from CSP diagrams gives opportunities to use the Raw-Metal occam eXperiment (RMoX) as a minimal operating system on the embedded control PCs in our mechatronics laboratory. In addition, all processors supported by KRoC can be reached from our graphical CSP tool. The commstime benchmark is used to show the trajectory for gCSP code generation for the RMoX operating system. The result is a simple means for using RMoX in our laboratory for our control systems. We want to use RMoX for future research on distributed control and for performance comparisons between a minimal operating system and our CTC++/RT-linux systems. Keywords - CSP, Embedded Control Systems, Real-time, occam
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Formally, on Guards Alistair McEwan, Department of Computing, University of Surrey, UK
	Abstract - In this paper, we consider the problem of output guards in occam style programs. We show how these programs can be modelled in CSP. We then show how guarded outputs can be removed from the CSP specification such that the resulting implementation is a valid occam program. The techniques for removing guarded outputs are shown to be jointly complete -- meaning that any guarded output can be removed. Verification is performed using the model-checker for CSP, FDR.
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