Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2018,
the 40th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by
Professor Dr. Rainer Spallek,
Chair of
VLSI Design, Diagnostics and Architecture
at the Faculty of Computer Science,
Technische Universität Dresden, Germany.
The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke
and in partnership with WoTUG.
About WoTUG
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
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theory (programming models, process algebra, semantics, ...);
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practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
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education (at school, undergraduate and postgraduate levels, ...);
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applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
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for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
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for system integrity (dependability, security, safety, liveness, ...);
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for making things simple.
Of course, neither of the above sets of bullets are exclusive.
WoTUG publications
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
Adapted OS Link / DS Link Protocols for Use in Mutliprocessor Routing Networks
By S. Triger, Brian C. O'Neill, S. Clark
Inter-processor communications play a vital role in the performance of distributed parallel networks. This document analyses various protocol options for high speed, serial, inter-processor communications for use in embedded multiprocessor systems. The protocol is used to pass information in a fault tolerant routing network. The work has resulted in a custom processor interface, which forms the gateway between the processing node and the distributed communications network, building on previous work. The role of the interface is to provide maximum hardware support for communications between the network and the processor. This alleviates the processor from having to oversee communications transactions and allows it to concentrate on program execution. The research focuses on protocol alterations aimed at improving the fault tolerant aspects of the design when dealing with various forms of network failure. By improving the fault tolerance of the network, communications bottlenecks can be avoided and data throughput can be maximised. Previously, communications across the network had used the OS Links protocol and, experimentally, DS Links. These were analysed and adapted to provide the current communications protocol, which is compared with these protocols. This protocol is more efficient, and helps to provide many features to ensure data integrity.
Complete record...
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