Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2018,
the 40th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by
Professor Dr. Rainer Spallek,
Chair of
VLSI Design, Diagnostics and Architecture
at the Faculty of Computer Science,
Technische Universität Dresden, Germany.
The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke
and in partnership with WoTUG.
About WoTUG
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
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theory (programming models, process algebra, semantics, ...);
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practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
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education (at school, undergraduate and postgraduate levels, ...);
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applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
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for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
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for system integrity (dependability, security, safety, liveness, ...);
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for making things simple.
Of course, neither of the above sets of bullets are exclusive.
WoTUG publications
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
A Personal Perspective on the State of HPC in 2013
By Christopher C.R. Jones
This paper is fundamentally a personal perspective on the sad state of
High Performance Computing (HPC, or what was known once as
Supercomputing). It arises from the author's current experience in
trying to find computing technology that will allow codes to run
faster: codes that have been painstakingly adapted to efficient
performance on parallel computing technologies since around 1990, and
have allowed effective 10-fold increases in computing performance at 5
year HPC up-grade intervals, but for which the latest high-count
multi-core processor options fail to deliver improvement. The
presently available processors may as well not have the majority of
their cores as to use them actually slows the code - hard-won budget
must be squandered on cores that will not contribute. The present
situation is not satisfactory: there are very many reasons why we need
computational response, not merely throughput. There are a host of
cases where we need a large, complex simulation to run in a very short
time. A simplistic calculation based on the nominal performance of
some of the big machines with vast numbers of cores would lead one to
believe that such rapid computation would be possible. The nature of
the machines and the programming paradigms, however, remove this
possibility. Some of the ways in which the computer science community
could mitigate the hardware shortfalls are discussed, with a few more
off the wall ideas about where greater compute performance might be
found.
Complete record...
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