Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2018,
the 40th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by
Professor Dr. Rainer Spallek,
Chair of
VLSI Design, Diagnostics and Architecture
at the Faculty of Computer Science,
Technische Universität Dresden, Germany.
The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke
and in partnership with WoTUG.
About WoTUG
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
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theory (programming models, process algebra, semantics, ...);
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practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
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education (at school, undergraduate and postgraduate levels, ...);
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applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
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for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
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for system integrity (dependability, security, safety, liveness, ...);
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for making things simple.
Of course, neither of the above sets of bullets are exclusive.
WoTUG publications
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
Using occam-pi Primitives with the Cell Broadband Engine
By Damian J. Dimmich
The Cell Broadband Engine has a unique non-heterogeneous archi-
tecture, consisting of an on-chip network of one general purpose PowerPC pro-
cessor (the PPU), and eight dedicated vector processing units (the SPUs).
These processors are interconnected by a high speed ring bus, enabling the use
of different logical network topologies. When programming the Cell Broadband
Engine using languages such as C, a developer is faced with a number of chal-
lenges. For instance, parallel execution and synchronisation between proces-
sors, as well as concurrency on individual processors, must be explicitly, and
carefully, managed. It is our belief that languages explicitly supporting concur-
rency are able to offer much better abstractions for programming architectures
such as the Cell Broadband Engine.
Support for running occam- programs on the Cell Broadband Engine has
existed in the Transterpreter for some time. This support has however not
featured efficient inter-processor communication and barrier synchronisation,
or automatic deadlock detection. We discuss some of the changes required to
the occam- scheduler to support these features on the Cell Broadband Engine.
The underlying on-chip communication and synchronisation mechanisms are
explored in the development of these new scheduling algorithms. Benchmarks
of the communications performance are provided, as well as a discussion of how
to use the occam- language to distribute a program onto a Cell Broadband
Engine’s processors. The Transterpreter runtime, which already has support
for the Cell Broadband Engine, is used as the platform for these experiments.
The Transterpreter can be found at www.transterpreter.org.
Complete record...
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