Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2018,
the 40th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by
Professor Dr. Rainer Spallek,
Chair of
VLSI Design, Diagnostics and Architecture
at the Faculty of Computer Science,
Technische Universität Dresden, Germany.
The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke
and in partnership with WoTUG.
About WoTUG
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
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theory (programming models, process algebra, semantics, ...);
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practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
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education (at school, undergraduate and postgraduate levels, ...);
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applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
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for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
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for system integrity (dependability, security, safety, liveness, ...);
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for making things simple.
Of course, neither of the above sets of bullets are exclusive.
WoTUG publications
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
Implementation of KRoC on Analog Devices "SHARC" DSP
By André W. P. Bakkers, G. W. Otten, M. H. Schwirtz, R. Bruis, Jan F. Broenink
This paper summarises the experiences gained at the Control Laboratory of the University of Twente in porting the Kent Retargetable occam Compiler - KroC - to the Analog Devices’ ADSP21060 SHARC Digital Signal Processor. The choice of porting the KRoC to the DSP processor was in our view both a challenge and an absolute necessity because DSP processors are an important ingredient in modern day control systems. Currently, our implementation contains the most important occam primitives such as channel communication, PAR, ALT, and most of the integer arithmatic. Furthermore, a basic kernel was realised, providing channel-communication based scheduling only. This porting process, using quite straight-forward modifications of the SPARC KRoC-translator, was done within six weeks. A representative benchmark was constructed, showing that the 33Mhz SHARC-KRoC implementation is 40% faster than the the 25Mhz T800 using the INMOS D7205 Toolset.
Complete record...
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