Paper Details

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@InProceedings{Mir12,
  title = "{A} {H}igh {P}erformance {R}econfigurable {A}rchitecture for {F}lash {F}ile {S}ystems",
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  author= "Mir, Irfan and McEwan, Alistair A. and Perrins, Neil J.",
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  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
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  pages = "171--184",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "NAND flash memory is widely adopted as the primary storage
     medium in embedded systems. The design of the flash
     translation layer, and exploitation of parallel I/O
     architectures, are crucial in achieving high performance
     within a flash file system. In this paper we present our new
     FPGA based flash management framework using
     reconfigurable computing that supports high performance
     flash storage systems. Our implementation is in Verilog, and
     as such enables us to design a highly concurrent system at a
     hardware level in both the flash translation layer and the
     flash controller. Results demonstrate that implementing the
     flash translation layer and flash controller directly in
     hardware, by exploiting reconfigurable computing, permits us
     to exploit a highly concurrent architecture that leads to
     fast response times and throughput in terms of read/write
     operations."
}

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