Paper Details

@InProceedings{TanakaFukuchi04,
  title = "{D}esign of a {T}ransputer {C}ore and {I}mplementation in an {FPGA}",
  author= "Tanaka, Makoto and Fukuchi, Naoya and Ooki, Yutaka and Fukunaga, Chikara",
  editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.",
  pages = "361--372",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004",
  isbn= "1 58603 458 8",
  year= "2004",
  month= "sep",
  abstract= "We have made an IP (Intellectual Property) core for the T425
     transputer. The same machine instructions as the transputer
     are executable in this IP core (we call it TPCORE). To
     create an IP code for the transputer has two aspects. On one
     hand, if we could succeed in building our own one and put it
     in an FPGA, we could apply it as a core processor in a
     distributed system. We also intend to put it in a VLSI chip.
     On the other hand, if we can extend our transputer
     development starting from a very conventional one to more
     sophisticated ones, as Inmos proceeded to the T9000, we will
     eventually find our technological breakthrough for the
     bottlenecks that the original transputer had, such as the
     restriction of the number of communication channels. It is
     important to have an IP core for the transputer. Although
     TPCORE uses the same register set with the same
     functionality as transputer and follows the same mechanisms
     for link communication between two processes and interrupt
     handling, the implementation must be very different from
     original transputer. We have extensively used the micro-code
     ROM to describe any states that TPCORE must take. Using this
     micro code ROM for the state transition description, we
     could implement TPCORE economically on FPGA space and
     achieve efficient performance."
}

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