Paper Details

A Transputer-based Workstation Accelerator for Optimisation Algorithms

Authors: Woodhams, F. W. D., Price, W. L.

Abstract:

This paper discusses the design of a transputer-based accelerator for both combinatorial and global optimisation algorithms. Combinatorial optimisation has engineering applications in, for example, placement and routing of VLSI circuits. This type of problem is known to be in the complexity class NP-complete 1. For the solution of these problems some form of random search heuristic is often required. One such heuristic is the simulated annealing algorithm^. This algorithm is usually too slow for the interactive user and is normally run on a mainframe computer.

Proceedings:

OUG-12: Tools and Techniques for Transputer Applications, Stephen J. Turner, 1990, pp 148 - 153 published by IOS Press, Amsterdam

This record in other formats:

Web page: BibTEX, Refer
Plain text: BibTEX, Refer

If you have any comments on this database, including inaccuracies, requests to remove or add information, or suggestions for improvement, the WoTUG web team are happy to hear of them. We will do our best to resolve problems to everyone's satisfaction.

Copyright for the papers presented in this database normally resides with the authors; please contact them directly for more information. Addresses are normally presented in the full paper.