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- OCCARM: An Occam Parallel Simulation Model of the AMULET1
Asynchronous Microprocessor (OCCARM)
OCCARM is a simulation model of the AMULET1
microprocessor -- asynchronous implementations of the ARM
RISC microprocessor developed at the University of Manchester.
OCCARM has been implemented as a hierarchy of occam
processes, with each process modelling a different functional
module of AMULET1. OCCARM consists of more than fifteen
thousand lines of occam code.
Author: Georgios K. Theodoropoulos (email@example.com)
- Instruction-Level Simulation And Tracing resources
- Resources for MPtrace: Techniques for Efficient Inline Tracing
on a Shared-Memory Multiprocessor
- Resources for Shade: A Fast Instruction-Set Simulator for
- Solaris port of the Proteus parallel computer simulator.
Sun Solaris 2.5 and SunOS 4.1.3 port of the Proteus parallel
computer simulator. Includes improved shared memory simulation,
scripting, and many other changes.
Author: David M. Koppelman (firstname.lastname@example.org), 102 EE Building, Louisiana State University, and
Baton Rouge, LA, 70803, USA
- Sparc V8 and SunOS 5.x simulator/emulator (SimICS)
SimICS is a combination of a Sparc V8 instruction-set simulator
and SunOS 5.x operating system emulator. SimICS is a powerful
tool for debugging and profiling Solaris 2.x programs, including
support for multiprogramming and parallel applications.
Author: Peter Magnusson (email@example.com)
- MINT (MIPS Interpreter)
A fast program-driven simulator for multiprocessor
Author: Jack Veenstra (firstname.lastname@example.org)
Small multiprocessor simulator package written.
Author: Felix Quevedo (email@example.com), University of Miami, USA
- PAINT: PA Instruction Set Interpreter
An instruction set simulator based on Mint which
interprets the PA-RISC instruction set.
- PDATS trace format
Sources and ACS trace driven cache simulator from
Tracebase at New Mexico State University (NMSU), USA.
- PROTEUS parallel architecture simulator
Author: Eric Brewer (firstname.lastname@example.org)
- Bob Wilson's fine-grain parallelism simulator from Stanford.
This is the simulator that was used to generate the results in
the paper "Limits of Control Flow on Parallelism" from
Copyright © 1993-2000 Dave Beckett & WoTUG