Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2017,
the 39th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 20th. to Wednesday August 23rd. 2017 and is hosted by the
Department of Computer Science at the
University of Malta.
Conference sessions will take place at the
Auditorium of the University of Malta, Valletta Campus.
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
and to stimulate discussion and ideas on the roles concurrency will play in the future:
theory (programming models, process algebra, semantics, ...);
practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
education (at school, undergraduate and postgraduate levels, ...);
applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
Of course, neither of the above sets of bullets are exclusive.
for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
for system integrity (dependability, security, safety, liveness, ...);
for making things simple.
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
The name may be familiar of old to the WoTUG community, but it has now been adopted by one of the fastest growing sectors of the silicon industry. Reconfigurable Computers are computing systems whose hardware architecture can be modified by software to suit the application at hand. The core component is the FPGA. Remarkable performance gains are achieved by placing an algorithm in an FPGA for embedded applications, compared with using a microprocessor or DSP. This is because an FPGA takes advantage of hardware parallelism while reducing the timing overheads needed for general-purpose microprocessor applications. For example the time taken by load/store operations and instruction decoding can be eliminated. Reconfiguration enables the FPGA to provide a problem specific computer for highly optimised application performance. Just as high level programming languages liberated the first microprocessors programming languages will liberate the FPGA. The first of these languages to become commercially available is Handel-C. Handel-C is based on the CSP Model; it was developed by the Hardware Compilation Group at the University of Oxford and is to be marketed by ESL. The Handel-C tools enable a software engineer to target directly FPGAs in a similar fashion to classical microprocessor cross-compiler development tools, without recourse to a Hardware Description Language. Thereby allowing the software engineer to directly realise the raw real-time processing capability of the FPGA. The skills and expertise gained by the WoTUG, provide the group with a competitive advantage to develop the innovative algorithms, applications and products in this domain.