Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2018,
the 40th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by
Professor Dr. Rainer Spallek,
VLSI Design, Diagnostics and Architecture
at the Faculty of Computer Science,
Technische Universität Dresden, Germany.
The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke
and in partnership with WoTUG.
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
and to stimulate discussion and ideas on the roles concurrency will play in the future:
theory (programming models, process algebra, semantics, ...);
practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
education (at school, undergraduate and postgraduate levels, ...);
applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
Of course, neither of the above sets of bullets are exclusive.
for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
for system integrity (dependability, security, safety, liveness, ...);
for making things simple.
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
Experiments in Translating CSP||B to Handel-C
This paper considers the issues involved in translating
specifications described in the CSP||B formal method into
Handel-C. There have previously been approaches to translating CSP
descriptions to Handel-C, and the work presented in this paper is
part of a programme of work to extend it to include the B component
of a CSP||B description. Handel-C is a suitable target language
because of its capability of programming communication and state,
and its compilation route to hardware. The paper presents two case
studies that investigate aspects of the translation: a buffer case
study, and an abstract arbiter case study. These investigations
have exposed a number of issues relating to the translation of
the B component, and have identified a range of options available,
informing more recent work on the development of a style for CSP||B
specifications particularly appropriate to translation to Handel-C.