Communicating Process Architectures
Communicating Process Architectures 2014,
the 36th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 24th to Wednesday August 27th 2014 and is hosted by the
Department of Computer Science, University of Oxford.
Accommodation and evening Fringe sessions will be at
St. Anne's College,
a few minutes walk from the Department.
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
and to stimulate discussion and ideas on the roles concurrency will play in the future:
theory (programming models, process algebra, semantics, ...);
practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
education (at school, undergraduate and postgraduate levels, ...);
applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
Of course, neither of the above sets of bullets are exclusive.
for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
for system integrity (dependability, security, safety, liveness, ...);
for making things simple.
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
A 40 Gbit/s Network Processor Design Platform
As the Internet evolves, the rapidly increasing demand for bandwidth is matched by a greater need for more intelligence with which to manage and meter the flow of that data to sustain economic growth. Conventional processing architectures and hardwired point solutions are not suited to these conflicting demands; there is an emerging need for a new approach for this data flow processing problem. This paper presents ClearSpeed's integrated Network Processor design platform that embodies many different levels of parallel processing. Designed to balance the bandwidth needs with programmability we introduce the MTAP architecture. An area and power efficient, fine-grained, scalable, multi-threaded parallel processor, designed with a 'bandwidth-centric' architecture and programmed in C. Based on the ClearConnect™ bus, an SoC communication architecture with VCI compliant interfaces, a high-bandwidth system architecture including a number of hardware accelerator units is also described. An example 40Gbit/s programmable and scalable classifier/forwarder is presented, embodying the concepts of the platform. To complete the picture, a comprehensive suite of software and hardware development tools is described.