Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2017,
the 39th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 20th. to Wednesday August 23rd. 2017 and is hosted by
Kevin Vella, Head of Department in
at the University of Malta.
Conference sessions will take place at the
Victoria Hotel in Sliema, Malta.
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
and to stimulate discussion and ideas on the roles concurrency will play in the future:
theory (programming models, process algebra, semantics, ...);
practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
education (at school, undergraduate and postgraduate levels, ...);
applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
Of course, neither of the above sets of bullets are exclusive.
for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
for system integrity (dependability, security, safety, liveness, ...);
for making things simple.
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
Shared-Clock Methodology for Time-Triggered Multi-Cores
The co-operative design methodology has significant advantages when
used in safety-related systems. Coupled with the time-triggered
architecture, the methodology can result in robust and predictable
systems. Nevertheless, use of a co-operative design methodology may
not always be appropriate especially when the system possesses tight
resource and cost constraints. Under relaxed constraints, it might be
possible to maintain a co-operative design by introducing additional
software processing cores to the same chip. The resultant multi-core
microcontroller then requires suitable design methodologies to
ensure that the advantages of time-triggered co-operative design are
maintained as far as possible. This paper explores the application of
a time-triggered distributed-systems protocol, called
on an eight-core microcontroller. The cores are connected in a
mesh topology with no hardware broadcast capabilities and three
implementations of the shared-clock protocol are examined. The
custom multi-core system and the network interfaces used for
the study are also described. The network interfaces share higher
level serialising logic amongst channels, resulting in low hardware
overhead when increasing the number of channels.