WoTUG - The place for concurrent processes

Annual Conference: Communicating Process Architectures

Communicating Process Architectures 2016, the 38th. WoTUG conference on concurrent and parallel systems, takes place from Sunday August 21st. to Wednesday August 24th. 2016 and is hosted by the Niels Bohr Institute, University of Copenhagen. Conference sessions will take place at the Hans Christian Ørsted Institute, which is located here. The evening Fringe sessions will be at the Caféen Bar, which is just a few minutes walk from the Ørsted buildings.

About WoTUG

WoTUG provides a forum for the discussion and promotion of concurrency ideas, tools and products in computer science. It organises specialist workshops and annual conferences that address key concurrency issues at all levels of software and hardware granularity. WoTUG aims to progress the leading state of the art in:

  • theory (programming models, process algebra, semantics, ...);
  • practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
  • education (at school, undergraduate and postgraduate levels, ...);
  • applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
  • for the next generation of scalable computer infrastructure (hard and soft) and application, where scaling means the ability to ramp up functionality (stay in control as complexity increases) as well as physical metrics (such as absolute performance and response times);
  • for system integrity (dependability, security, safety, liveness, ...);
  • for making things simple.
Of course, neither of the above sets of bullets are exclusive.

WoTUG publications

A database of papers and presentations from WoTUG conferences is here. The Abstract below has been randomly selected from this database.

SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces

By Arash Saifhashemi, Peter A. Beerel

This paper describes how to model channel-based digital asynchronous circuits using SystemVerilog interfaces that implement CSP-like communication events. The interfaces enable explicit handshaking of channel wires as well as abstract CSP events. This enables abstract connections between modules that are described at different levels of abstraction facilitating both verification and design. We explain how to model one-to-one, one-to-many, one-to-any, any-to-one, and synchronized channels. Moreover, we describe how to split communication actions into multiple parts to more accurately model less concurrent handshaking protocols that are commonly found in many asynchronous pipelines.

Complete record...


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