Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2017,
the 39th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 20th. to Wednesday August 23rd. 2017 and is hosted by the
Department of Computer Science at the
University of Malta.
Conference sessions will take place at the
Auditorium of the University of Malta, Valletta Campus.
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
and to stimulate discussion and ideas on the roles concurrency will play in the future:
theory (programming models, process algebra, semantics, ...);
practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
education (at school, undergraduate and postgraduate levels, ...);
applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
Of course, neither of the above sets of bullets are exclusive.
for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
for system integrity (dependability, security, safety, liveness, ...);
for making things simple.
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
Scheduling for ILP in the 'Processor-as-a-Network'
This paper explores the idea of the processor as an asynchronous network,called the micronet, of functional units which compute concurrently and communicateasynchronously. A micronet-based asynchronous processor exposes spatial as well astemporal concurrency. We analyse the performance of the ‘processor-as-a-network’by comparing three scheduling algorithms for exploiting Instruction Level Parallelism(ILP). Schedulers for synchronous architectures have relied on deterministic instructionexecution times. In contrast, ILP scheduling in micronet-based architectures is achallenge as it is less certain in advance when instructions start execution and whenresults become available. Performance results comparing the three schedulers are presentedfor SPEC95 benchmarks executing on a cycle-accurate model of the micronetarchitecture.