Communicating Process Architectures
Communicating Process Architectures 2014,
the 36th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 24th to Wednesday August 27th 2014 and is hosted by the
Department of Computer Science, University of Oxford.
Accommodation and evening Fringe sessions will be at
St. Anne's College,
a few minutes walk from the Department.
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
and to stimulate discussion and ideas on the roles concurrency will play in the future:
theory (programming models, process algebra, semantics, ...);
practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
education (at school, undergraduate and postgraduate levels, ...);
applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
Of course, neither of the above sets of bullets are exclusive.
for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
for system integrity (dependability, security, safety, liveness, ...);
for making things simple.
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
Virtual memory management for the transputer
During the last decade a number of microprocessors appeared on the market with operating system mechanisms designed into the firmware e.g. the Intel 80286 which supports segmented memory management and the 80386 supporting segmentation and paging. The idea was very attractive as protection amongst users could be enforced by the hardware. The support of multi-users on one processor implied the conventional strategy of sharing the scarce processor resource amongst more than one user. The limitations in processing power of microprocessors did however limit their multi-user exploitation.