WoTUG - The place for concurrent processes

Annual Conference: Communicating Process Architectures

Communicating Process Architectures 2018, the 40th. WoTUG conference on concurrent and parallel systems, takes place from Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by Professor Dr. Rainer Spallek, Chair of VLSI Design, Diagnostics and Architecture at the Faculty of Computer Science, Technische Universit├Ąt Dresden, Germany. The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke and in partnership with WoTUG.

About WoTUG

WoTUG provides a forum for the discussion and promotion of concurrency ideas, tools and products in computer science. It organises specialist workshops and annual conferences that address key concurrency issues at all levels of software and hardware granularity. WoTUG aims to progress the leading state of the art in:

  • theory (programming models, process algebra, semantics, ...);
  • practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
  • education (at school, undergraduate and postgraduate levels, ...);
  • applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
  • for the next generation of scalable computer infrastructure (hard and soft) and application, where scaling means the ability to ramp up functionality (stay in control as complexity increases) as well as physical metrics (such as absolute performance and response times);
  • for system integrity (dependability, security, safety, liveness, ...);
  • for making things simple.
Of course, neither of the above sets of bullets are exclusive.

WoTUG publications

A database of papers and presentations from WoTUG conferences is here. The Abstract below has been randomly selected from this database.

Programming the CELL-BE using CSP

By Kenneth Skovhede, Morten N. Larsen, Brian Vinter

The current trend in processor design seems to focus on using multiple cores, similar to a cluster-on-a-chip model. These processors are generally fast and power efficient, but due to their highly parallel nature, they are notoriously difficult to program for most scientists. One such processor is the CELL broadband engine (CELL-BE) which is known for its high performance, but also for a complex programming model which makes it difficult to exploit the architecture to its full potential. To address this difficulty, this paper proposes to change the programming model to use the principles of CSP design, thus making it simpler to program the CELL-BE and avoid livelocks, deadlocks and race conditions. The CSP model described here comprises a thread library for the synergistic processing elements (SPEs) and a simple channel based communication interface. To examine the scalability of the implementation, experiments are performed with both scientific computational cores and synthetic workloads. The implemented CSP model has a simple API and is shown to scale well for problems with significant computational requirements.

Complete record...

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