Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2017,
the 39th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 20th. to Wednesday August 23rd. 2017 and is hosted by
Kevin Vella, Head of Department in
at the University of Malta.
Conference sessions will take place at the
Victoria Hotel in Sliema, Malta.
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
and to stimulate discussion and ideas on the roles concurrency will play in the future:
theory (programming models, process algebra, semantics, ...);
practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
education (at school, undergraduate and postgraduate levels, ...);
applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
Of course, neither of the above sets of bullets are exclusive.
for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
for system integrity (dependability, security, safety, liveness, ...);
for making things simple.
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
A Programming Language for Hardware/Software Co-Design
We have developed a programming language that allows programs to be expressed as single specifications in which any number of processes may be tagged for hardware compilation and the rest are compiled into software. We introduce a number of novel transformations that may be arbitrarily applied to an occam process in order to decompose it into two semantically equivalent concurrent processes. Our compiler targets hardware by compiling one of these processes into a field programmable gate array and the other into x86 object code. Furthermore, the compiler integrates a specialised communications protocol between the two programs that consists of a full-duplex channel implementation, multiplexor and buffers that are dependent on the program structure and that guarantee all external communications are free from deadlock. We demonstrate the elegance of our language and the power of our compiler on a small benchmark program.