Communicating Process Architectures - 2000

Conference Themes and Goal

Communicating Process Architectures addresses many of the key issues in modern computer science and its application.  In broad terms, the conference themes will concern concurrency - at all levels of software and hardware granularity. The goal of the conference is to stimulate discussion and ideas as to the role concurrency will play in the future generation of scaleable computer infrastructure and applications - where scaling means the ability to ramp up functionality (i.e. stay in control as complexity increases) as well as physical metrics (such as performance).

Traditionally, concurrency has been taught and considered and experienced as an advanced and difficult topic. The thesis underlying this conference is that this tradition is wrong. The natural world operates through the continuous interaction of massive numbers of autonomous agents at all levels of granulartiy (astronomic, human, sub-atomic). If modern computer science finds concurrency hard, then it is not doing it right - discuss! It is time for concurrency to mature into a simple discipline that can be used everyday.

Conference Structure and Call for Delegates

Communicating Process Architectures will run a mix of submitted and invited papers during the day, with workshops and/or tutorials in the evenings. Submitted papers have been refereed by the Programme Committee. The conference proceedings will be published by IOS Press as part of their Concurrent Systems Engineering series.

The accepted papers address the conference themes and goals as discussed above. Specific areas include, but are not limited to:

• theory - getting the underlying model right (CSP, pi-calculus, channels, monitors, semaphores, BSP, barriers, buckets...);
• concurrent design patterns and tools (built upon the above);
• safety and security issues (race-hazards, deadlock, livelock, process starvation, ...);
• language issues (Java(TM), CSP libraries for Java/C/C++, occam(TM), Handel-C(TM), Limbo(TM), ...);
• system issues (lightweight multithreading kernels, lightweight external communications/interrupts, ...)
• processor issues (instruction sets for zero-cost multithreading, VLIW, multiprocessor chips, software cache control, ...)
• specialised hardware issues (link and router technologies, FPGAs, ...);
• shared-memory -v- message-passing paradigms (unification?), SMP and virtual SMP architectures;
• supercomputing from commodity components (cluster computing, internet grids, ...);
• applications: scientific (including graphics and GUIs), engineering (including embedded, real-time and safety-critical), business (including mobile and e-commerce) and home (including entertainment);
• global architectural issues (vertical integration of all the above);
• etc.

This conference is the 23rd. in the series of WoTUG conferences, which have consistently proven to be a valuable meeting place for all those interested in the problems and opportuinites thrown up by parallel computing and concurrency. The delegates and speakers reflect a wide spectrum of disciplines - theoreticians, software engineers, hardware engineers, tool builders and applications specialists - and we meet in a relaxed, exciting, friendly and highly productive atmosphere ... often till very late the next morning.

Registration Fees

The registration fee will be £310.00 sterling (no VAT chargeable). This includes:

• accommodation for the nights of the 10, 11, 12 September 2000;
• all meals, starting with the evening meal on Sunday night, through to Wednesday lunch;
• conference dinner;
• one copy of the conference proceedings.

Please follow this link to register.

Student Bursaries

WoTUG is sponsoring a limited number of Student Bursaries, worth £100 sterling. To qualify, you must be registered as a student at a Higher Education institution, not in receipt of a salary and obtain a supporting letter from your academic supervisor. Please fax this to the Conference Secretary before you register - you will be given a reference number to quote on your registration form.  The bursaries will be awarded in FIFO scheduling to qualifying applicants until they run out.

Conference Organiser and Secretary

Professor Peter Welch / Judith Broom
Computing Laboratory
The University
Canterbury
Kent
CT2 7NF
UK
Tel: +44 (0)1227 823629 / +44 (0)1227 827833
Email: P.H.Welch@ukc.ac.uk  / J.Broom@ukc.ac.uk

[Note: Peter Welch is on holiday from the 19th. August through the 4th. September. Judith Broom will be around to answer most questions you may be asking. For questions other than purely administrative, my colleague David Wood is standing by - David is (email) D.C.Wood@ukc.ac.uk and (tel) +44 1227 823814. Peter Welch, 18th. August, 2000.]

Programme Committee

• Professor David May FRS, University of Bristol, UK. (Patron)

• Professor Andre Bakkers, University of Twente, The Netherlands. (Co-Chair)
• Professor Peter Welch, University of Kent at Canterbury, UK. (Co-Chair)

• Dr. Alastair Allen, University of Aberdeen, UK.
• Professor Hamid Arabnia, University of Georgia, Athens, Georgia, USA.
• Richard Beton, Roke Manor Research Ltd., UK.
• Dr. Alan Chalmers, University of Bristol, UK.
• Professor Peter Clayton, Rhodes University, South Africa.
• Dr. Barry Cook, University of Keele, UK.
• Dr. Janet Edwards, Loughborough University of Technology, UK.
• Ruth A. Ivimey-Cook, ARM Ltd., Cambridge, UK
• Christopher Jones, British Aerospace, Warton Aerodrome, UK.
• Professor Jon Kerridge, Napier University, UK
• Stephen Maudsley, Esgem Ltd, UK.
• Professor Chris Nevison, Colgate University, New York, USA.
• Professor Patrick Nixon, University of Strathclyde, UK.
• Dr. Brian O'Neill, Nottingham Trent University, UK.
• Dr. Roger Peel, University of Surrey, UK
• Dr. Michael Poole, Consultant, UK.
• Professor Nan Schaller, Rochester Institute of Technology, New York, USA.
• Professor G. S. Stiles, Utah State University, Utah, USA.
• Øyvind Teig, Navia Maritime AS, Division Autronica, Norway.
• Professor Rod Tosten, Gettysburg University, USA.
• Dr. Stephen J Turner, Nanyang Technological University, Singapore.
• Professor Paul Tymann, Rochester Institute of Technology, New York, USA.
• Paul Walker, 4Links Ltd, UK.
• Dr. Hugh Webber, Defence Evaluation Research Agency, Malvern, UK.

Published Proceedings

The Proceedings will be published by IOS Press, Netherlands as part of the Concurrent Systems Engineering Series (ISSN 1383-7575).
Style sheets for papers for CPA-2000, including LaTeX and MS Word templates, will be available to authors of accepted papers.

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occam is a Trademark of SGS-Thomson Microelectronics Inc.
Limbo is a Trademark of Lucent Technologies Inc.
other trademarks are acknowledged