SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces
Authors: Saifhashemi, Arash, Beerel, Peter A.
Abstract:This paper describes how to model channel-based digital asynchronous circuits using SystemVerilog interfaces that implement CSP-like communication events. The interfaces enable explicit handshaking of channel wires as well as abstract CSP events. This enables abstract connections between modules that are described at different levels of abstraction facilitating both verification and design. We explain how to model one-to-one, one-to-many, one-to-any, any-to-one, and synchronized channels. Moreover, we describe how to split communication actions into multiple parts to more accurately model less concurrent handshaking protocols that are commonly found in many asynchronous pipelines.
Communicating Process Architectures 2011, Peter H. Welch, Adam T. Sampson, Jan Baekgaard Pedersen, Jon Kerridge, Jan F. Broenink, Frederick R. M. Barnes, 2011, pp 287 - 302 published by IOS Press, AmsterdamFiles: Paper (PDF), Slides (PDF)
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