Design of a Transputer Core and Implementation in an FPGA
Authors: Tanaka, Makoto, Fukuchi, Naoya, Ooki, Yutaka, Fukunaga, Chikara
We have made an IP (Intellectual Property) core for the T425 transputer. The same machine instructions as the transputer are executable in this IP core (we call it TPCORE). To create an IP code for the transputer has two aspects. On one hand, if we could succeed in building our own one and put it in an FPGA, we could apply it as a core processor in a distributed system. We also intend to put it in a VLSI chip. On the other hand, if we can extend our transputer development starting from a very conventional one to more sophisticated ones, as Inmos proceeded to the T9000, we will eventually find our technological breakthrough for the bottlenecks that the original transputer had, such as the restriction of the number of communication channels. It is important to have an IP core for the transputer. Although TPCORE uses the same register set with the same functionality as transputer and follows the same mechanisms for link communication between two processes and interrupt handling, the implementation must be very different from original transputer. We have extensively used the micro-code ROM to describe any states that TPCORE must take. Using this micro code ROM for the state transition description, we could implement TPCORE economically on FPGA space and achieve efficient performance.
Communicating Process Architectures 2004, Ian R. East, David Duce, Mark Green, Jeremy M. R. Martin, Peter H. Welch, 2004, pp 361 - 372 published by IOS Press, AmsterdamFiles: PDF
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