WoTUG - The place for concurrent processes

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  title = "{M}essage routing systems for transputer based parallel computers",
  author= "Talia, Domenico",
  editor= "Allen, Alastair R.",
  pages = "1--12",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "An efficient communication system is an essential component
     of a transputer-based parallel computer. In the last years
     many message routing systems for transputer networks have
     been developed. They allow data exchanging among processes
     mapped on transputers not directly connected. This paper
     surveys and compares some of these routing systems with
     respect to several criteria, such as deadlock freedom,
     adaptivity, network latency, livelock freedom, and
  title = "{A}n environment for investigating the effectiveness of process migration strategies on transputer-based machines",
  author= "Philips, Joe and Candlin, Rosemary",
  editor= "Allen, Alastair R.",
  pages = "13--23",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "This paper describes an experimental system which can be
     used to study and compare the behaviour of different process
     migration strategies for occam programs running on
     transputer machines. The approach taken involves loading the
     code and data for every process onto every transputer.
     Processes can then be enabled and disabled to reflect the
     initial placement and subsequently to reflect process
     migrations. While simplifying the implementation process
     this means that the entire program must fit onto a single
     transputer. A statistics collection mechanism has also been
     implemented to enable intelligent migration decisions to be
     made. The system has been verified using a random migration
     strategy on several candidate programs."
  title = "{E}valuation of a set of message- passing routines on transputer networks",
  author= "Cai, Wentong and Skillicorn, David B.",
  editor= "Allen, Alastair R.",
  pages = "24--36",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "A major obstacle to the use of parallel computers in
     ordinary applications, where their price/performance ratio
     should make them attractive, is the sheer difficulty of
     parallel programming. One approach which can ease the
     difficulties is data parallel programming, because of the
     simplicity of a single-threaded flow of control. Data
     parallelism also expresses parallelism with enough
     regularity to be readily implemented across a range of
     machine types. In this paper, we describe a data parallel
     model based on a set of second order functions from the
     Bird-Meertens theory of lists, demonstrate the
     implementation of these functions as a set of
     message-passing routines, and evaluate their performance on
     transputer networks configured as hy-percubes."
  title = "{P}erformance modelling of a parallel meural network simulator",
  author= "Tollenaere, Tom and Roose, Dirk",
  editor= "Allen, Alastair R.",
  pages = "37--48",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "A model program structure is presented for parallel
     applications with local interactions between the data
     elements, such as neural networks simulations and the
     solution of partial differential equations. The performance
     of this model program is analyzed both theoretically by
     means of classical performance models, and experimentally
     using a parallel neural network simulator program. The
     program runs on a Meiko transputer array, and uses the Meiko
     CSTools libraries for its communications. The comparison of
     both analyses allows to predict applications performance on
     new and other machines, and indicate what parts of an
     application are worth optimizing. Moreover, it is shown that
     classical theoretical models not always capture the behavior
     of a real machine."
  title = "{F}arming: {T}owards a rigorous definition and efficient transputer implementation",
  author= "Day, Warren",
  editor= "Allen, Alastair R.",
  pages = "49--62",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "The technique of the processor farm has become a very widely
     used for parallelising applications, often being mentioned
     without reference to any source.The goal of this work has
     been to put together a complete and rigorous understanding
     of what the technique can be used for and what is needed in
     order to arrive at an efficiently farmed application. This
     paper consists of these two parts.We have shown, via the
     UNITY theory of programming, that the basic structure of the
     processor farm may be used to parallelise a much wider
     domain of applications than has generally been
     considered.Second, we show by example, how to build
     efficient implementations for the first generation of INMOS
     Transputers. This work is new in that it is the first that
     has been able to test farming harnesses by taking an
     abstract view of the application.This paper has been written
     in a semi-\"instruction manual\"\" style.
     Also it should serve as an introduction to the subject."
  title = "{P}orting the 3{L} {P}arallel {C} environment to the {T}exas {I}nstruments {TMS}320{C}40",
  author= "Culloch, Alan D.",
  editor= "Allen, Alastair R.",
  pages = "63--76",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "The TMS320C40 ('C40) is a transputer-like parallel processor
     from Texas Instruments. It is an order of magnitude faster
     than the T800 transputer. Parallel C is a popular
     programming environment for the transputer. The properties
     of both the 'C40 and Parallel C are described and the
     significant differences between the 'C40 and the transputer
     are pointed out. The techniques used to overcome these
     obstacles to porting Parallel C are presented. These include
     building a new real-time kernel and reusing existing
     software packages from industry and academia. The
     suitability of the 'C40 for parallel applications is
  title = "{T}ransputer based adaptive signal processing",
  author= "Soragham, John J. and Gan, Woon S. and Goh, Kwong H. and Stewart, Robert W. and Durrani, Tariq S.",
  editor= "Allen, Alastair R.",
  pages = "77--96",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "Transputer based adaptive signal processing systems are
     considered. Efficient use of data communication networks
     requires adaptive equaliser structures that are efficient
     and have fast mean square error (MSE) convergence rates. The
     transputer based non-canonical least mean square (NCLMS)
     algorithm is implemented using a variant of the standard
     finite impulse response (FIR) filter,called the
     non-canonical FIR (NCFIR). Simulation results are given
     which show areduced excess mean square error level and an
     improved performance in an impulsive noise environment for
     the NCLMS over the conventional least mean square (LMS)
     algorithm. Simulation results comparing the LMS and NCLMS
     are presented.The equaliser structure based on the Kalman
     Filter has convergence rates that are independent of the
     channel's characteristics. A transputer based Kalman
     Equaliser and fast Kalman Equaliser are described. Speed-up
     curves for a variety of topologies for both systems are
  title = "{A} transform accelerator for a transputer system",
  author= "Dodge, C. J. and Ross, P. G. B. and Undrill, P. E. and Allen, Alastair R.",
  editor= "Allen, Alastair R.",
  pages = "97--111",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "A DSP based image transform accelerator for a transputer
     system is described. The formal specification language Z has
     been employed in the accelerator design, examples of which
     are presented including aspects of the refinement process
     and some of the problems encountered in working with a
     combined hardware/software specification."
  title = "{A} transputer based active vision system",
  author= "Smith, Andrew B. and Welch, Peter H.",
  editor= "Allen, Alastair R.",
  pages = "112--121",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "The visual detection and tracking of moving targets is
     computationally intensive and any but the most simple tasks
     are beyond the ability of single processor architectures.
     Many algorithms that are parallel in nature have been
     suggested for the recognition and tracking of moving
     targets. Implementing these algorithms on parallel computer
     systems requires the transcription of a massively parallel
     architecture onto a system with fewer physical processors.
     This, of course, is a much easier transformation than the
     reverse process: distributing a serial algorithm effectively
     over multiple processing elements.This paper describes a
     parallel Transputer implementation of a vision tracking
     system. The system is able to track a designated target by
     the physical movement of the camera. The camera is mounted
     on a pan and tilt unit and its movement and lens are under
     full control of the system. The system is modular in nature
     having been designed in three stages: i) the pre-processing
     of the image and extraction of edge information, ii) the
     control of the focus and gain of the lens, and iii) the
     detection and tracking of moving targets. The system
     operates in real-time (i.e. 25 frames/second)."
  title = "{SYDAMA}-2: a heterogeneous multiprocessor system for real time image processing",
  author= "Stokar, Dieter",
  editor= "Allen, Alastair R.",
  pages = "122--128",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "In this paper we will present the architecture of SYDAMA-2
     and its programming environment as well as early experiences
     gained in developing applications with it. The goal of this
     project was to find and develop an architecture that was
     capable of executing entire applications in the domain of
     real time image processing. The architecture consists of two
     parts: one for low level preprocessing and one for
     intermediate and high level postprocessing.The preprocessing
     subsystem is based on the direct mapping of static dataflow
     graphs onto hardware. While highly specialized processing
     elements can be implemented for reasons of efficiency most
     of them consist of lookup tables for the sake of their
     processing speed and flexibility. All of them are controlled
     by a transputer that does the housekeeping.The processing
     elements are interconnected through a communication network
     which is realized as a pipelined multichannel ringbus that
     is fully reconfigurable on the fly. The bandwidth is large
     enough to carry several video streams and because the buses
     can be subdivided at every stage, the overall bandwidth
     effectively scales with the number of stages (processing
     elements).The postprocessing subsystem consists of a
     standard off the shelf transputer network that is closely
     connected to the low level subsystem.The programming
     environment consists of a number of tools that cover the
     different stages of programming an application: The low
     level programming interface for the image processing
     subsystem, a configuration tool and the runtime support that
     controls and interconnects the different tasks."
  title = "{G}eneral purpose parallel computers: a standard architecture with a standard programming interface",
  author= "Barrett, Geoff and Barton, Eric and Carden, Trevor and Duval, Dominique and Nicole, Denis A.",
  editor= "Allen, Alastair R.",
  pages = "129--138",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "Recent developments in the area of high performance
     computing are pointing the way to a standard architecture
     for parallel computers. This architecture contains a number
     of medium-cost processing elements which communicate with
     each other through a high-bandwidth, low-latency
     interconnect. The design of the interconnect eliminates the
     concerns of \"locality\" which are current in the
     programming of present-day machines. This \"flat\"
     topology and common architectural model lead to increased
     opportunities for establishing portable software for high
     performance computing. The Esprit GP-MIMD project has
     exploited these opportunities by developing the
     architectural model and denning a programming interface for
     software which runs efficiently on machines with a range of
     processing power."
  title = "{A}n efficient multi- priority scheduler for the transputer",
  author= "Shea, K. M. and Cheung, M. H. and Lau, Francis C. M.",
  editor= "Allen, Alastair R.",
  pages = "139--153",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "Multi-priority scheduling is essential in a spectrum of
     applications especially those involving real time. We have
     extended the hardware scheduler in the transputer to support
     multi-priority scheduling. We did it by implementing a layer
     of provably safe and efficient queue manipulation primitives
     and a \"plug-in\" data structure for process
     queueing on top of the original scheduler. For optimal
     performance, different data structures for queueing may be
     plugged into our scheduler to suit different application
     domains. We tested our scheduler with different process
     loads (up to 200 processes) and the performance is
     excellent: overhead due to the scheduler accounts for less
     than 1\% of a timeslice on a T8."
  title = "{T}owards an adaptable scheduler for real-time system",
  author= "Moron, Celio Estevan and Zedan, Hussein S. M.",
  editor= "Allen, Alastair R.",
  pages = "154--166",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "Issues for designing adaptable real-time scheduler are
     discussed. A general approach that utilises milestones [1]
     is given and illustrated using the Least Laxity Algorithm.
     Some performance results are also given (in the form of
     upper bound of the overhead)."
  title = "{TCP}/{IP} on transputers -- the performance implications",
  author= "Peel, Roger M. A.",
  editor= "Allen, Alastair R.",
  pages = "167--179",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "At the 14th WoTUG Technical Meeting at Loughborough
     University in September 1991, Graeme Tozer from INMOS
     described the architecture of the IMS B300 Ethernet
     Interface. This product supports four external transputer
     networks, providing each with an Iserver interface to
     Ethernet and connectivity to a host Iserver running on a
     processor elsewhere on the Ethernet. Performance claims in
     the range 200-300 kbytes per second were made for raw TCP
     transfers between a typical Unix workstation and transputers
     networked to it using the B300. This paper outlines the
     techniques which the author has used recently to enhance the
     performance of his own pipelined TCP/IP implementation for
     Ethernet to achieve throughputs of up to 925 kbytes per
     second on substantially similar hardware. Many of these
     techniques are equally appropriate to any large
     communicating process application."
  title = "{A} transputer-based accelerator for digital circuits fault simulation",
  author= "Balboni, G. P. and Cabodi, G. P. and Gai, S. and Reorda, M. Sonza",
  editor= "Allen, Alastair R.",
  pages = "180--186",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "Fault simulating digital devices requires powerful tools
     able to deal with their increased size and complexity.
     Software simulators are often unable to satisfy the needs of
     designers and test engineers due to the size of the
     simulated circuits, and to the large number of faults;
     hardware accelerators have been proposed to solve the
     problem. We present a system running on a net of transputers
     which uses a fault-partitioning strategy to fully exploit
     the available processors. The results show that this
     solution can represent a good trade-off between the cost of
     the system and the obtained speed-up."
  title = "{F}ormal methods in the design of the {T}9000",
  author= "Barrett, Geoff and May, David and Shepard, D.",
  editor= "Allen, Alastair R.",
  pages = "187--204",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "The complexity of integrated circuits continues to grow, and
     chips with over 100,000,000 transistors will be in
     widespread use by the late 1990s. These chips will combine
     general purpose processors with subsystems for
     communications and other specialised tasks. They will be far
     too complex for the design to be tested, and manufacturing
     volumes will be far too high for the design to be
     wrong!Mathematical techniques have already been applied to
     the design of parts of VLSI chips. Most of this work is
     experimental, and requires an unusual combination of
     engineering, mathematical and programming skills. Sometimes
     new theoretical work is needed, and specialised tools may
     have to be constructed. Despite these difficulties,
     mathematical techniques are playing an important role in the
     design of microprocessors at INMOS and techniques suitable
     for incorporation in standard computer-aided design systems
     are emerging."
  title = "{H}ow to achieve replication within a {CASE} tool environment",
  author= "Manson, Gordon A. and Cachia, E. A. and Boyle, A.",
  editor= "Allen, Alastair R.",
  pages = "205--217",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "A CASE tool, called ParStP, has been developed at the
     University of Sheffield. ParStP is built on top an existing
     open CASE tool called Software through Pictures and it
     combines design, compilation, running, testing and
     documentation into one integrated system. This paper shows
     how ParStP is being extended to cope with replication."
  title = "{T}he {PARIX} pregramming environment",
  author= "GmBH., Parsytec",
  editor= "Allen, Alastair R.",
  pages = "218--230",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "The new Parsytec GC is a high-performance parallel
     processing system for scientific and technical
     applications.Between 64 and 16,384 processors provide a
     computational performance from 1 to 400 GigaFlops (peak
     performance, double precision, 190 GigaFlops sustained,
     double precision) thus meeting even the most extreme
     demands.In the software environment PARIX, users work with
     standard compilers for Fortran and C, make use of
     UNIXdevelopment tools and libraries and have
     high-performance systems for I/O, backup, graphics and
     video.The Parsytec GC is based on Inmos T9000 processors
     which can be structured into random topologies and which
     communicate both, the Inmos T800/T805 and the, at a maximal
     rate of 80 MBytes/s."
  title = "{A}n {O}ptimised {P}arallel {C}ompiler for {E}xecuting {D}eclarative {P}rograms on {T}ransputer {A}rray",
  author= "Dingxing, Wang and Xinmin, Tian and Weimin, Zheng and Meiming, Shen and Dongchan, Wen",
  editor= "Allen, Alastair R.",
  pages = "231--245",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "Many Declarative Programming Languages (DPLs) such as KL1,
     Prolog, PARLOG, Miranda and SML are considered attractive
     candidates for artificial intelligent application and
     execution on parallel architecture. However, there are many
     issues such as compile-time granularity analysis, partial
     evalution, task scheduling and load balancing for the
     efficient implementations of DPLs on multiprocessor system.
     In this paper, we take the emphasis on the compiling
     implementation of PARLOG and SML on a distributed memory
     multiprocessor system (transputer array). Under the graph
     rewriting framework, a Heterogeneous Parallel Graph Rewritng
     Execution Model (HPGREM) and corresponding description
     Language CIL are proposed. Based on the HPGREM, a parallel
     abstract machine PAM /TGR (Parallel Abstract Machine for
     Term Graph Rewriting) and corresponding compilation rules to
     generate PAM/TGR code are presented. Futhcrmore, an
     optimised parallel compiler for executing declarative
     programs on transputer array is described. The performance
     statistic on a 16-nodes transputer array demonstrates the
     effectiveness of our model, compiling techniques and
  title = "{I}mplementation of learning automata games on a 128-transputer reconfigurable machine using {VCR}1.8c ({V}irtual {C}hannel {R}outer)",
  author= "Seredynski, Franciszek and Kitajima, Jo\~{a}o Paulo and Plateau, Brigitte",
  editor= "Allen, Alastair R.",
  pages = "246--250",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "An implementation of learning automata games on a
     distributed memory message-passing reconfigurable
     multiprocessor with 128 Transputers is presented. The game
     is played using a conjugate exchange process in order to
     transform the maximal price point into the Nash point. The
     game was implemented in Occam2 with Virtual Channel Router
     (VCR), a router developed at the University of Southampton."
  title = "{N}onconvex continuous optimization experiments on a transputer system",
  author= "Laak, A. ter and Hertzberger, L. O. and Sloot, P. M. A.",
  editor= "Allen, Alastair R.",
  pages = "251--265",
  booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn= "90 5199 085 5",
  year= "1992",
  month= "mar",
  abstract= "In this paper we investigate the functionality of various
     parallel implementations of Simulated Annealing on a
     transputer platform. The optimization problem to be solved
     is that of efficiently finding the global minimum in
     continuous spaces. Our work concentrates on the consequences
     of long-range and short-range interactions on algorithmic
     and geometric decomposition schemes. We introduce a mixed
     transputer topology to by-pass some of the inherent time
     critical operations involved. We show that combining the
     Fast Simulated Annealing algorithm with a systolic
     decomposition strategy results in a highly efficient
     algorithm for continuous optimization problems. Experiments
     indicate that incorporation of functional decomposition of
     the energy function results in a near optimal

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