WoTUG - The place for concurrent processes

Paper Details

%T An Evaluation of Intel\[rs]s Restricted Transactional Memory for CPAs
%A Carl G. Ritson, Frederick R. M. Barnes
%E Peter H. Welch, Frederick R. M. Barnes, Jan F. Broenink, Kevin Chalmers, Jan Bækgaard Pedersen, Adam T. Sampson
%B Communicating Process Architectures 2013
%X With the release of their latest processor
   microarchitecture, codenamed Haswell, Intel added new
   Transactional Synchronization Extensions (TSX) to their
   processors\[rs] instruction set. These extensions include
   support for Restricted Transactional Memory (RTM), a
   programming model in which arbitrary sized units of memory
   can be read and written in an atomic manner. This paper
   describes the low\-level RTM programming model, benchmarks
   the performance of its instructions and speculates on how it
   may be used to implement and enhance Communicating Process

If you have any comments on this database, including inaccuracies, requests to remove or add information, or suggestions for improvement, the WoTUG web team are happy to hear of them. We will do our best to resolve problems to everyone's satisfaction.

Copyright for the papers presented in this database normally resides with the authors; please contact them directly for more information. Addresses are normally presented in the full paper.

Pages © WoTUG, or the indicated author. All Rights Reserved.
Comments on these web pages should be addressed to: www at wotug.org

Valid HTML 4.01!