%T A High Performance Reconfigurable Architecture for Flash File Systems
%A Irfan Mir, Alistair A. McEwan, Neil J. Perrins
%E Peter H. Welch, Frederick R. M. Barnes, Kevin Chalmers, Jan Bækgaard Pedersen, Adam T. Sampson
%B Communicating Process Architectures 2012
%X NAND flash memory is widely adopted as the primary storage
medium in embedded systems. The design of the flash
translation layer, and exploitation of parallel I/O
architectures, are crucial in achieving high performance
within a flash file system. In this paper we present our new
FPGA based flash management framework using
reconfigurable computing that supports high performance
flash storage systems. Our implementation is in Verilog, and
as such enables us to design a highly concurrent system at a
hardware level in both the flash translation layer and the
flash controller. Results demonstrate that implementing the
flash translation layer and flash controller directly in
hardware, by exploiting reconfigurable computing, permits us
to exploit a highly concurrent architecture that leads to
fast response times and throughput in terms of read/write
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