WoTUG - The place for concurrent processes

Paper Details

%T Hardware/Software Synthesis and Verification Using Esterel
%A Satnam Singh
%E Alistair A. McEwan, Steve Schneider, Wilson Ifill, Peter H. Welch
%B Communicating Process Architectures 2007
%X The principal contribution of this paper is the
   demonstration of a promising technique for the synthesis of
   hardware and software from a single specification which is
   also amenable to formal analysis. We also demonstrate
   how the notion of synchronous observers may provide a way
   for engineers to express formal assertions about circuits
   which may be more accessible then the emerging grammar
   based approaches. We also report that the semantic basis for
   the system we evaluate pays dividends when formal static
   analysis is performed using model checking.

If you have any comments on this database, including inaccuracies, requests to remove or add information, or suggestions for improvement, the WoTUG web team are happy to hear of them. We will do our best to resolve problems to everyone's satisfaction.

Copyright for the papers presented in this database normally resides with the authors; please contact them directly for more information. Addresses are normally presented in the full paper.

Pages © WoTUG, or the indicated author. All Rights Reserved.
Comments on these web pages should be addressed to: www at wotug.org

Valid HTML 4.01!