Paper Details

%T Scheduling for ILP in the \[rs]Processor\-as\-a\-Network\[rs]
%A D.K. Arvind, S. Sotelo-Salazar
%E Jan F. Broenink, Gerald H. Hilderink
%B Communicating Process Architectures 2003
%X This paper explores the idea of the processor as an
   asynchronous network,called the micronet, of functional
   units which compute concurrently and
   communicateasynchronously. A micronet\-based asynchronous
   processor exposes spatial as well astemporal concurrency. We
   analyse the performance of the
   ‘processor\-as\-a\-network’by comparing three scheduling
   algorithms for exploiting Instruction Level
   Parallelism(ILP). Schedulers for synchronous architectures
   have relied on deterministic instructionexecution times. In
   contrast, ILP scheduling in micronet\-based architectures is
   achallenge as it is less certain in advance when
   instructions start execution and whenresults become
   available. Performance results comparing the three
   schedulers are presentedfor SPEC95 benchmarks executing on a
   cycle\-accurate model of the micronetarchitecture.

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