Paper Details

%T An Algorithm for Caching Software to Configurable Hardware
%A J. D. Campbell
%E Barry M. Cook
%B Proceedings of WoTUG\-22: Architectures, Languages and Techniques for Concurrent Systems
%X In the same fashion that a memory cache arranges for machine
   instructions and data that are frequently accessed to
   operate from high speed memory, the functionality cache
   installs hardware implementations of frequently executed
   code sequences in reconfigurable hardware. Code sequences
   become candidates for instantiation as hardware if the
   benefits outweigh the costs over some accounting period.
   Algorithms are provided for converting sequences of stack
   manipulations characteristic of executable Java programs
   into systolic processing circuitry and mapping that
   machinery into networks of FPGAs (Field Programmable Gate
   Arrays).

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