Paper Details

%T A transputer\-based accelerator for digital circuits fault simulation
%A G. P. Balboni, G. P. Cabodi, S. Gai, M. Sonza Reorda
%E Alastair R. Allen
%B Proceedings of WoTUG\-15: Transputer Systems \- ongoing Research
%X Fault simulating digital devices requires powerful tools
   able to deal with their increased size and complexity.
   Software simulators are often unable to satisfy the needs of
   designers and test engineers due to the size of the
   simulated circuits, and to the large number of faults;
   hardware accelerators have been proposed to solve the
   problem. We present a system running on a net of transputers
   which uses a fault\-partitioning strategy to fully exploit
   the available processors. The results show that this
   solution can represent a good trade\-off between the cost of
   the system and the obtained speed\-up.

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