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Paper Details

  title = "{A}n {E}valuation of {I}ntel's {R}estricted {T}ransactional {M}emory for {CPA}s",
  author= "Ritson, Carl G. and Barnes, Frederick R. M.",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan B√¶kgaard and Sampson, Adam T.",
  pages = "271--292",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013",
  isbn= "978-0-9565409-7-3",
  year= "2013",
  month= "nov",
  abstract= "With the release of their latest processor
     microarchitecture, codenamed Haswell, Intel added new
     Transactional Synchronization Extensions (TSX) to their
     processors' instruction set. These extensions include
     support for Restricted Transactional Memory (RTM), a
     programming model in which arbitrary sized units of memory
     can be read and written in an atomic manner. This paper
     describes the low-level RTM programming model, benchmarks
     the performance of its instructions and speculates on how it
     may be used to implement and enhance Communicating Process

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