Paper Details

@InProceedings{SaifhashemiBeerel11,
  title = "{S}ystem{V}erilog{CSP}: {M}odeling {D}igital {A}synchronous {C}ircuits {U}sing {S}ystem{V}erilog {I}nterfaces",
  author= "Saifhashemi, Arash and Beerel, Peter A.",
  editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.",
  pages = "287--302",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011",
  isbn= "978-1-60750-773-4",
  year= "2011",
  month= "jun",
  abstract= "This paper describes how to model channel-based digital
     asynchronous circuits using SystemVerilog interfaces that
     implement CSP-like communication events. The interfaces
     enable explicit handshaking of channel wires as well as
     abstract CSP events. This enables abstract connections
     between modules that are described at different levels
     of abstraction facilitating both verification and design. We
     explain how to model one-to-one, one-to-many, one-to-any,
     any-to-one, and synchronized channels. Moreover, we describe
     how to split communication actions into multiple parts to
     more accurately model less concurrent handshaking protocols
     that are commonly found in many asynchronous pipelines."
}

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