Paper Details

@InProceedings{Athaide08,
  title = "{S}hared-{C}lock {M}ethodology for {T}ime-{T}riggered {M}ulti-{C}ores",
  author= "Athaide, Keith F. and Pont, Michael J. and Ayavoo, Devaraj",
  editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.",
  pages = "149--162",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008",
  isbn= "978-1-58603-907-3",
  year= "2008",
  month= "sep",
  abstract= "The co-operative design methodology has significant
     advantages when used in safety-related systems. Coupled with
     the time-triggered architecture, the methodology can result
     in robust and predictable systems. Nevertheless, use of a
     co-operative design methodology may not always be
     appropriate especially when the system possesses
     tight resource and cost constraints. Under relaxed
     constraints, it might be possible to maintain a co-operative
     design by introducing additional software processing cores
     to the same chip. The resultant multi-core microcontroller
     then requires suitable design methodologies to ensure that
     the advantages of time-triggered co-operative design
     are maintained as far as possible. This paper explores the
     application of a time-triggered distributed-systems
     protocol, called
     \textlessq\textgreatershared-clock\textless/q\textgreater, on
     an eight-core microcontroller. The cores are connected in
     a mesh topology with no hardware broadcast capabilities and
     three implementations of the shared-clock protocol are
     examined. The custom multi-core system and the network
     interfaces used for the study are also described. The
     network interfaces share higher level serialising logic
     amongst channels, resulting in low hardware overhead when
     increasing the number of channels."
}

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