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Paper Details

  title = "{A}n {A}lgorithm for {C}aching {S}oftware to {C}onfigurable {H}ardware",
  author= "Campbell, J. D.",
  editor= "Cook, Barry M.",
  pages = "77--86",
  booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems",
  isbn= "90 5199 480 X",
  year= "1999",
  month= "mar",
  abstract= "In the same fashion that a memory cache arranges for machine
     instructions and data that are frequently accessed to
     operate from high speed memory, the functionality cache
     installs hardware implementations of frequently executed
     code sequences in reconfigurable hardware. Code sequences
     become candidates for instantiation as hardware if the
     benefits outweigh the costs over some accounting period.
     Algorithms are provided for converting sequences of stack
     manipulations characteristic of executable Java programs
     into systolic processing circuitry and mapping that
     machinery into networks of FPGAs (Field Programmable Gate

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