Paper Details

Using CSP to Verify Aspects of an Occam-to-FPGA Compiler

Authors: Peel, Roger M. A., Javier, Wong Han Feng

Abstract:

This paper reports on the progress made in developing techniques for the verification of an occam to FPGA compiler.The compiler converts occam programs into logic circuits that are suitable for loading into field-programmable gate arrays (FPGAs). Several levels of abstraction of these circuits provide links to conventional hardware implementations. Communicating Sequential Processes (CSP) has then been used to model these circuits. This CSP has been subjected to tests for deadlock and livelock freedom using the Failures-Divergence Refinement tool (FDR). In addition, FDR has been used to prove that the circuits emitted have behaviours equivalent to CSP specifications of the original occam source codes.

Proceedings:

Communicating Process Architectures 2004, Ian R. East, David Duce, Mark Green, Jeremy M. R. Martin, Peter H. Welch, 2004, pp 339 - 352 published by IOS Press, Amsterdam

Files: PDF

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