A 40 Gbit/s Network Processor Design Platform
Authors: McConnell, R., Winser, P.
As the Internet evolves, the rapidly increasing demand for bandwidth is matched by a greater need for more intelligence with which to manage and meter the flow of that data to sustain economic growth. Conventional processing architectures and hardwired point solutions are not suited to these conflicting demands; there is an emerging need for a new approach for this data flow processing problem. This paper presents ClearSpeed's integrated Network Processor design platform that embodies many different levels of parallel processing. Designed to balance the bandwidth needs with programmability we introduce the MTAP architecture. An area and power efficient, fine-grained, scalable, multi-threaded parallel processor, designed with a 'bandwidth-centric' architecture and programmed in C. Based on the ClearConnect™ bus, an SoC communication architecture with VCI compliant interfaces, a high-bandwidth system architecture including a number of hardware accelerator units is also described. An example 40Gbit/s programmable and scalable classifier/forwarder is presented, embodying the concepts of the platform. To complete the picture, a comprehensive suite of software and hardware development tools is described.
Communicating Process Architectures 2001, Alan G. Chalmers, Majid Mirmehdi, Henk Muller, 2001, pp 193 - 212 published by IOS Press, Amsterdam
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