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An Optimised Parallel Compiler for Executing Declarative Programs on Transputer Array

Authors: Dingxing, Wang, Xinmin, Tian, Weimin, Zheng, Meiming, Shen, Dongchan, Wen


Many Declarative Programming Languages (DPLs) such as KL1, Prolog, PARLOG, Miranda and SML are considered attractive candidates for artificial intelligent application and execution on parallel architecture. However, there are many issues such as compile-time granularity analysis, partial evalution, task scheduling and load balancing for the efficient implementations of DPLs on multiprocessor system. In this paper, we take the emphasis on the compiling implementation of PARLOG and SML on a distributed memory multiprocessor system (transputer array). Under the graph rewriting framework, a Heterogeneous Parallel Graph Rewritng Execution Model (HPGREM) and corresponding description Language CIL are proposed. Based on the HPGREM, a parallel abstract machine PAM /TGR (Parallel Abstract Machine for Term Graph Rewriting) and corresponding compilation rules to generate PAM/TGR code are presented. Futhcrmore, an optimised parallel compiler for executing declarative programs on transputer array is described. The performance statistic on a 16-nodes transputer array demonstrates the effectiveness of our model, compiling techniques and compiler.


Proceedings of WoTUG-15: Transputer Systems - ongoing Research, Alastair R. Allen, 1992, pp 231 - 245 published by IOS Press, Amsterdam

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