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| Machine type | Distributed-memory multi-processor |
|---|---|
| Models | TA9800 (TA9400, TA9500) |
| Operating system | Idris (a real-time sub-Unix variant) |
| Connection structure | Multi-stage crossbar |
| Compilers | Extended Fortran 77, ANSI C, Pascal, Modula 2 |
System parameters:
| Model | TA9800 |
|---|---|
| Clock cycle | 4.3 ns |
| Theor. peak performance | |
| Per Proc. (32 bits) | 233 Mflop/s |
| Maximal (32 bits) | 119.3 Gflop/s |
| Main memory | <=32 |
| Memory/node | <=64 |
| Communication bandwidth | 25 MB/s/link |
| No. of processors | <=512 |
Remarks:
The Parsys TransAlpha TA9000 series systems are the successors of the Parsys SN9000 machines. The latter had the Thomson T9000 transputer as their basic processors. The new TA9000 systems use the DEC Alpha 21066 transputers for that purpose.
The TA9000 is roughly 10 times faster than its predecessor, the SN9000, which had a maximal speed of roughly 25 Mflop/s per node. However the communication speed has remained the same still using T9000 transputers for the internode communication. The use of the T9000 as a communication engine enables employment of the fast C104 communication switch. The same multistage crossbar switch is also used in the Meiko CS-2 (see 3.4.12) and allows for very good latency and bandwidth characteristics (although at this stage no figures are available to show how much of these are realised).
Apart from the largest model, the SN9800, there are smaller models, like the desktop models SN9400 and SN9500. The latter houses up to 12 processors and can be driven either as a Sun SparC back-end system or as a network device via Ethernet. An optimised PVM library is available for standard message passing programs.
Measured Performances: Although the TransAlpha machines were announced and available from May 1995, until now no measured performances are known to the author.
Copyright © 1996 Aad J. van der Steen and Jack J. Dongarra
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