%T Architecture Design Space Exploration for Streaming Applications through Timing Analysis
%A  Maarten H. Wiggers,  Nikolay Kavaldjiev,  Gerard J. M. Smit,  Pierre G. Jansen
%E  Jan F. Broenink,  Herman Roebbers,  Johan P. E. Sunter, Peter H. Welch,  David C. Wood
%B Communicating Process Architectures 2005
%X In this paper we compare the maximum achievable throughput
   of different memory organisations of the processing elements
   that constitute a multiprocessor system on chip. This is
   done by modelling the mapping of a task with input and
   output channels on a processing element as a homogeneous
   synchronous dataflow graph, and use maximum cycle mean
   analysis to derive the throughput. In a HiperLAN\2 case
   study we show how these techniques can be used to derive the
   required clock frequency and communication latencies in
   order to meet the application&\[sh]8217;s throughput
   requirement on a multiprocessor system on chip that has one
   of the investigated memory organisations.