DRAFT AN IEEE COMPUTER SOCIETY INFORMATION BULLETIN: FOR IMMEDIATE RELEASE FOR ADDITIONAL INFORMATION CONTACT: Dr Colin Whitby-Strevens, Chairman IEEE P1355 Tel: +44 454 616616, Fax: +44 454 619796, email: colinws@isnet.inmos.co.uk IEEE ESTABLISHES P1355 WORKING GROUP: A STANDARD FOR LOW-COST, LOW-LATENCY INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION July nn, 1993, Bristol, England and Paris, France. The IEEE Standards Board has approved the creation of the P1355 Working Group to develop a ``Standard for Heterogeneous InterConnect (HIC) (Low Cost Low Latency Scalable Serial Interconnect for Parallel System Construction)''. The standard will use as its baseline the results of ESPRIT Project 7252 OMI/HIC - Open Microprocessor systems Initiative - High Performance Heterogeneous Interprocessor Communication. Additional information about this proposed standard is attached, and further details may be obtained by contacting: Dr Colin Whitby-Strevens, INMOS Limited, 1000, Aztec West, Almondsbury, Bristol, BS12 4SQ, UK; Tel: +44 454 616616; Fax: +44 454 619796; Email: colinws@isnet.inmos.co.uk For information about participating in the IEEE Computer Society contact the IEEE Computer Society at: 1730 Massachusetts Ave., NW, Washington, D.C., 20036: (202) 371- 0101, fax: (202) 728-9614 - MORE - Information for editors The new P1355 interconnect standard will enable high-performance, scalable, modular, parallel systems to be constructed with low system integration cost, which includes not only the price of components but also the engineering effort required to use them successfully. The standard will specify the physical connectors and cables to be used, the electrical properties of the interconnect, and a cleanly-separated set of logical protocols to perform the interconnection in the simplest possible way. The standard is aimed at a wide range of application areas, including Asynchronous Transfer Mode (ATM) switches, peripherals (eg disk arrays), next generation mainframe computer systems, graphics supercomputers, workstations, massively parallel supercomputers, multi-microprocessor systems addressing the full range of embedded systems applications, telecommunications applications and satellite communications, consumer electronics (eg HDTV), etc. The ability to implement a link conforming to the standard in a very small chip area and consuming a small amount of power using commodity VLSI technology (particularly CMOS) is a major factor differentiating the OMI/HIC technology from that necessary to implement other standards. The proposal to the IEEE to develop this new standard was made by the participants in the ESPRIT OMI/HIC (Open Microprocessor systems Initiative - High Performance Heterogeneous InterConnect) Project, which is a collaboration between INMOS Limited, Bull SA, Bull SpA, Thomson RCM, Thomson SINTRA ASM, Dolphin SCI Technology and the Universit‚ Pierre et Marie Curie (Paris). The project builds on the INMOS DS-Link communication and routing technology (as used for the new IMS T9000) and on Bull SA's Gigabit Serial Link technology which was demonstrated at ESPRIT '92. The standard will also draw on work on connectors for INMOS DS-Links carried out by Harting Elektronik, Fujitsu and AMP. "Our proposal has received an enthusiastic and warm welcome from the relevant IEEE committees,'' commented Colin Whitby- Strevens, the chairman of the new P1355 Working Group. "It complements other standards being developed within IEEE, and we already have excellent technical collaboration. The IEEE committees have been very complimentary on the technologies that the OMI/HIC project is developing, and are very pleased to support the development of corresponding standards.'' Colin Whitby-Strevens, who is also chairman of the OMI Standards Board, added, "I hope that this will be the first of many standards that the OMI will develop and promulgate in the international arena.'' As an IEEE committee, the P1355 Working Group will work in open meetings. Whilst most of the meetings will be held alongside the OMI/HIC project meetings in various locations in Europe, the Group is using electronic mail technology to encourage active participation from all parts of the globe. The Working Group has set itself a timetable with the aim of final IEEE approval within two years. Contacts IEEE P1355 WG Chairman: Dr Colin Whitby-Strevens, INMOS Limited, 1000, Aztec West, Almondsbury, Bristol, BS12 4SQ, UK. Tel: +44 454 616616, Fax: +44 454 619796, email: colinws@isnet.inmos.co.uk IEEE P1355 WG Co-chairman: Roland Marbot Bull SA, Avenue Jean Jaures, BP 53, 78340 Les Clayes sous Bois, France Tel: +33 1 30 80 74 71, Fax: +33 1 30 80 75 83, email: Roland.Marbot@frcl.bull.fr Background It is widely recognised today that the most economic way to build very high-performance systems is by using parallelism. Parallel systems can provide - very high computational power (in machines such as the CM-5 and the Parsytec GC-machine), - fast response (for transaction processing or distributed control), - very large i/o throughput (eg in RAID-type disk array systems) - extremely high reliability (in redundant fault-tolerant systems) - better maintainability and expandability than conventional, monolithic systems. The construction of high-performance systems with parallel processing and/or parallel i/o demands a fast, low-cost, low-latency interconnect. It must be fast and low-latency, otherwise it will be the limiting factor in system performance, and it must be low-cost, or else it will dominate the system cost. Most importantly, it must scale well in both performance and cost relative to the system size, otherwise highly parallel systems will be limited in performance or be too expensive. Existing standards do not meet these criteria, because either they are designed for communication over long distances (which incurs high costs), or they aim at the extreme of currently achievable performance (which again increases costs), or they are based on a restricted model such as a conventional bus, which limits overall performance and scalability. The P1355 PAR (Project Authorisation Request) describes the purpose of the new standard as being `to enable high- performance, scalable, modular, parallel systems to be constructed with low system integration cost; to support communications systems fabric; to provide a transparent implementation of a range of high level protocols (communications (eg ATM), message passing, shared memory transactions, etc), to support links between heterogeneous systems'. The PAR also indicates the standard's scope as being `physical connectors and cables, electrical properties, and logical protocols for point-to-point serial scalable interconnect, envisaged speeds of 100/200 Mbit/sec, 1 Gbit/sec and 3 Gbit/sec, copper and optic technologies (as developed in OMI/HIC)'. The OMI/HIC Project is a European collaboration, supported by the Commission of the European Communities (CEC) through the ESPRIT (European Strategic Programme for Research and Development in Information Technology), which is developing protocols and technology to meet these criteria. Major goals are to minimise the cost/performance ratio and to optimise for power efficiency. There is a strong commitment to exploitation, and the first components supporting these protocols (100/200 Mbit/sec) are anticipated to be commercially available this year, with higher speeds (1Gbit/sec) supported within three years, in both copper and optic technologies. A CMOS implementation of a 1 Gigabit/sec link was demonstrated at ESPRIT '92, and interfacing chips supporting gigabaud communications, suitable for prototyping, will be available in 1993. Anticipated products include dynamic packet routers (up to 32 links connected by a non- blocking full crossbar on a single chip), interfaces (eg to SCI), and CMOS and BiCMOS macrocells available under licence for integration into 3rd party ASIC designs. The emphasis in OMI/HIC is on highly integrated (in VLSI) communications for parallel system construction, with the aim of providing excellent performance/cost trade-off and the scalability of cost and performance with system size, rather than providing maximum performance. These aims will be achieved through using serial interconnect and simple protocols. The P1355 protocols are designed so that a link can be implemented using a relatively small amount of silicon area (CMOS for copper up to 1 Gbaud), allowing, for example, the integration of a large number of links (eg 32) with a full non-blocking crossbar to implement a packet router on a single VLSI chip. Innovative techniques such as wormhole routing with flow control at sub-packet level provide low latency (sub 1 microsecond) through such routers and the ability to support arbitrary packet sizes. This in turn enables the HIC technology to provide efficient support for a range of higher level protocols (eg ATM, SCI, Fibre Channel, virtual shared memory protocols, T9000 virtual channel message-passing, . . .) The OMI/HIC routers can be combined in a wide variety of topologies (grids, Clos networks, hypercubes, . . .) to construct high bandwidth packet switches permitting communication between thousands of nodes with latencies still in the very low units of microseconds. Techniques such as grouped adaptive routing and header deletion provide further efficiencies, and allow an arbitrary number of such switches to be combined in a communications fabric, each switch having its own topology and local addressing scheme (in a manner analogous to the telephone network, with local exchanges and area codes). The trade-offs in the P1355 protocols and the OMI/HIC technology are optimised towards relatively local communication, where the cost of the medium (whether copper or optic) is negligible compared to the cost of the components to drive and receive signals. This is in contrast to longer distance communications, or circumstances where even higher performance and/or lower latency is required. The OMI/HIC project is taking care to ensure the maximum of compatibility between the protocols used on copper and optic media, with the expectation that copper will be used between chips, and providing the designer with a choice of copper or optic between boards, cabinets and rooms according to the trade-offs and requirements inherent in his particular application. Related Activities The bit encoding for the 200 Mbit/sec DS-Links has already been adopted by the proposed Serialbus (IEEE P1394). Work in the OMI/HIC project is addressing the use of its routing technology to support SCI (IEEE 1596-1992) transaction protocols and Fibre Channel (ANSI ASC X3T9.3) fabric, together with the development of the appropriate interfaces. Work elsewhere is addressing the use of the HIC technology for ATM switches. Of particular relevance are the proposed ATM Platform standards (IEEE P1356 and IEEE P1357) and close collaboration is planned between the respective working groups.