Two files accompany this readme.pci file:

    pciflier.ps which is a single page Product Outline

    pci-pcb.psz which is an approximately actual size plot of the pcb.

The pcb file is compressed with gzip from the .ps file which is nearly
1 Mbyte.

You will notice on the PCB there is a large prototyping area, including
a footprint for a 208-pin QFP, a 100-pin QFP, and a Size2 HTRAM. None
of these is wired up to the logic, but they are there for you to develop
your own applications with IEEE 1355. The tracking on the PCB provides
full functionality for the two C101s driven in target mode from the
PCI bus.

The current PCB, with its prototyping space, is designed primarily for
development with IEEE 1355 and is not expected to be used by
end-users. This version of the PCB will not, therefore, be tested to 
ensure compliance with the EEC EMC Directive. The board has, of course,
been designed to minimise EMC radiation and susceptibility.

Current status is that the prototype PCB has been tested with both C101s 
looped back through the 1355 connectors. Many hundreds of packets have
been sent and received correctly. The C101s used on this prototype are
Rev C and Rev B. Apart from C101s, components for a preproduction build
are in hand or available on short lead times.

For further information, contact

Paul Walker
4Links for technical help
PO Box 816, Two Mile Ash
Milton Keynes, MK8 8NS
England

+44 1908 566253 (voice/fax)
paul@walker.demon.co.uk