From: Fred Chong Newsgroups: comp.parallel Subject: ASPLOS Early Registration Date: 25 Aug 1998 20:54:49 GMT Organization: UC Davis Approved: bigrigg@cs.cmu.edu Message-Id: <6rv8ap$sip$1@encore.ece.cmu.edu> Originator: bigrigg@ece.cmu.edu Reminder: ASPLOS early registration ends August 31st. Note this year's excellent selection of tutorials described in detail below. Advance Program for ASPLOS-VIII Eighth International Conference on Architectural Support for Programming Languages and Operating Systems October 3-7, 1998. San Jose, California http://arch.cs.ucdavis.edu/ASPLOS98 Sponsored by the ACM SIGARCH -- SIGPLAN -- SIGOPS ---------------------------------------------------------------------------- Rapid advances in VLSI technology, compilers, operating systems, and computer architecture provide a rich environment for creative system design. Like its predecessors, the eighth ASPLOS conference focuses on the interaction of these technologies. ---------------------------------------------------------------------------- Saturday, October 3 Afternoon (W1): First Workshop on PC-based System Performance and Analysis Rich Uhlig, Todd Austin, and Dave Kaeli http://www.eecs.umich.edu/~uhlig/asplos-pc/ ---------------------------------------------------------------------------- Sunday, October 4 Tutorial 1: Processor Techniques for Exploiting Instruction-Level Parallelism Sriram Vajapeyam, Indian Inst. of Science, Bangalore Tutorial 2: The Impact of Database System Configuration on Computer Architecture Performance Evaluation Kimberly Keeton, UC Berkeley Tutorial 3: SimOS: The Complete Machine Simulator Environment Mendel Rosenblum, Stanford University Tutorial 4: Profiling, Instrumentation, and Profile Based Optimization David Goodwin and Robert Cohn, Alpha Design Group, Compaq Tutorials 1 and 3 are concurrent in the morning. Tutorials 2 and 4 are concurrent in the afternoon. Tutorial descriptions: --------------------------------------------------------------------------- TUTORIAL #1 Emerging Processor Techniques for Exploiting Instruction-Level Parallelism Abstract -------- Instruction-Level Parallelism (ILP) has witnessed a number of significant innovations in the last few years. At the same time, explosive technology trends promise a continued boom in transistor counts. The resulting scenario is one where several recent ILP innovations are expected to be implemented in commercial processors in the next few years, making processor design and evaluation both complex and challenging. This tutorial presents an overview of important recently-proposed ILP processor techniques. Primarily, the tutorial is a quick but comprehensive tour of ILP techniques for each of the different processor pipeline stages and selected aspects of the top level memory hierarchy. Examples of topics to be covered include: high-bandwidth instruction fetch, dispatch, and issue mechanisms; high-accuracy and high-bandwidth control prediction; memory dependence handling; data value prediction; aspects of high- bandwidth data caches; reuse of dependence and scheduling information; recovery from mis-speculation; sub-word SIMD parallelism for multi- media; and support for precise interrupts. Drawing from relevant literature, we discuss the hardware complexity of several of the techniques. Putting things together, we present an example high-ILP processor of the future that incorporates several of these techniques, in order to show how they might fit together and interact with each other. In conclusion, we mention open research issues and current research directions in the ILP area. About the Presenter Sriram Vajapeyam is an Assistant Professor at the Indian Institute of Science, Bangalore, with primary research interests in processor architecture. His recent research contribution includes the first work on trace-centric processors. The speaker's industry experience includes over a year with the processor design group of Cray Research, Inc. in 1991-1992. Sriram obtained a Ph.D. from the University of Wisconsin, Madison in 1991 for a thesis on the characterization of the Cray Y-MP processor. He is currently researching hardware and software runtime schemes for further exploiting instruction-level parallelism in high-performance processors. ------------------------------------------------------------------ TUTORIAL #2 The Impact of Database System Configuration on Computer Architecture Performance Evaluation ASPLOS-VIII Tutorial October 4, 1998 Online transaction processing (OLTP) and decision support (DSS) databases are important, yet often overlooked workloads for evaluating the effectiveness of computer architecture innovations. Using commercial workloads to drive performance studies often proves to be difficult, due to the complexity of the workloads, the large hardware requirements for fully scaled experiments, the lack of access to source code, and the restrictions on the disclosure of performance information. How can we make it tractable for academic and industrial researchers to measure these workloads? This tutorial will feature a series of industrial presentations, followed by a panel discussion to "ask the industrial experts" questions such as the following: - How does one build well-balanced configurations to run a TPC-C or TPC-D workload? - What does it mean for a system to be "well-balanced"? - (How) is it possible to scale back the hardware requirements of full-scale systems, while ensuring representative behavior? - Alternately, what microbenchmarks can be used to measure representative behavior? - How do (academic) researchers get around logistical difficulties of running these workloads? - What are the right future benchmarks to examine? Organizer/Moderator: Kim Keeton, UC Berkeley Speaker/Panelists: Walter Baker, Gradient Systems (formerly of Informix Software) Luiz Barroso, Compaq/DEC Western Research Laboratory Michael Koster, Sun Microsystems Seckin Unlu, Intel Kim Keeton, the organizer of this session, is completing her PhD at UC Berkeley with Dave Patterson on computer architecture support for database workloads. She has worked with Informix to analyze the processor and memory system behavior of their shared memory database for OLTP workloads, and is currently investigating the use of increasingly intelligent disks (IDISKs) for offloading data-intensive DSS operations. The industrial experts participating in this session collectively possess decades of experience analyzing the performance of databases and other commercial applications, and grappling with many of these issues. ------------------------------------------------------------------- TUTORIAL #3 SimOS: The Complete Machine Simulator SimOS is a complete machine simulation environment designed for the efficient and accurate study of both uniprocessor and multiprocessor computer systems. SimOS simulates computer hardware in enough detail to boot and run commercial operating systems. SimOS currently models hardware similar to that of machines sold by Silicon Graphics, Inc. We simulate CPUs, caches, multiprocessor memory busses, disk drives, ethernet, consoles, and other devices commonly found on these machines. By simulating the hardware typically found on commercial computer platforms, we are able to easily port existing operating systems to the SimOS environment. A key component of SimOS is "annotations". Annotations are non-intrusive Tcl scripts that are executed whenever an event of interest occurs in the simulator. These events may be execution of a particular program counter value, a reference to a specified memory address, or even reaching a particular cycle count. Annotations collect and classify performance data, providing detailed information regarding operating system performance, application behavior, or architectural decisions. In this half-day tutorial, we cover the design decisions made in the development of SimOS and present several case studies highlighting SimOS's utility. About the presenter: Prof. Mendel Rosenblum is an Assistant Professor in the Computer Science Department at Stanford University. His research focuses on system software and simulation systems for high performance computing architectures, including the SimOS and Flash projects. ------------------------------------------------------------------------ Profiling, Instrumentation, and Profile Based Optimization David Goodwin and Robert Cohn Alpha Design Group Compaq Our understanding of the dynamic characteristics of programs drives the development of next generation processors and compilers. At Compaq, we use a variety of tools to study and exploit the behavior of programs. An execution profile is a summary of the number of times an event occurs for each instruction, where an event can be instruction issue, cache miss, clock cycle, etc. We study profiles to identify performance pitfalls and opportunities for optimization. Compilers use profiles to guide optimization. Instrumentation is the process of adding extra code to a program to measure some characteristic. We use customized instrumentation to model architectural alternatives and study program behavior. This tutorial describes the technology behind profiling, instrumentation, and profile based optimization. We discuss how to decide which technique is appropriate for a problem, and describe the tools that are publicly available from Compaq for Alpha based Unix and NT systems. David Goodwin is also in the Alpha Desgign Group, where he works on architecture and compiler advanced development. He has contributed to the performance analysis of the 21164, 21164PC, and 21264 microprocessors. David has implemented profile-directed register allocation and interprocedural dataflow analysis in the Spike executable optimizer. David received a B.S.E.E.from Virginia Tech and a Ph.D. in computer science from the University of California, Davis. Robert Cohn is also in the Alpha Design Group, where he works on advanced compiler technology for Alpha microprocessors. He has implemented trace scheduling and profile based optimizations in the production compilers for Alpha. He is a key contributor to Spike, implementing code layout and other profile based optimizations. Robert received a BA from Cornell University and a Ph.D. from Carnegie Mellon, both in computer science. ------------------------------------------------------------------------ ------------------------------------------------------------------------ Monday, October 5 8:45 Welcome 9:00-10:30 Compiler Optimizations for Memory * Compiler-Controlled Memory T. Harvey, K. Cooper, Rice University * Segregating Heap Objects by Reference Behavior and Lifetime B. Zorn, M. Seidl, Univ. of Colorado * Finding a Storage Reuse Pattern for any Legal Loop Schedule M. Strout, L. Carter, J. Ferrante, B. Simon, UC San Diego 11:00-12:30 Speculation and ILP Compilation - 1 * An Empirical Analysis of Instruction Repetition A. Sodani, G. Sohi, Univ. of Wisconsin - Madison * Space-Time Scheduling of Instruction-Level Parallelism on a RAW Machine W. Lee, R. Barua, M. Frank, D. Srikrishna, J. Babb, V. Sarkar, S. Amarasinghe, MIT Lab. for Computer Science * Data Speculation Support for a Chip Multiprocessor L. Hammond, M. Willey, K. Olukotun, Stanford University 2:00-3:30 I/O Systems * VISA: Netstation's Virtual Internet SCSI Adapter R. Van Meter, Quantum Corp.; G. Finn, S. Hotz, ISI - Univ. of Southern California * Active Disks: Programming Model, Algorithms and Evaluation A. Acharya, UC Santa Barbara; M. Uysal, J. Saltz, UMD - College Park * A Cost-Effective High-Bandwidth Storage Architecture G. Gibson, D. Nagle, K. Amiri, J. Butler, F. Chang, H. Gobioff, C. Hardin, E. Riedel, D. Rochberg, J. Zelenka, Carnegie Mellon University 4:00-6:00 Caches and Memory Systems * Hardware-Software Trade-Offs in a Direct Rambus Implementation of the RAMpage Memory Hierarchy P. Machanick, P. Salverda, L. Pompe, Univ. of the Witwatersrand, South Africa * Dependence Based Prefetching for Linked Data Structures A. Roth, A. Moshovos, G. Sohi, Univ. of Wisconsin - Madison * Performance Counters and State Sharing Annotations: a Unified Approach to Thread Locality Boris Weissman, Int. Computer Science Inst., Berkeley * Cache-Conscious Data Placement B. Calder, C. Krintz, S. John, UC San Diego; T. Austin, Intel Corp. ---------------------------------------------------------------------------- Tuesday, October 6 9:00-10:30 Cross-Platform Techniques and Branch Prediction * An Out-of-Order Execution Technique for Runtime Binary Translators B. Le, Hewlett Packard * Overlapping Execution with Transfer Using Non-Strict Execution for Mobile Programs C. Krintz, B. Calder, UC San Diego; H. Lee, B. Zorn, Univ. of Colorado * Variable Length Path Branch Prediction J. Stark, M. Evers, Y. Patt, Univ. of Michigan - Ann Arbor 11:00-12:30 Multiprocessor Systems * Performance Isolation: Sharing and Isolation in Shared-Memory Multiprocessors B. Verghese, Compaq Computer Corp. (WRL); A. Gupta, Microsoft and Stanford Univ.; M. Rosenblum, Stanford Univ. * UTLB: A Mechanism for Address Translation on Network Interfaces Y. Chen, C. Dubnicki, S. Damianakis, A. Bilas, K. Li, Princeton University * Locality-Aware Request Distribution in Cluster-Based Network Servers V. Pai, M. Aron, G. Banga, M. Svendsen, P. Druschel, W. Zwaenepoel, Rice University; E. Nahum, IBM TJ Watson 2:00-3:30 New Ideas Session Submission information available here. 4:00-5:30 Cache Analysis * Investigating Optimal Local Memory Performance O. Temam, Laboratoire PRiSM, Universite Versailles * Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity S. Ghosh, M. Martonosi, S. Malik, Princeton University * Capturing Dynamic Memory Reference Behavior with Adaptive Cache Topology J. Peir, Y. Lee, Univ. of Florida - Gainesville; W. Hsu, UC Berkeley 8:00-10:00 Panel Session ---------------------------------------------------------------------------- Wednesday, October 7 9:00-10:30 Speculation and ILP Compilation - 2 * Accelerating Multi-Media Processing by Implementing Memoing in Multiplication and Division Units D. Citron, D. Feitelson, Hebrew Univ. of Jerusalem; L. Rudolph, MIT * Value Speculation Scheduling for High Performance Processors C. Fu, M. Jennings, S. Larin, T. Conte, North Carolina State Univ. * An Empirical Study of Decentralized ILP Execution Models N. Ranganathan, Intel Corp.; M. Franklin, Univ. of Maryland 11:00-12:30 Simulation and Performance * Fast Out-Of-Order Processor Simulation Using Memoization E. Schnarr, J. Larus, Univ. of Wisconsin - Madison * A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organizations B. Jacob, Univ. of Maryland; T. Mudge, Univ. of Michigan - Ann Arbor * Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors P. Ranganathan, Rice University; K. Gharachorloo, Compaq Computer Corp. (WRL); S. Adve, Rice University; L. Barroso, Compaq Computer Corp. (WRL) Afternoon (W2): The 3rd Workshop on Interaction between Compilers and Computer Architectures Pen-Chung Yew and Gyungho Lee http://www-users.cs.umn.edu/~sycho/Workshop98 Conference Chairs General: Dileep Bhandarkar, Intel Program: Anant Agarwal, MIT Tutorial/Workshops: David R. Kaeli, Northeastern Local: Jason Ding and Akhilesh Kumar, Intel Finance/Registration: D. N. Jayasimha, Intel Publicity: Frederic T. Chong, UC Davis Program Committee Saman Amarasinghe, MIT Prith Banerjee, Northwestern Brian Bershad, University of Washington Josh Fisher, HP Laboratories Maya Gokhale, Sarnoff Allan Gottlieb, NYU Anoop Gupta, Stanford and Microsoft Research Mark Hill, Wisconsin Wen-mei Hwu, Illinois Randy Katz, UC Berkeley John Kubiatowicz, UC Berkeley Kathryn S. McKinley, Univ of Massachusetts, Amherst Chuck Thacker, Microsoft Willy Zwaenepoel, Rice Conference Site and Accomodations San Jose is conveniently located midway between San Francisco and the Monterey/Carmel area at the sunny southern end of San Francisco Bay. The ocean, the mountains, and many other attractions are just a short drive away. Accomodations: The Fairmont Hotel is centrally located in downtown San Jose at 170 South Market Street, across from the Convention Center. Call 408-998-1900 for reservations (mention ASPLOS). Reservations must be made before September 12th to guarantee room availability and rates. Single rooms are $159 and double rooms are $179 per night. Transportation: The nearest airport is San Jose International Airport. One can take a taxi (around $12) or a shuttle (South Bay Flyer 888-463-5937; about $6 from San Jose International, $16 from San Francisco International) to the hotel. Registration Form Early registration must be postmarked by August 31, 1998. Please circle all that apply: CONFERENCE Early Late ACM/SIG Members 350 425 Non-Members 450 525 Students 175 200 Incl 3 continental bkfsts, 2 lunches, 5 coffee breaks, reception TUTORIALS: T1 T2 T3 T4 (Circle) Full Day (2 Tutorials) Members 125 150 Non-members 175 200 Students 50 75 Incl 2 coffee breaks Half Day (1 Tutorial) Members 75 100 Non-Members 100 125 Students 35 50 Incl coffee break Workshops (Prices for Each) W1 W2 (Circle) Member 75 100 Non-member 100 125 Student 35 50 incl coffee break Early Registration Special Includes conference, all tutorials, and workshops Members 550 Non-Member 750 Students 250 Total____________________________(US Dollars) Name _____________________________________ Affiliation _________________________________ Address __________________________________ _________________________________________ Phone _______________ Fax __________________ E-mail ____________________________________ ACM Member Number _______________________ Payment: __Money Order __Check drawn on US Bank, payable to ACM ASPLOS-8 __MasterCard __Visa __American Express Cardmember's Name _________________________ Card number _____________________ Exp _______ Card Issuer/Bank ____________________________ Signature __________________________________ Mail or fax form to (secure on-line registration also available via conference web site): D. N. Jayasimha (ASPLOS 98) 2200 Mission College Blvd, MS RN2-02 Intel Corporation Santa Clara, CA 95052-8119 fax: (408) 765-4340 -- Articles to bigrigg+parallel@cs.cmu.edu (Admin: bigrigg@cs.cmu.edu) Archive: http://www.hensa.ac.uk/parallel/internet/usenet/comp.parallel