31st May 1994 /parallel/environments/splash Added mirror of SPLASH (Stanford Parallel Applications for Shared-Memory) system from Stanford. /parallel/software/simulators/wilson-sim Added mirror of Bob Wilson's fine-grain parallelism simulator from Stanford. This is the simulator that was used to generate the results in the paper "Limits of Control Flow on Parallelism" from ISCA'92. /parallel/conferences/wtc94 Call for participants and details of programmes and tutorials for the World Transputer Congress 1994 (WTC '94) being held from 5th-7th September 1994 at Villa Erba, Cernobbio, Lake Como, Italy. Sponsored by the Transputer Consortium (TTC) and SGS-Thomson in conjunction with the Italian Transputer User Group (ItTUG). Deadlines: Papers: 1st March 1994; Acceptance: 24th May 1994; Camera-ready copy: 23rd June 1994. Entry-Range:1994-09-05-1994-09-07 /parallel/languages/fortran/adaptor/ Latest mirrored version 2.0 arrived. Source-to-source FORTRAN translator. Handles F77, F90 arrays, data layout directives, CM Fortran, HPF features. Supports CM-5, iPSC/860, Paragon, Net of Sun Sparcs/IBM Riscs, Meiko CS1/2, KSR1, SGI MPs, Allian FX/2800, IBM SP1. Version 2.0 additions: cyclic distributions, multi-dimensional distributions on different processoar arrays Functionality and performance has increased for many features. 27th May 1994 /parallel/info/mirrors.html Added HTML version of current mirrors (generated automatically). 24th May 1994 /parallel/www Merged WWW files into FTP area /parallel/software/simulators/chaos Added mirror of CHAOS router simulator package from the Chaos Project Group (chaos@cs.washington.edu) at the University of Washington, USA. /parallel/software/simulators/chaos/README (258 bytes) Overview of directories /parallel/software/simulators/chaos/docs/ Documentation /parallel/software/simulators/chaos/docs/README (2006 bytes) Overview of files, see guide.ps.Z for a guide to the Chaotic Routing project's literature and publications. /parallel/software/simulators/chaos/docs/guide.ps.Z (39360 bytes) "A Guide to Literature on Chaotic Routing" by the Chaotic Routing Project, University of Washington, Seattle, WA 98195, USA. /parallel/software/simulators/chaos/docs/UW-CSE-91-04-04.PS.Z (145517 bytes) "Mesh and Torus Chaotic Routing" by Kevin Bolding and Lawrence Snyder. ABSTRACT: The chaos router is an adaptive nonminimal message router for multicomputers that is simple enough to compete with the fast, oblivious routers now in use in commercial machines. It improves on previous adaptive routers by using randomization, which eliminates the need for complex livelock protection and speeds the router. The two-dimensional chaos router is shown to be theoretically sound and physically realizable. Extensive simulation studies compare chaos routing with oblivious and deflection routing in mesh and torus networks. Chaos routing is shown to be competitive for mesh networks and superior for torus networks. This high performance is, perhaps, unexpected for the mesh since there is no finite bound on the delivery time of any message. /parallel/software/simulators/chaos/docs/UW-CSE-92-07-07.PS.Z (42090 bytes) "Non-Uniformities Introduced by Virtual Channel Deadlock Prevention" by Kevin Bolding. ABSTRACT: A common scheme for preventing deadlock in networks is the virtual channel method of Dally and Seitz [DS87]. Due to the nature of this scheme, an otherwise completely uniform network will have non-uniformities introduced into it. The variations introduce several effects, ranging from limitations on overall network performance to differences in observed network characteristics from node to node and from message to message. /parallel/software/simulators/chaos/docs/UW-CSE-92-12-03.PS.Z (79427 bytes) "A High-Speed Channel Controller for the Chaos Router", An Independent Master's Project by Robert Wille, December 8, 1992. /parallel/software/simulators/chaos/docs/UW-CSE-93-06-01.PS.Z (386071 bytes) "Performance of Chaos and Oblivious Routers Under Non-uniform Traffic" by Melanie L. Fulgham and Lawrence Snydery ABSTRACT: Chaos router is a nonminimal adaptive packet router that is both deadlock free and probabilistically livelock free [Kon91]. Unlike its predecessors [Nga89], the Chaos router uses randomization to provide an efficient way to avoid livelock [KS90]. The Chaos router has been compared in software simulation studies to the state-of-the-art oblivious routers (i.e. dimension order routers) on the hypercube topology [KS91], and the mesh and torus topologies [BS92]. The results, based on simulations of two different workloads, one uniform and one non-uniform load, show that in general the Chaos router is superior to the oblivious router. However, two workloads alone are not representative of the typical types of traffic encountered in practice. In this paper five additional non-uniform workloads are simulated. Each was chosen to represent one of the various types of communication encountered in typical programs. The workloads, compared on both the 256 node torus and hypercube topologies, show considerable variety and reveal insight on the effectiveness of Chaotic adaptive routing on non-uniform loads. Data presented includes the saturation point of the networks under the various loads, the throughput as a function of presented load, latency, and total delay of packets through the network. Collectively, this data gives a much clearer and complete characterization of the Chaos and oblivious routers' behavior on non-uniform traffic. /parallel/software/simulators/chaos/docs/UW-CSE-93-12-03.PS.Z (76855 bytes) "Multicomputer Interconnection Network Channel Design", Technical Report UW-CSE-93-12-03 by Kevin Bolding December 14, 1993. ABSTRACT: Massively parallel multicomputers require a high-performance interconnection network. The physical channels which connect nodes in the network are the components that most commonly impose restrictions on the amount of data which can be communicated between nodes of the network. Several different schemes for maximizing the bandwidth of physical interconnection channels are examined. Conventional technology centers on 5V electrical signalling. Within this paradigm, there are several different methods of maximizing throughput of a channel, given its limited bandwidth. Simplex and duplex channels are examined, as well as arbitration protocols and transmission line pipelining. Non-conventional technologies which achieve higher bandwidth transmission through low-voltage signalling and fiber optic communication are also examined. For the present, it is expected that most networks will continue to use electrical signalling with low-voltage signalling because fiber optic hardware is too expensive. As technology changes, though, it may become more common for networks to be built out of optical or other new technologies. /parallel/software/simulators/chaos/docs/UW-CSE-94-02-04.PS.Z (686833 bytes) "The Case for Chaotic Adaptive Routing": Technical Report CSE-94-02-04 by Kevin Bolding, Melanie L. Fulgham and Lawrence Snyder ABSTRACT: Chaotic routers are randomizing, non-minimal adaptive packet routers designed for use in the communication networks of parallel computers. Chaotic routing is reviewed along with other contemporary network routing approaches, including the state-of-the-art oblivious routers. Each routing approach is evaluated for its effectiveness as a multicomputer message router. The results indicate that the Chaos router is the most effective of known routing methods. /parallel/software/simulators/chaos/docs/chaos.ps.Z (149913 bytes) "The Chaos router" by S. Konstantinidou of IBM Almaden Research Center and L.Snyder of the University of Washington, Seattle, USA. ABSTRACT: In this paper the Chaos router, a randomizing, nonminimal adaptive packet router is introduced. Adaptive routers allow messages to dynamically select paths, depending on network traffic, and bypass congested nodes. This flexibility contrasts with oblivious packet routers where the path of a packet is statically determined at the source node. A key advancement of the Chaos router over previous nonminimal routers is the use of randomization to eliminate the need for livelock protection. This simplifies adaptive routing to be of approximately the same complexity along the critical decision path as an oblivious router. The primary cost is that the Chaos router is probabilistically livelock free rather than being deterministically livelock free, but evidence is presented implying that these are equivalent in practice. The principal advantage is excellent performance for nonuniform traffic patterns. The Chaos router is described, it is shown to be deadlock free and probabilistically livelock free, and performance results are presented for a variety of work loads. /parallel/software/simulators/chaos/docs/boldingPhd.ps.Z (868309 bytes) "Chaotic Routing -- Design and Implementation of an Adaptive Multicomputer Network Router" by Kevin Bolding. ABSTRACT: A crucial component of a massively parallel multicomputer is the interconnection network which links all of the nodes of the computer together. This network provides the primary method of communication between the hundreds or thousands of processing nodes and is, thus, critical to the successful operation of the multicomputer. Current state-of-the-art interconnection networks use simple, oblivious routing techniques which achieve very good performance when loading is light, but do not perform well in the presence of non-uniform congestion or faults. Chaotic routing, a non-minimal adaptive routing technique, provides a mechanism which takes into account the presence of congestion and faults when choosing a path for a message and can, thus, achieve better performance. Chaotic routing is shown to be applicable to all finite-sized networks of bounded degree with bi-directionally connected links. A design for a chaotic router is presented which includes both the features of virtual cut-through routing and the advantages of internal non-blocking buffering. This design allows messages to follow minimumlatency paths when network loading is light, and provides sufficient buffering to ensure high throughput when the network is heavily loaded. The resulting design is compared with other minimal and non-minimal adaptive designs, as well as with oblivious routing. Chaotic routing is shown to be superior to most other adaptive designs due to its lower design complexity, and simulations are used to compare it with oblivious and deflection routing. The simulations show that, for mesh-connected networks, chaotic routing performs only slightly better than oblivious routing. However, for torus- and hypercube-connected networks, chaotic routing is superior to oblivious and deflection routing, achieving much higher throughput and lower latency. To demonstrate the feasibility of chaotic routing, a prototype chaos router chip is presented. This chip, fabricated in 1.2m CMOS, implements a two-dimensional chaos router. The chip, in simulations, operates at 66MHz, with the speed being limited only by the speed at which the 5V CMOS pads can be switched. Thus, the chip should operate at the same clock speed as oblivious routers using the same technology, giving an equivalent bandwidth capability. /parallel/software/simulators/chaos/docs/chip.ps.Z (100545 bytes) "The Chaos Router Chip: Design and Implementation of an Adaptive Router" by Kevin Bolding, Sen-Ching Cheung, Sung-Eun Choi, Carl Ebeling, Soha Hassoun, Ton Anh Ngo and Robert Wille. ABSTRACT: Chaotic routers are randomizing, non-minimal adaptive packet routers designed for use in the communication networks of parallel computers. Although adaptive routing, and, specifically, chaotic routing, has been shown to be superior to oblivious routing in most cases, the practical application of adaptive routing to multi-computer networks has been difficult to achieve due to the complex nature of adaptive routers. A prototype two-dimensional (mesh and torus) chaotic router chip has been designed and is being fabricated in a 1:2m CMOS process. The chip exhibits high bandwidth, limited only by the speed of the off-chip drivers, and low input-to-input latency. To achieve this, much attention is given to reducing the critical path complexity of the router. The resulting chip is shown to be as good or better than state-of-the-art oblivious routers in almost all cases. /parallel/software/simulators/chaos/docs/faultOverview.ps.Z (42311 bytes) "Overview Of Fault Handling For The Chaos Router" by Kevin Bolding and Lawrence Snyder. ABSTRACT: The chaos router is an adaptive nonminimal message router for multicomputers that is simple enough to compete with the fast, oblivious routers now in use in commercial machines. It improves on previous adaptive routers by using randomization, which eliminates the need for complex livelock protection and speeds the router. This randomization, however, greatly complicates the fault detection because there is no worstcase bound on the time required to deliver a message. Distinguishing between lost and very slow messages is difficult. A new method of fault detection is presented that applies not only to the chaos router but also to other adaptive routers as well. In addition, solutions to several practical fault diagnosis and recovery problems in the chaos router are presented. The presentation supports the claim that fault tolerance can be incorporated into a practical router without harming performance for the normal, fault-free cases. /parallel/software/simulators/chaos/docs/hyp-tor.ps.Z (57825 bytes) "On The Comparison Of Hypercube And Torus Networks" by Kevin Bolding and Smaragda Konstantinidou. ABSTRACT The binary hypercube and the family of k-ary, n-cubes have long been used as communication networks in massively parallel machines. In an effort to understand the effect of dimensionality on the network performance, k-ary, n-cubes have been compared under constant bisection bandwidth and constant pin count constraints. We show that these constraints are not independent and when either one is ignored the comparison strongly favors some particular network. We propose a new cost function, namely the product of the network's bisection bandwidth and pin count, and compare the networks under equal cost functions. We then give specific examples of a comparison between the binary hypercube and the torus networks under this new model, both in terms of their minimum latency and maximum throughput bounds and in terms of average latency and sustained throughput under varying applied traffic. /parallel/software/simulators/chaos/simulator/ Simulator source /parallel/software/simulators/chaos/simulator/INSTALL (584 bytes) Run this to install the Chaos Simulator Package /parallel/software/simulators/chaos/simulator/README (929 bytes) Details of Chaos Simulator Package /parallel/software/simulators/chaos/simulator/chaosSim.tar.Z (473483 bytes) Chaos Simulator Package source distribution /parallel/software/simulators/proteus Added mirror of PROTEUS parallel architecture simulator by Eric Brewer /parallel/software/simulators/proteus/README (1853 bytes) README /parallel/software/simulators/proteus/InstallationNotes (2424 bytes) Notes on settup up Proteus. /parallel/software/simulators/proteus/proteus-V3.01.tar.Z (1155725 bytes) Proteus distribution V3.01. /parallel/software/simulators/proteus/userdoc0.5.tar.Z (632021 bytes) User documentation V0.5 /parallel/software/simulators/proteus/reference.bibtex (906 bytes) Proteus references (in BibTeX) /parallel/software/simulators/proteus/examples/ /parallel/software/simulators/proteus/examples/disk.tar.Z (27378 bytes) /parallel/software/simulators/proteus/examples/fib.tar.Z (15909 bytes) /parallel/software/simulators/proteus/examples/wave.tar.Z (42095 bytes) /parallel/software/simulators/proteus/libevt.tar.Z (433859 bytes) Source of Proteus-format Event-Generation Library. /parallel/software/simulators/proteus/overview.ps.Z (144779 bytes) "PROTEUS: A High-Performance Parallel-Architecture Simulator" by Eric A. Brewer, Chrysanthos N. Dellarocas, Adrian Colbrook and William E. Weihl, September 1991. MIT/LCS/TR-516. ABSTRACT: Proteus is a high-performance simulator for MIMD multiprocessors. It is fast, accurate, and flexible: it is one to two orders of magnitude faster than comparable simulators, it can reproduce results from real multiprocessors, and it is easily configured to simulate a wide range of architectures. Proteus provides a modular structure that simplifies customization and independent replacement of parts of architecture. There are typically multiple implementations of each module that provide different combinations of accuracy and performance; users pay for accuracy only when and where they need it. Finally, Proteus provides repeatability, nonintrusive monitoring and debugging, and integrated graphical output, which result in a development environment superior to those available on real multiprocessors. /parallel/software/simulators/proteus/patches/ /parallel/software/simulators/proteus/patches/Notes_On_V3toV3.01 (1073 bytes) /parallel/software/simulators/proteus/patches/README (474 bytes) /parallel/software/simulators/proteus/patches/V3toV3.01 (5289 bytes) /parallel/software/simulators/proteus/pipes_tr.ps.Z (108603 bytes) "Pipes: Linguistic Support for Ordered Asynchronous Invocations" by Adrian Colbrook, Eric A. Brewer, Wilson C. Hsieh, Paul Wang and William E. Weihl, April 1992. ABSTRACT: We describe pipes, a new linguistic mechanism for sequences of ordered asynchronous procedure calls in multiprocessor systems. Pipes allow a sequence of remote invocations to be performed in order, but asynchronously with respect to the calling thread. Using pipes results in programs that are easier to understand and debug than those with explicit synchronization between asynchronous invocations. The semantics of pipes make no assumptions about the underlying architecture, which enhances code portability. However, the implementation of pipes by the language compiler can be optimized so as to take advantage of any underlying message ordering a particular architecture may provide. Pipes also provide application-transparent flow control for asynchronous invocations and are able to throttle invocations from multiple calling threads. We present four implementations of pipes and show that the performance and space overheads associated with pipes are low. /parallel/software/simulators/proteus/prelude-notes (72920 bytes) Prelude language notes /parallel/software/simulators/proteus/stats-source.tar.Z (94059 bytes) Source to stats graphic package /parallel/conferences/scs-ieee-acm-simulation-symposium Call for papers for the 28th Annual Simulation Symposium being held from 9th-13th April 1995 at the Crescent Hotel, Phoenix, Arizona, USA. In cooperation with SCS, IEEE and ACM. Deadlines: Email Paper: 1st October 1994; Paper Paper: 15th September 1994; Notification: 10th Decemeber 1994; Camera-ready papers: 20th January 1995. Entry-Range:1995-04-09-1995-04-13 /parallel/courses/romania-summer-school-par-comp-europe Call for participation for the Black Sea University,Romania Summer School on Parallel Computing in Europe: Achievements and Trends being held from 10th-23rd July 1994 at Mangalia, Romania. Topics are: Distributed memory parallel computers, parallel programming, EVAL: data parallel language for scientific programming, Parallel operating systems and development of applications and Performance analysis. Entry-Range:1994-06-10-1994-06-23 23rd May 1994 /parallel/papers/announcements/tool-eval-with-NAS-par-benchmarks Announcement of evaluation report by Florian Sukup on the parallization tools: PVM 2.x, PVM 3.x, p4, Express and Linda on a workstation cluster: 9 IBM RS6000 320H, token ring capable of 16 Mbits/s using the NAS parallel benchmark kernels: Embarrassingly Parallel, Multigrid, Conjugate Gradient and Integer Sort available via anonymous ftp. /parallel/user-groups/ppecc/inaugural-meeting Details of Inaugural Meeting of the Engineering Applications IT Support ProgrammE (EASE) Education and Awareness Programme's Parallel Processing in Engineering Community Club being held on 1st June 1994 at R22 Lecture Theatre, Rutherford Appleton Laboratory, Chilton, Didcot, Oxfordshire, UK. /parallel/conferences/wotug18 Call for papers for the 18th World occam and Transputer User Group (WoTUG) conference being held from 2nd-5th April 1995 at Manchester Metropolitan University, Britain. Deadlines: Full/nearly complete papers: 1st November 1994; Notification: Mid-December 1994; Camera-ready copy: 9th January 1995. Entry-Range:1995-04-02-1995-04-05 /parallel/environments/lam/mailing-list LAM mailing list information. /parallel/conferences/pc2-deutschland Call for participation for PC^2 User Workshop und Oeffentlicher Parallelitaetstag vom 15 bis 17 Juni 1994 nach Universitaet-GH, Paderborn, Deutschland. Entry-Range:1994-06-15-1994-06-17 /parallel/vendors/tandem/tpc-c-results Report by Tandem on a "New world record TPC-C results" for Tandem's Himalaya K10000 system. /parallel/environments/chimp /parallel/environments/chimp/chimp-mpi-2.1.announce Added mirror of: CHIMP (Common High-level Interface to Message Passing) project from the EPCC (Edinburgh Parallel Computing Centre) at the University of Edinburgh, Scotland. Includes an implementation of MPI over CHIMP /parallel/documents/humor/building-par-prog-systems "Building parallel programming systems" by Brent Gorda, Paul Lu, Greg Wilson. March 1994. /parallel/courses/colorado-summer-par-prog-institute Details of University of Colorado Center for Software Systems Science Summer Parallel Programming Institute being held from 6th-12th August 1994 organized by the Center for Software Systems Science at the University of Colorado and cosponsored by Convex CXSoft. Courses on C/C++/HPF/... including work on Convex,KSR1,CM5,Intel Paragon. Entry-Range:1994-08-06-1994-08-12 /parallel/user-groups/hpff/minutes-1994-Apr-06-08 Minutes of HPFF94 April Meeting, Chicago from 6th-8th April 1994 by Mary E Zosel /parallel/vendors/pallas/hpf-pallas+portland Details of Portland Group and PALLAS cooperating on High Performance Fortran products in Europe. 20th May 1994 /parallel/transputer/software/utils/uchan/uchan.announce Announcement of UCHAN-0.1 channel.h emulation for gcc on UNIX systems. Implements a subset of the INMOS C channel interface for UNIX hosts to run processes on multiple hosts. Written by Michael Bartmann /parallel/transputer/software/utils/uchan/uchan-0.1.tar.gz UCHAN version 0.1 sources /parallel/vendors/3L/C-TMS320C40 Announcement of version 1.1 of 3L Parallel C for the TMS320C40 including lots of new stuff -- global I/O, 8-level priority scheduling of threads and tasks, 50 new C40-specific low-level functions, built-in processor farms, a network explorer utility, register-model libraries, latest release of TI C compiler,... /parallel/conferences/india-wks-par-proc Call for participation in the First International Workshop on Parallel Processing being held from 27th-30th December 1994 at the Hotel Oberoi, Bangalore, India in cooperation with IEEE Computer Society Technical Committee on Parallel Processing (TCPP) and the IEEE Computer Society Technical Committee on Computer Architecture (TCCA) and with support from Center for Development of Advanced Computing (CDAC); Department of Science and Technology, Government of India (pending) and the National Science Foundation (pending). Deadlines: Abstracts: 1st July 1994; Notification: 31st July 1994; Camera-ready papers: 31st August 1994; Tutorials: 31st July 1994. Entry-Range:1994-12-27-1994-12-30 /parallel/software/simulators/cpd.announce Announcement of CPS 1.0 Parallel Discrete-Event Simulator availability. The modules are written in C and have to be linked with user's application program. CPS 1.0 currently runs on Intel iPSC multicomputers, but can be ported (upon request) to other parallel MIMD machines, such as Caltech hypercubes or Sequent multicomputers. Contact: Dr. Bojan Groselj /parallel/software/announcements/enterprise Announcement v2.3.0 of the Enterprise Parallel Programming Environment, a programming environment for designing, coding, debugging, testing, monitoring, profiling and executing programs in a distributed hardware environment. Implemented on RS6K, SGI and SUN4 and available via anonymous FTP. /parallel/user-groups/ittug/launch Launch details of Italian Transputer User's Group (ItTUG) at the World Tranputer Congress '94 (WTC '94) that will be held on 5-7 September 1994 at the Villa Erba, Cernobbio, Como (Italy) by Giovanni Muscato /parallel/languages/modula2star/karlsruhe Added mirror of Modula-2* programming environment for sequential architectures by Ernst A. Heinz et al of Institute for Program Structures and Data Organization (IPD), Department of Informatics, University of Karlsruhe, Germany. /parallel/documents/mpi/anl/misc/heath.ps.Z Chapter 1: Performance Analysis of MPI Programs by Ed Karrels and Ewing Lusk. ABSTRACT: "The Message Passing Interface (MPI) standard has recently been completed. MPI is a specification for a library of functions that implement the message-passing model of parallel computation. One novel feature of MPI is its very general profiling interface," that allows users to attach assorted profiling tools to the MPI library even though they do not have access to the MPI source code. We describe the MPI profiling interface and describe three profiling libraries that make use of it. These libraries are distributed with the portable, publicly available implementation of MPI." 19th May 1994 /parallel/software/simulators/mint Added mirror of MINT simulator. /parallel/software/simulators/mint/mint.announce Description of the MINT simulator by the author Jack Veenstra . MINT reads the unmodified application executable and creates synthesized functions in memory at initialization time to simulate blocks of instructions from the application. MINT runs on SGI machines, DECstations, and SPARCstations (but always simulates applications compiled for the MIPS instruction set) /parallel/software/simulators/mint/mint-2.2.tar.Z MINT 2.2 sources /parallel/software/simulators/mint/mint-splash-src-and-binaries.tar.Z MINT source and binaries for splash /parallel/software/simulators/mint/mint.README MINT README /parallel/software/simulators/mint/mint.user.manual.ps.Z Mint user manual /parallel/papers/announcements/collect-ops-elros Announcement of report by Kishore Viswanathan and Anthony Skjellum: "Collective Operations Using ELROS and Sockets" available for anonymous ftp. The paper discusses the implementation of collective operations using ELROS (Embedded Language for Remote Operation Service, developed at Lawerence Livermore National Laboratory) and sockets. The advantages and disadvantages of using ELROS over sockets to implement collective operations is also discussed. 18th May 1994 /parallel/documents/hippi Added mirror of HIPPI documentation. /parallel/conferences/icpads94 Call for papers for the 1994 International Conference on Parallel and Distributed Systems (ICPADS '94) being held from 19th-21st December 1994 at National Chiao Tung University, Hsinchu, Taiwan, R.O.C. Deadlines: Papers: 6th June 1994, Acceptance: 15th September 1994; Camera-ready papers: 15th October 1994. /parallel/software/iservers/wiserver-src.zip Source to final version of WIserver by Mike Morgan. Mike has a new job that does not involve Transputers and hence is releasing the source code to the public domain. The source was provided by an ex-colleague of his, David Eastlake . 17th May 1994 /parallel/vendors/transtech/i860-super-computer Announcement of "Affordable Parallel Supercomputer" based on i860 built by Transtech Parallel Systems. /parallel/papers/announcements/Kahaner-Hitachi-report Announcement of a report by Dr. David Kahaner on Hitachi's parallel processing plans. Posted by Rick Schlichting /parallel/papers/announcements/Kahaner-Indian-report Announcement of a report by Dr. David Kahaner on Indian parallel processing activities. Posted by Rick Schlichting /parallel/papers/announcements/Kahaner-PCG94-report Announcement of a report by Dr. David Kahaner on the PCG'94 conference at Keio University, Yokohama Japan /parallel/conferences/spaa94.tex /parallel/conferences/spaa94.ascii Details of and program for the 6th Annual ACM Symposium on Parallel Algorithms and Architectures being held from 27th-29th June 1994 at Cape May, New Jersey, USA sponsored by the ACM Special Interest Groups for Automata and Computability Theory (SIGACT) and Computer Architecture (SIGARCH) and organized in cooperation with the European Association for Theoretical Computer Science (EATCS). Entry-Range:1994-06-27-1994-06-29 /parallel/conferences/part94 Registration details of Australasian Workshop on Parallel and Real-Time Systems (PART'94) being held from 7th-8th July 1994 at Victoria University of Technology Melbourne, Australia. Deadlines: Registration: 30th June 1994; Workshop registration: 6th July 1994. Entry-Range:1994-07-07-1994-07-08 /parallel/software/announcements/prospero-0.9 Announcement of version 0.9 of the Prospero Resource Manager that enables users to run sequential or parallel applications on a collection of workstations. Sequential jobs may be offloaded to lightly loaded workstations while parallel jobs can make use of the collection of processors to achieve speedups. Developed at USC Information Sciences Institute (ISI) via anonymous FTP. /parallel/conferences/dags94 Call for papers for The Dartmouth Institute For Advanced Graduate Studies (DAGS) In Parallel Computation Symposium On Parallel Computing And Problem Solving Environments: Providing Massively Parallel Computing to Problem Solvers being held from 5th-7th July 1994 at DAGS,Dartmouth College, Hanover, NH, USA. Deadlines: Extended abstract: 25th April 1994; Notification: 25th May 1994; Final paper: 20th June 1994. Entry-Range:1994-07-05-1994-07-07 /parallel/courses/compilers-for-par-comps Advanced course on Languages, Compilers, And Programming Environments For Scalable Parallel Computers being held from 6th-7th July 1994 at the Institute for Software Technology and Parallel Systems, University of Vienna, Austria. Entry-Range:1994-06-06-1994-06-07 16th May 1994 /parallel/occam/compilers/inmos/oc/preocc-bin-sun4.gz sun4 binary of INMOS occam 2 pre-processor 10th May 1994 /parallel/conferences/hicss28-comp-bio-par-computing Call for papers and referees for the Computational Biology and Parallel Computing Minitrack for the BioTechnology Track at HICSS-28 (28th Hawaii International Conference on System Sciences) being held from 3rd-6th January 1995 at Maui, Hawaii, USA. Deadlines: (Optional) Abstract: 29th April 1994; 8xPaper: 17th June 1994; Notification: 31st August 1994; Camera-ready papers: 1st October 1994 Entry-Range:1995-01-03-1995-01-06 /parallel/conferences/pcrcw94 Announcement and advanced registration for the 1994 University of Washington Parallel Computer Routing and Communication Workshop (PCRCW '94) being held from 16th-18th May 1994 at the University of Washington, Seattle, Washington, USA Entry-Range:1994-05-16-1994-05-18 /parallel/journals/Elsevier/parallel-computing/1994-03-10 Contents listing of Parallel Computing vol 20, iss 3: 1994-03-10 /parallel/journals/Elsevier/parallel-computing/1994-03-31 Contents listing of Parallel Computing vol 20, iss 4: 1994-03-31 /parallel/courses/par-computing-summer-workshop Call for participation in the Summer Workshop and Conference on Parallel Computing being held from 23rd May 1994-3rd June 1994 at the University of Central Florida, Orlando, FL, USA. It is a two week residential course (no fees) to train academia and industry in parallel computing. /parallel/user-groups/ppsg/ppsg-meeting Details of British Computer Society Parallel Processing Specialist Group (BCS PPSG) One Day Open Meeting with Invited Papers: Bulk Data Types for Architecture Independence being held on 20th May 1994 at Institute of Education, London, UK. /parallel/documents/benchmarks/ftp-sites Details of some FTP sites having benchmark programs for running on a parallel computer simulator by Sharma R. Podila /parallel/faqs/wormhole-routing Summary of replies to questions about wormhole routed machines by Kant C Patel /parallel/software/announcements/NESL Announcement of NESL language and environment. NESL is a fine-grained, functional, nested data-parallel language currently implemented on workstations, the Connection Machines CM2 and CM5, the Cray Y-MP and the MasPar MP2. It is available via anonymous FTP. /parallel/faqs/MPI MPI (Message Passing Interface) Frequently Asked Questions by Nathan Doss 6th May 1994 /parallel/conferences/tc94-workshop-case-tools Call for papers for CASE Tools for Parallel System Development workshop being held either 3rd or 4th September 1994 just before the World Transputer Congress 1994 (WTC '94) conference at Villa Erba, Cernobbio, Lake Como, Italy. Deadlines: Papers: 1st July 1994 Entry-Range:1994-09-03-1994-09-04 /parallel/conferences/tat94 Details of TAT 94 (Treffen der Parallelrechner-Anwender) conference of DeTAG (Deutsche Transputer-Anwender-Gemeinschaft) being held from 26th-27th September 1994 in Aachen, Germany. Conference language is German. Entry-Range:1994-09-26-1994-09-27 /parallel/conferences/capps94 Call for papers for CAPPS 94 - Commercial Applications of Parallel Processing Systems being held from 17th-19th October 1994 at Stouffer Hotel, Austin, Texas, USA. Entry-Range:1994-10-17-1994-10-19 /parallel/conferences/pdcs94-session-gis Call for papers for PDCS 94 special session on Geographical Information Systems (GIS) being held at from 6th-8th October 1994 at Las Vegas, Nevada, USA. Deadlines: Papers: 27th May 1994; Acceptance: 8th July 1994; Camera-ready-copy: 5th August 1994. Entry-Range:1994-10-06-1994-10-08