Newsgroups: comp.parallel,comp.sys.super,comp.arch,ba.seminars From: "B. Mitchell Loebel" Subject: The PARALLEL Processing Connection-December 8th Meeting Notice Organization: Parallel Processing Connection Date: 6 Dec 1997 01:27:19 GMT Message-ID: <66a9ln$3ik@darkstar.ucsc.edu> On December 8th Wolf-Dietrich Weber of HAL Computer Systems will talk about that company's interconnect, code-named Mercury. It was designed to link commodity microprocessors, memory, and I/O components into high-performance Distributed Shared Memory multiprocessing servers. Shared-memory, message-passing, and hybrid systems thereof are all supported by the interconnect. HAL claims that its Mercury Interconnect Architecture features low latency, high bandwidth, and a simplicity that enables very cost-effective implementations. The first implementation links four 4-processor Pentium Pro based nodes to create 16 processor shared-memory configurations. This system achieves a remote read latency of just over 1 micro-second and a maximum interconnect bandwidth of 6.4 GByte/s; Wolf notes that these figures are better than comparable (?) SCI-based solutions, while utilizing much fewer hardware components. That statement should generate a lively conversation because SCI people can be expected to offer up a significant challenge. A second PCI card based implementation enables very high performance clustering. The main meeting starts promptly at 7:30PM at Sun Microsystems at 901 San Antonio Road in Palo Alto. This is just off the southbound San Antonio exit of 101. Northbound travelers also exit at San Antonio and take the overpass to the other side of 101. A discussion of member projects currently underway and other issues of interest to entrepreneurs follows immediately thereafter at 9:15PM. Please be prompt; as usual, we expect a large attendance; don't be left out or left standing. There is a $12 fee for non-members and members will be admitted free. Yearly membership fee is $65.