INTEL SUPERCOMPUTER USERS' GROUP ELECTRONIC NEWSLETTER Sept. 27, 1993 WELCOME to the first edition of the Intel Supercomputer Users' Group Electronic News. In this issue, you'll find: * Late-breaking news: Oak Ridge National Laboratory accepts delivery of one of the largest Paragon(tm) supercomputers installed to date -- a 512- node configuration with peak performance of 38 GFLOPS. * An article from Users' Group chair Gary Lamont (Air Force Institute of Technology) on what's in store at the upcoming Supercomputer Users' Group Annual Conference, which takes place Oct. 3-6 in St. Louis. * A report from Marsha Jovanovic (San Diego Supercomputer Center) on the Paragon supercomputer and SDSC's recent summer institute. * A wrap-up from Thierry Priol (IRISA) on the Intel Supercomputer European Users' Group Annual Conference, held last June in Munich. * An in-depth interview with Oregon State University professor and HPC user advocate Dr. Cherri Pancake on Intel's new ParAide software development environment, which will be available this fall on the Paragon supercomputer. * A write-up on this summer's SuperQuest Northwest, where winning teams of high school students had a crack at parallel programming on an iPSC(R)/860 computer. * An Intel News Roundup -- all the news that fits, including new Paragon supercomputer configurations, a C++ CRADA with Sandia National Laboratories, an alliance with Unisys to develop scalable computers based on the Pentium(tm) processor and more. If you have feedback on the Intel SUG Electronic Newsletter, we'd like to hear from you. Send your comments to Gary Lamont (lamont@afit.af.mil). *************************************************************************** TOP OF THE NEWS: OAK RIDGE NATIONAL LAB ACCEPTS DELIVERY OF 38 GFLOPS PARAGON(tm) SYSTEM The Intel Paragon(tm) XP/S supercomputer at Oak Ridge National Laboratory (ORNL), Oak Ridge, Tenn., has passed its acceptance test and is now available to the Grand Challenge science community at the Laboratory. The announcement came following a rigorous testing period that included, among others, tests of performance features and a seven-day reliability run using actual application codes. All quantitative criteria were surpassed by substantial margins, according to Ken Kliewer, director of ORNL's Center for Computational Sciences. The 38 GFLOPS Paragon XP/S system is one of a series of Intel scalable supercomputers at ORNL. A Paragon XP/S 5 system is already active at the lab, a Model 75 will be delivered to ORNL later this year, and a Model 150 is scheduled for delivery in late summer, 1994. Early Paragon system users at ORNL have been scientists working in the areas of global change, groundwater transport, high energy physics and materials modeling. With the additional computing power, the Lab will also provide computing resources to the Grand Challenge chemistry, biology and fusion engineering groups. Oak Ridge National Laboratory is managed by Martin Marietta Energy Systems for the U.S. Department of Energy. *************************************************************************** GARY LAMONT: PIONEERING NEW SUPERCOMPUTING TRAILS IN ST. LOUIS This year marks the 150th anniversary of the Oregon Trail -- a trail that ends just a few miles away from the headquarters of our favorite supercomputer company. So, since parallel computer users are pioneering a new route to high performance computing, it seems completely fitting for the Intel Supercomputer Users' Group to hold its annual conference in the city that was the starting point for the Oregon trail: St. Louis, Missouri. I'm tremendously excited at the program we have planned this year. Packed into a full four days of activities, it reflects the high degree of enthusiasm, leadership and participation that have typified the Intel Users' Group this past year. On Sunday, we'll have two hands-on workshops on the Paragon supercomputer and its software. Conducting the training sessions will be Marilynn Livingston of Southern Illinois University at Edwardsville, George Kremenek and Reagan Moore of the San Diego Supercomputer Center, Chuck Mosher of Arco, Jerry Yan of NASA, Paul Messina of Caltech, Buddy Bland of ORNL and Judy Guist of Intel. To support the workshop, we'll have a 28-node Paragon XP/E computer -- the first XP/E off the production line! It's equipped with 32 MB of memory per node, a 2.4 GB disk and a HIPPI connection to a Sun workstation and will be running a pre-release version of Release 1.1 of the Paragon operating system. In addition to some 20 technical presentations by users, we'll hear from a variety of invited speakers and Intel representatives. Invited speakers include Paul Messina of Caltech, Reagan Moore of SDSC, Art Hale of Sandia National Laboratories, John Drake of Oak Ridge National Laboratory and Tom Pyke of the National Oceanographic and Atmospheric Administration (NOAA). Reagan has also organized a special panel discussion dealing with Paragon system management. Speaking on behalf of Intel will be Ed Masi, SSD's president; Justin Rattner, director of technology; and Eli Lamb, director of software. In addition, Judy Guist will demonstrate Intel's new ParAide software development environment, and Mike Barton will discuss applications. We'll also have SIG meetings, plus Birds of a Feather sessions on large-site Paragon system installations; operating systems; compilers, math libraries and solvers; applications tuning; tools and debuggers; I/O and connectivity; system administration; service and support; and real-time/signal processing A technology partners forum will feature presentations by Applied Parallel Research, Juniper Systems, Maximum Strategy, Network Systems, the Portland Group and Verdix. We'll also be announcing the inauguration of something I'm very proud of -- the Users' Group's first annual Parallel Computation Prize. We'll tell you all about it in St. Louis and in the November issue of the Users' Group News. On the final morning of the conference, I'll pass the gavel to our new chair. The Users' Group nominating committee had a difficult task, with many more willing volunteers than board positions -- an unusual situation for volunteer organizations, as I'm sure many of you know! I know Chuck joins me in wishing the new leadership well and looking forward to great things for the Users' Group in 1994-95! No conference would be complete without an ice-breaking social event, and this year we're planning an evening at the world-famous St. Louis Arch, complete with dinner, a jazz combo, tram rides to the top of the arch and time to tour the museum. Needless to say, it takes a great commitment of time, energy and skill to bring together such an event. I'd like to especially commend Chuck Mosher for his organizational skills as this year's vice president and program chair; George Kremenek and Marilynn Livingston for putting together the workshops; JoAnne Wold of Intel, who serves as our administrative secretary; and the many, many users who have volunteered as organizers, presenters and participants. And I hope to meet you all in St. Louis! Gary B. Lamont Air Force Institute of Technology (AFIT) Chair Intel Supercomputer Users' Group *************************************************************************** SAN DIEGO SUPERCOMPUTER CENTER INTRODUCES ENGINEERS AND SCIENTISTS FROM ACROSS THE NATION TO THE PARAGON(TM) SUPERCOMPUTER The San Diego Supercomputer Center (SDSC) recently featured its 400- compute-node Intel Paragon(tm) XP/S 30 supercomputer at the center's annual advanced computational science institute. The two-week, NSF- funded institute in August brought 23 researchers to SDSC to learn how parallel computing can be used in computational research. Participants alternately listened to expert lecturers and implemented their applications on the Paragon computer. "Intel and SDSC staff worked hard to make this Paragon computer-based institute happen," said Wayne Pfeiffer, SDSC deputy director for research. "That so many mostly inexperienced parallel computing users came up to speed in less than two weeks is a remarkable achievement for both the people and the machine," added Mark Sheddon, SDSC user services manager and institute director. What participants may have lacked in parallel computing experience, however, they made up for with experience in a variety of disciplines that can benefit from parallel computational approaches. Among the applications they brought to meet the parallel challenge were several computational fluid dynamics applications, including studies of turbulent flow, magnetohydrodynamics, aerodynamics, and smoothed particle hydrodynamics. Several others brought molecular dynamics and modeling studies, such as simulation of energy transfer and reaction dynamics in complex many-atom systems, quantitative methods for de novo protein design, and analysis of protein interactions. Astrophysics studies included simulations of galactic luminous tracer development, gravito-electrodynamics to explain Voyager spacecraft observations from outer planets, and the origin of astrophysical jets in active galactic nuclei. Other studies included partial differential equation techniques in computational electromagnetics, radiative transfer in rainy clouds using satellite-based remote sensing data, alignment of distantly related protein sequences and the construction of evolutionary trees, information processing and representation in the human brain, and large-scale combinational problems related to travel and information networks, facility layout and guided vehicle flow path. Participants were enthusiastic about the potential offered by parallel computing. "Parallel computers such as the Intel Paragon system allow rapid simulations, which are important to develop improved evaluation functions and search strategies [for modeling protein structures]," commented Bruce Duncan of The Scripps Research Institute. Duncan's project included developing techniques to model and predict the interaction of proteins whose molecular structures are known. Duncan feels that machines like the Paragon can influence the development of protein docking codes by cutting the time needed to analyze an evaluation function. After an evaluation function is determined using a parallel computer, production runs can be done on a workstation. Another researcher, Xiche Hu, from the University of California, Irvine, parallelized and implemented a molecular dynamics program called VENUS on the Paragon computer. Hu stated that VENUS represents a wide spectrum of classical trajectory programs that could also be parallelized. "Higher throughput in classical trajectory calculation will advance the study of molecular dynamics into more realistic systems involving more particles and more complicated potentials," he added. Maurice van Putten, a researcher from the University of California, Santa Barbara, parallelized a serial code for numerical simulation of astrophysical jets, stablized the code in the Paragon computer environment, and, with help from SDSC consultant Rama Ramachandran, produced a video of the results. The participants included three industry and government researchers, who paid to attend the institute, as well as 20 academic researchers chosen from among 60 applicants based on a project proposal and its applicability to parallel computing, among other information. Participants were given access to the Paragon computer until Oct. 1, and then could submit a formal proposal for an allocation on the machine. In addition to the institute activity, SDSC's Paragon computer is being used for several large, on-going research projects. Among these is a collaboration of physicists from the University of California, Santa Barbara, who are making calculations of the properties of elementary particles. Their runs are already reaching multi-gigaflops speeds. In another research endeavor, Kim Baldridge, SDSC computational chemist, is studying increasingly complex models of molecules using codes she has parallelized and ported to the Paragon computer. Biomedical researchers from several San Diego institutions have also begun to implement their applications on the machine. As part of a partnership agreement with Intel, SDSC systems programmers have developed software for automatic scheduling of jobs on Paragon systems. The scheduler is incorporated within the NQS batch system that is being released with the Paragon operating system software. To aid in the development of a distributed computing environment, SDSC networking specialists are testing High Performance Parallel Interface (HIPPI) connections between the center's Paragon and CRAY Y-MP supercomputers and a graphics frame buffer. The HIPPI connections, which allow data transfer at speeds up to 100 megabytes per second, will be used to display calculated data in near real-time and to run especially demanding applications simultaneously on more than one supercomputer. SDSC is a national laboratory for computational science and engineering located at the University of California, San Diego. SDSC has funding from the National Science Foundation, Advanced Research Projects Agency, the State of California, the University of California, and industrial partners. The center is operated by General Atomics, an energy R&D corporation. The SDSC Paragon supercomputer was installed at the center in February 1993 and upgraded to 400 compute nodes this summer. With this upgrade, the machine's peak speed is 40 gigaflops for 32-bit arithmetic, making it one of the world's fastest supercomputers. A special feature of the SDSC machine is that 64 of the 400 compute nodes have 32 MBytes of memory each, resulting in a total memory of over 7 Gbytes. The larger memory nodes should prove particularly useful in chemistry and climate modeling applications because both typically involve very large-sized problems. Marsha Jovanovic San Diego Supercomputer Center **************************************************************************** THIERRY PRIOL: A REPORT FROM THE EUROPEAN USERS' GROUP ANNUAL MEETING More than 40 attendees coming from seven European countries came together in Munich for the sixth annual conference of the European Intel Supercomputer Users' Group. The meeting was held June 18-19 as a satellite event of the PARLE '93 conference. For the first time, we increased the duration of the meeting to a day and half. Users' contributions were presented Friday, and a workshop dedicated to software optimizations was organized for Saturday morning. In addition, our first European Special Interest Group, which is devoted to the Paragon(tm) supercomputer, held its first meeting on June 17, preceding the conference. Friday was devoted to eleven user presentations, plus an update on activities of the U.S. Users' Group presented by Gary Lamont and an Intel product update by Ray Asbury and Peter Wolochow. The meeting ended with a presentation by Ed Masi, head of Intel SSD. His last slide was an empty student report card regarding the performance of the "Paragon student" with the objectives to meet in 1994. Ed Masi promises that "Paragon" will be a good student in 1994 since he said that its performance will increase during the next months. Ed asked Jutta Docter of KFA, who chairs the Paragon Special Interest Group, to be in charge of following the performance of this promising student. During the dinner that followed the meeting, Gary Lamont, who helped in the creation of the European User's group, was officially rewarded by receiving a Bavarian beer tankard. In fine Bavarian fashion, he drained it in one gulp, to the applause of all. A workshop on software optimization techniques, primarily for the Paragon supercomputer, was held Saturday morning. Talks about efficient global operations on a 2D mesh, OSF/1 issues and i860(tm) processor performance hints were presented mainly by Intel engineering staff members. A presentation of Forge 90 was made by a representative from Genias Gmbh. Despite it being the first day of the weekend, thirty users attended the meeting. The new Paragon ESIG is devoted to the Paragon supercomputer, since the number of European sites equipped with the new Intel system is growing quickly. The Paragon ESIG will allow Paragon users to share their experiences as well as to provide an interface with Intel engineering staff. Twenty-five users from current and future Paragon installations attended the meeting. Discussions revolved around the availability of new software functionalities and users reported their experiences with their machines. An electronic mailing list (esig-paragon@kfa-juelich.de) is available for exchanging information between users. Next ESIG meetings will be announced through the use of this mailing list. For any information concerning this ESIG, please send an e-mail to J. Docter (J.Docter@kfa- juelich.de). We also organized an executive board meeting where several ideas were discussed to improve the organization of the ESUG. A draft version of the European charter has been written and is still under discussion within the executive board members. It will be submitted to users soon. We also discussed the opportunity to open an ftp site in Europe to archive users' source codes for their Intel supercomputers. We also discussed the location of the next Users' Group meeting. We're tentatively planning to hold it in conjunction with the International Conference on Supercomputing Conference which will be held in Manchester (UK) in July 1994. I would like to thank Alastair McKeeman of Intel, who was responsible for organizing the conference program, and Jutta Docter, who was in charge of the organization of the Paragon ESIG. On behalf of the executive board, I would also like to express my gratitude to Intel for its support as well as to Intel staff members who attended the ESUG meeting. They did a great deal to ensure the quality of our meeting. Thierry Priol IRISA/INRIA Chair, European Intel Supercomputer Users' Group **************************************************************************** THE PARAIDE DEVELOPMENT ENVIRONMENT: NDUSTRY PERSPECTIVE FROM PROFESSOR CHERRI PANCAKE Intel's new ParAide Integrated Development Environment is among the strongest on the market and takes an important step toward making scalable supercomputers easy to program, according to Cherri M. Pancake, an assistant professor at Oregon State University and visiting scientist at the Cornell Theory Center. Dr. Pancake is a well-known user advocate in the HPC community. Her research focus is software support for high-performance computing, particularly parallel debuggers, performance tuning tools and parallel languages. She is the author of "Do Parallel Languages Respond to the Needs of Scientific Programmers?" (IEEE Computer), "Software Support for Parallel Computing -- Where Are We Headed?" (Communications of the ACM) and "What Should We Expect from Parallel Language Standards?" (International Journal of Supercomputer Applications). ParAide will be available this fall with Release 1.1 of the Paragon(tm) supercomputer operating system. It provides an integrated, graphical environment for monitoring, debugging and visualizing the performance of large-scale parallel applications. It also offers facilities for viewing system performance at any level of detail, from the system as a whole down to individual components. ParAide is designed around a Tools Application Monitor (TAM) that runs in parallel on the system's nodes and contributes to both performance and scalability. Dr. Pancake was interviewed by newsletter contributing editor Jan Rowell of Rowell Communications. ROWELL: You're familiar with the ParAide development environment, as well as with tool suites from a number of other parallel computer companies. How does ParAide compare to what's out there? PANCAKE: I think there are two or three areas where the ParAide tool suite is really very strong -- not only much stronger than Intel's previous offerings but also very strong in comparison to pretty much everything that's out on the market. I think this is due to some specific efforts that were made by the tools group, in cooperation with the operating system and other groups. They seem to have made a very conscious attempt to make distributed-memory parallelism, and specifically message passing, more tractable for the programmer. Second, they have been much more sensitive than their competitors have been to the very strong day-to-day limitations that affect real-world applications programmers. Third, they've made a very conscious and serious effort to use some of the latest technology to streamline how programmers use tools -- to make the programmer's task easier. I see these three factors coming together to produce a very strong tool suite for distributed-memory, message-passing programming. "Programmers do not turn to parallelism if they're satisfied running their application on a serial machine -- they'd be crazy to do that." Let me give you some examples of what I mean by making this paradigm more tractable. First of all, they put in a global clock. This has been one of the things that has been most frustrating to programmers of distributed-memory and message passing systems. The lack of a global clock meant that when you were debugging and trying to tune your program and you had these hundreds or thousands of activities happening at the same time, you could never really get a handle on what was happening when. To have an efficient hardware clock that is totally accurate and global across the system -- well, it should have been a requirement years ago, but the fact is, it's an absolute bonus for today's programmer. Another thing that helps make this message-passing paradigm more tractable is the fact that the debugger has message examination integrated into it. On most other systems, the programmer is responsible for doing print statements or otherwise recording the information if they want to examine the contents of the message queues in mid-stream, either for debugging or tuning. Another thing that's really critical is that the environment provides a technique for efficient monitoring of the program's progress, because the Tools Application Monitor itself -- the TAM -- runs in parallel. This is very unusual. It seems common sense that parallel tools would want to exploit parallelism, but that hasn't been the case. I think it was quite progressive of Intel to make the TAM parallel from the start. It means that the monitoring is efficient, and it fits into a model that I believe will turn out to be very scalable. ROWELL: You mentioned that you saw evidence of a greater sensitivity to the everyday concerns of parallel programmers. PANCAKE: One of the salient facts of parallel programming is that programmers do not turn to parallelism if they're satisfied running their application on a serial machine -- they'd be crazy to do it. But they've run into problems with either size or length of execution on a serial machine and that's why they're turning to parallelism. So a real-world program that's going to be put on a machine like the Paragon is first of all, huge; and second, likely to run for extremely long periods of time. There are several features in the Paragon development environment that particularly address this. One is that it's possible to monitor the performance of a parallel program without having to recompile it. This is something that most other vendors don't seem to understand is a problem -- but if your program is 200,000 lines long and incorporates hundreds or even thousands of files, it is a tremendous problem. Needing to recompile it solely so you can monitor it is totally impractical. "I mean, if I've got a program that runs for three weeks in regular mode, what's it going to do when I put a monitor on it?" Another "real-world" aspect is that programs are very long running, so you can't afford to monitor the entire thing. I mean, if I've got a program that runs for three weeks in regular mode, what's it going to do when I put a monitor on it? This is one advantage of having a really efficient monitoring system like the TAM provides. But it's also very important to allow the programmer to control which portions of the application need to be monitored. If I've decided to substitute a new algorithm for one routine, I'm only concerned with the piece of the program I changed, not with the initialization of my data structures and the generation of my graphical output. If I have to monitor the entire program, I not only have the problem of long run times, but also the incredible amount of monitoring output. So I see ParAide's selective monitoring as a very, very important feature. Another important feature that relates to practical, day-to-day parallel programming is the ability to look at the resource utilization of the machine. Say I've got this big program, and I know that if I can get hold of 64 nodes, I can run it in three days, but if I can only get a small number of nodes, it may take me a week and a half to run it. In the real world, I have to make that decision when I first submit the job. So it's very helpful to know who's using the system, how big the partitions are, how intensive the I/O traffic and communications traffic are. This information can tell me, perhaps, to wait until the weekend to submit my program, or it can tell me information on the partition sizes that I might want to use. This information typically is available only to the system administrator. In the Paragon system, though, there's a simple, easy-to-understand graphical tool that gives me this information. The ParAide System Visualization Tool makes it very easy to learn the couple of things that I really need to be paying attention to -- I can run the SPV, get a snapshot view of current utilization and make a decision about how to submit my job based on that information. ROWELL: What do you see in the ParAide environment in terms of making the tools easier to use? I know in your surveys of MPP users, you heard a lot of complaints about development tools. PANCAKE: That's right. When you talk to people about previous generations of parallel development tools, particularly users who are scientists and engineers rather than computer scientists, you find a very high percentage who do not use the tools that are available to them. They say it's too hard to learn the tool, or too hard to make sense of the data. They have a section of code that doesn't work or doesn't give them the performance they need. They call up a debugger or a performance tool and they face this blank screen, with no clues to help them answer the question, "What do I do next?" So they give up. "Graphical" means more than windows and menus; it means the use of non-textual elements. Most of the competitors' debuggers are purely textual...XIPD, on the other hand, allows you to watch the behavior of your program in graphical form." I see a lot of evidence in the ParAide environment of using the state-of-the- art in user interface technology and human factors knowledge to make the programmer's task easier. The first example of this is that XIPD, the ParAide debugger, is really graphical. A lot of parallel debuggers claim to be graphical because they have windows and menus. But "graphical" means more than windows and menus; it means the use of non-textual elements. Most of the competitors' debuggers are purely textual. There may be windows and menus, but there's nothing but text in the windows. At best, there might be a little teeny icon where you've set a breakpoint, but that's at best. XIPD, on the other hand, allows you to watch the behavior of your program in graphical form. It shows you a snapshot view that you can also control in graphical form; in other words, you directly manipulate the visualization in order to change and control what information you're seeing about your program. This is not done in other currently available parallel debuggers. Another important thing is that these tools are really geared to the target user community. They've been designed not just to be easy to use, but easy to use on an intermittent basis. The practical reality of parallel programming among scientists and engineers is that they don't use the tools on a day-to-day basis. They may work on their program, and then go off and do their science, and then come back and be ready to try out a new algorithm on an existing application or perhaps try out a new one. They essentially have to repeat the learning curve each time. The problem with most of the previous parallel tools, both from Intel and from other vendors, is that they relied on specialized commands and command languages -- which meant that each time I'm going to use a tool, I have to go back and start from scratch to learn this command language. Now, with ParAide, these tools are self-explanatory. They use all the latest user interface technology -- graphical techniques, windows, menus, online help facilities -- to take care of the fact that for many people developing parallel software, tools are not a one-time learning curve, they're a repeated learning curve. With ParAide, the programmer doesn't have to memorize anything, doesn't have to rely on his or her memory of what was done in a session that might have been six months ago. You don't have to face that blank screen, because the tools guide you on what to try next. The Intel tools always had good functionality underneath. Now it's easy for the programmer to get at that functionality, because it's easy to see what you need to do. "The Intel tools always had good functionality underneath. Now it's easy for the programmer to get at that functionality, because it's easy to see what you need to do." ROWELL: The Intel people talk about the tools environment being based on a commitment to open systems. From your perspective as someone who develops tools and who studies the use of tools, can you comment on what value you see in this approach? PANCAKE: In the long term, I see tremendous value. I think Intel's overall commitment to open systems in the tools environment may, in fact, be the most important investment that Intel could have made in the high performance computing environment. Again, let's take an example. We've already talked about the monitoring mechanism, the TAM -- it's efficient, it works in parallel, it's a great monitoring mechanism. And Intel has announced a commitment to make the interface to the TAM an open interface, and they're putting the hooks in place now so that in future releases, that interface will be open. What that's going to mean is that I as a tool developer at a university, at a national lab, inside a company, can decide what shortcuts my particular user community might find useful. Maybe I've got people working in quantum chromodynamics, maybe I'm a fluid dynamicist at an aerospace corporation. There are always going to be certain features that will be absolutely vital for me and my users that won't necessarily be general enough to warrant being in a commercial product. "I can take advantage of the whole TAM facility and come up with a domain-specific or an in-house-specific tool at a very small fraction of the development time it has traditionally cost. In the past, I would have had to write a tool from scratch. But once the interface to the TAM is open, I can tack on my style of visualization, say, for my QCD people, or provide a specific kind of performance evaluation that we need for specific in-house metrics. I can take advantage of the whole TAM facility and come up with a domain-specific or an in-house-specific tool at a very small fraction of the development time it has traditionally cost. Not only that, but I can have more confidence in the data I'm gathering, because I know that the information the TAM provides is accurate and correct, and therefore I can build on that base to provide accuracy and correctness in the tool I design. I also think Intel was very wise to support some of the de facto standards that have evolved in the message-passing world in terms of tools and message-passing systems. The Intel development team showed a real willingness to work with the developers of PVM, to work with the developers of ParaGraph. These tools were not developed at Intel, they're not in-house, but they're widely accepted, and having the tools or aspects of the tools as part of the ParAide development environment will help users move over to the Paragon system more easily. These kinds of choices demonstrate publicly Intel's commitment to open systems. And to the user, open systems are absolutely the road to the future. **************************************************************************** HIGH SCHOOLERS TACKLE PARALLEL COMPUTING AT SUPERQUEST NORTHWEST SUMMER INSTITUTE How does the human retina work? Can you train a computer to predict population growth? How do you prevent forest fires from raging out of control? Solutions to these questions and more were offered at the 1993 SuperQuest Northwest Summer Institute, not by trained scientists, but by high-school students. Four teams of students and their teacher/coaches were chosen to receive an all-expenses-paid trip to Reed College in Portland, Ore., one of five sites for SuperQuest '93, for a three week summer workshop and a chance to put their ideas to the test on Intel's iPSC(R)/860 supercomputer. Intel's Supercomputer Systems Division, the Oregon Graduate Institute and Reed College organized SuperQuest Northwest by planning the programs and providing staff support for instruction, consultation, system administration, scientist mentors and program management. Intel donated a 16-node iPSC/860 supercomputer to the state of Oregon for use in SuperQuest Northwest and other educational programs. SuperQuest Northwest is one of several national SuperQuest programs sponsored by the National Science Foundation and managed by Cornell University. Corporate sponsors for SuperQuest are Intel Corp., Digital Equipment Corp., Cray Research, Boeing Computer Services, IBM Corp., Cisco, Inc., and Advanced Digital Communications Consortium. The teams chosen to attend the Oregon program were from Lee's Summit High School in Lee's Summit, Mo., Albuquerque Academy in Albuquerque, N.M., Ironwood High School in Glendale, Ariz., and Monte Vista High School in Danville, Calif. Research topics were in physics, medicine and health, mathematics and zoology. Each team submitted a research proposal outlining the problems they hoped to solve and how they planned to apply supercomputing technology and resources to the research. Proposals were judged on their scientific content, effectiveness of computational approach and clarity. During the three-week program, students and teachers had the opportunity to discuss their research with scientist mentors currently working in the field and to learn first-hand the latest technology in optimization methods, visualization and parallel processing. They converted their project software to run on the iPSC/860 and continued advancing their research. At the end of the program, the teams presented their research and conclusions to the other teams and organizers of the event. The teams also received an Internet connection to the iPSC/860 for one year, as well as stipends for their research. All the teams were able to run their programs on the iPSC/860, and this year's institute was even more successful than last year's event, said Summer Institute director Gary Shlickeiser, director of networking and technical services at Reed College. "This was our second year, and everything ran very smoothly. We were impressed with how much the students learned in just a few weeks." Students from the Lee's Summit group, whose project was called, "The Retina, Window to the Mind," said they were grateful for the opportunity to participate in SuperQuest. "Computers are the future, and now we are a part of it too," said Jennifer Watrous. As for what they thought of working with parallel supercomputers, Scott Redding had the final word: "It was neat." **************************************************************************** THE INTEL NEWS ROUND-UP New Paragon(tm) XP/E Systems Target Entry-Level Supercomputing A new line of smaller Paragon(tm) supercomputer configurations are aimed at sites that need low-cost supercomputing systems or development platforms for larger, remote Paragon machines. Dubbed the Paragon XP/E systems, the new machines are available in configurations ranging from 8 to 28 nodes, with peak performance of 600 MFLOPS to 2.1 GFLOPS. The first production model of the 2.1 GFLOPS system, the Paragon XP/E-28N, will be on hand at the Intel Supercomputer Users' Group Annual Conference in St. Louis, Mo., Oct. 3-6. The XP/E systems offer the standard Paragon system software set, and applications developed on them are binary compatible and scale the same as on Paragon XP/S systems. *** Paragon(tm) Interconnect, Pentium(tm) Processor, Unisys Software Come Together in Intel/Unisys Scalable Computing Initiative Intel has joined forces with one of the giants of mainframe and client/server computing to move scalable computing into the business and commercial mainstream. Intel and Unisys Corp. will develop prototypes of a scalable high- performance computer based on Intel's Pentium(tm) microprocessor and Paragon mesh interconnect technology and Unisys' operating system and other software. Intel will provide Unisys with prototype development platforms resulting from joint design efforts between the two companies. Unisys will use these platforms to develop advanced software, using the microkernel UNIX* operating system Unisys has developed in conjunction with Chorus* Systems and UNIX System Laboratories. Unisys will also develop distributed database applications software for the new system. "This is a strategic alliance that enables the Supercomputer Systems Division to move our scalable technology and expertise into traditional mainframe business and commercial markets while maintaining our strong focus on the scientific and technical marketplace," said Christina Blackwell, manager of OEM marketing and sales at Intel. "The combination of the Paragon interconnect's scalability and high bandwidth with the high integer arithmetic performance of the Pentium processor should produce a very cost-effective and powerful architecture for transaction-oriented applications and other business computing." *** Intel, Sandia National Laboratories Sign CRADA Focusing On C++ Intel and Sandia National Laboratories have signed a three-year Cooperative Research and Development Agreement (CRADA) to commercialize parallel algorithm and programming technology developed at Sandia in the object-oriented C++ programming language. The two organizations will work together on a set of scalable parallel object classes and libraries for C++, as well as C++ software such as linear equation and eigenvalue solvers, grid decomposition techniques, and parallel rendering and visualization algorithms. *** Intel And Portland Group Announce Compiler Development Plans Intel and the Portland Group Inc. (PGI) are jointly developing compilers for High Performance Fortran, Fortran 90 and C++ for the Paragon computer. The new compilers will take advantage of optimized code-generation technology developed by Intel and PGI for existing Paragon system compilers. Intel and PGI will collaborate to maximize compiler performance for the Paragon supercomputer's current architecture, as well as for future generations of Paragon processing nodes. *** Lamb, Furnanz Take Software, Hardware Management Posts Eli Lamb and Les Furnanz are filling new posts at Intel's Supercomputer Systems Division: Lamb as director of software engineering and Furnanz as director of hardware engineering. Justin Rattner remains SSD's director of technology, focusing on long-term technology and product directions. Lamb joined Intel from SunSoft*, a Sun* Microsystems company, where he was most recently the director of operating system technology. He was responsible for evolving SunSoft's operating system strategy and for implementing the Solaris* 2.x (SunOS 5.x) operating systems. His responsibilities at SSD include systems software for the Paragon supercomputer, as well as the development and enhancement of compilers and application development tools. Furnanz oversees hardware system sustaining and development of the Paragon line of supercomputer. Furnanz is a 17-year Intel veteran, and has managed the development of Intel products ranging from single-board computers and subsystems to the iWarp(tm) product line, which was his most recent responsibility. In other personnel moves, Hans Derksen has joined SSD-Europe to manage sales, service and operations on the European continent. Derksen most recently was a strategic business consultant in Switzerland. He previously held executive positions in sales, service and marketing during a 20-year career with Digital Equipment Corp. in Geneva. Adrian S. King, formerly a senior technical staff member at Sandia National Labs, has moved to Intel, where he now works with supercomputer customers in the development of computational electromagnetics (CEM) applications. Dr. King pioneered the use of the hybridization of several solution techniques for CEM problems on scalable systems and has published more than 100 papers on CEM. Also joining Intel's ranks recently is Timothy G. Mattson, most recently of Yale University and Scientific Computing Associates. Dr. Mattson, a computational chemist, reports that his first love is quantum scattering theory and his second love is parallel computing. At Intel, he combines the two, dividing his time between the math libraries group, where he works on a variety of parallel mathematical libraries, and the marketing department, where he focuses on the computational chemistry marketplace and parallel programming environments. *** Intel Donates 32-Node iPSC(R)/860 to UC Davis A32-node iPSC(R)/ 860 computer donated by Intel to the University of California at Davis is "one of the most significant equipment gifts we've ever received," according to M.S. Ghausi, dean of the university's college of engineering. The system will be used by a cross section of engineering faculty and students for applications including circuit simulation, computational fluid dynamics and reservoir modeling. ### iPSC is a registered trademark and Paragon, Pentium and i860 are trademarks of Intel Corporation. *All other brands and names are the property of their respective owners. Copyright 1993 by the Intel Supercomputer Users' Group. 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