%T Using CSP to Verify Aspects of an Occam\-to\-FPGA Compiler
%A  Roger M. A. Peel,  Wong Han Feng Javier
%E Ian R. East, David Duce, Mark Green,  Jeremy M. R. Martin, Peter H. Welch
%B Communicating Process Architectures 2004
%X This paper reports on the progress made in developing
   techniques for the verification of an occam to FPGA
   compiler.The compiler converts occam programs into logic
   circuits that are suitable for loading into
   field\-programmable gate arrays (FPGAs). Several levels of
   abstraction of these circuits provide links to conventional
   hardware implementations. Communicating Sequential Processes
   (CSP) has then been used to model these circuits. This CSP
   has been subjected to tests for deadlock and livelock
   freedom using the Failures\-Divergence Refinement tool
   (FDR). In addition, FDR has been used to prove that the
   circuits emitted have behaviours equivalent to CSP
   specifications of the original occam source codes.