%T Synchronisation in a Multithreaded Processor
%A  Shondip Sen,  Henk Muller,  David May
%E Peter H. Welch,  Andr\[`e] W. P. Bakkers
%B Communicating Process Architectures 2000
%X A multithreaded architecture exploits instruction level
   parallelism by interleaving instructions from disjoint
   thread contexts. As each thread executes within its own
   instruction stream with private data (the context
   registers), there is no interdependency between instructions
   from different threads. This allows high resource
   utilisation of a super scalar pipelined processor at a very
   low cost, in terms of complexity and silicon area. A new
   synchronisation mechanism for a multithreaded architecture
   is outlined. Two new instructions have been introduced to
   perform one to one and n\-way synchronisation. The operation
   allows synchronisations to be requested and actioned
   efficiently on chip in as little as four clock cycles.
   Barriers and CSP style channels can easily be constructed
   with this new synchronisation instruction. A brief
   examination of performance of this multithreaded
   architecture shows that the optimum number of contexts per
   multithreaded processing element is four, based on test
   programs.