%T Reconfigurable Computing
%A  Roger Gook
%E  Andr\[`e] W. P. Bakkers
%B Proceedings of WoTUG\-20: Parallel Programming and Java
%X The name may be familiar of old to the WoTUG community, but
   it has now been adopted by one of the fastest growing
   sectors of the silicon industry. Reconfigurable Computers
   are computing systems whose hardware architecture can be
   modified by software to suit the application at hand. The
   core component is the FPGA. Remarkable performance gains are
   achieved by placing an algorithm in an FPGA for embedded
   applications, compared with using a microprocessor or DSP.
   This is because an FPGA takes advantage of hardware
   parallelism while reducing the timing overheads needed for
   general\-purpose microprocessor applications. For example
   the time taken by load/store operations and instruction
   decoding can be eliminated. Reconfiguration enables the FPGA
   to provide a problem specific computer for highly optimised
   application performance. Just as high level programming
   languages liberated the first microprocessors programming
   languages will liberate the FPGA. The first of these
   languages to become commercially available is Handel\-C.
   Handel\-C is based on the CSP Model; it was developed by the
   Hardware Compilation Group at the University of Oxford and
   is to be marketed by ESL. The Handel\-C tools enable a
   software engineer to target directly FPGAs in a similar
   fashion to classical microprocessor cross\-compiler
   development tools, without recourse to a Hardware
   Description Language. Thereby allowing the software engineer
   to directly realise the raw real\-time processing capability
   of the FPGA. The skills and expertise gained by the WoTUG,
   provide the group with a competitive advantage to develop
   the innovative algorithms, applications and products in this
   domain.