@InProceedings{PeelJavier04,
  title =        "{U}sing {CSP} to {V}erify {A}spects of an {O}ccam-to-{FPGA} {C}ompiler",
  author=        "Peel,  Roger M. A. and Javier,  Wong Han Feng",
  editor=        "East, Ian R. and Duce, David and Green, Mark and Martin,  Jeremy M. R. and Welch, Peter H.",
  pages =        "339--352",
  booktitle=     "{C}ommunicating {P}rocess {A}rchitectures 2004",
  isbn=          "1 58603 458 8",
  year=          "2004",
  month=         "sep",
  abstract=      "This paper reports on the progress made in developing
     techniques for the verification of an occam to FPGA
     compiler.The compiler converts occam programs into logic
     circuits that are suitable for loading into
     field-programmable gate arrays (FPGAs). Several levels of
     abstraction of these circuits provide links to conventional
     hardware implementations. Communicating Sequential Processes
     (CSP) has then been used to model these circuits. This CSP
     has been subjected to tests for deadlock and livelock
     freedom using the Failures-Divergence Refinement tool (FDR).
     In addition, FDR has been used to prove that the circuits
     emitted have behaviours equivalent to CSP specifications of
     the original occam source codes."
}