db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{McConnellWinser01,
title = "{A} 40 {G}bit/s {N}etwork {P}rocessor {D}esign {P}latform",
db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "McConnell, R. and Winser, P.",
db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk",
db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "193--212",
booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001",
isbn= "1 58603 202 X",
year= "2001",
month= "sep",
abstract= "As the Internet evolves, the rapidly increasing demand for
bandwidth is matched by a greater need for more intelligence
with which to manage and meter the flow of that data to
sustain economic growth. Conventional processing
architectures and hardwired point solutions are not suited
to these conflicting demands; there is an emerging need for
a new approach for this data flow processing problem. This
paper presents ClearSpeed's integrated Network Processor
design platform that embodies many different levels of
parallel processing. Designed to balance the bandwidth needs
with programmability we introduce the MTAP architecture. An
area and power efficient, fine-grained, scalable,
multi-threaded parallel processor, designed with a
'bandwidth-centric' architecture and programmed in C. Based
on the ClearConnectâ„¢ bus, an SoC communication
architecture with VCI compliant interfaces, a high-bandwidth
system architecture including a number of hardware
accelerator units is also described. An example 40Gbit/s
programmable and scalable classifier/forwarder is presented,
embodying the concepts of the platform. To complete the
picture, a comprehensive suite of software and hardware
development tools is described."
}