@InProceedings{BalboniCabodi92,
  title =        "{A} transputer-based accelerator for digital circuits fault simulation",
  author=        "Balboni,  G. P. and Cabodi,  G. P. and Gai,  S. and Reorda,  M. Sonza",
  editor=        "Allen,  Alastair R.",
  pages =        "180--186",
  booktitle=     "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch",
  isbn=          "90 5199 085 5",
  year=          "1992",
  month=         "mar",
  abstract=      "Fault simulating digital devices requires powerful tools
     able to deal with their increased size and complexity.
     Software simulators are often unable to satisfy the needs of
     designers and test engineers due to the size of the
     simulated circuits, and to the large number of faults;
     hardware accelerators have been proposed to solve the
     problem. We present a system running on a net of transputers
     which uses a fault-partitioning strategy to fully exploit
     the available processors. The results show that this
     solution can represent a good trade-off between the cost of
     the system and the obtained speed-up."
}