@InProceedings{Shepherd87, title = "{S}ecurity aspects of occam 2", author= "Shepherd, Roger", editor= "Muntean, Traian", pages = "1--8", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{ONeil87, title = "{T}he {TDS} occam 2 debugging system", author= "O'Neil, C.", editor= "Muntean, Traian", pages = "9--14", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Jones87, title = "{O}n guards", author= "Jones, Geraint", editor= "Muntean, Traian", pages = "15--24", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Pritchard87, title = "{M}athmatical models of distributing computation", author= "Pritchard, D.", editor= "Muntean, Traian", pages = "25--36", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Goldsmith87, title = "{O}ccam transformation at {O}xford", author= "Goldsmith, Michael", editor= "Muntean, Traian", pages = "37--54", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Roscoe87, title = "{R}outing messages through networks: {A}n exerecise in deadlock avoidance", author= "Roscoe, A. W.", editor= "Muntean, Traian", pages = "55--79", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{CrookesMilligan87, title = "{LATIN} -- {A} language for transputer networks", author= "Crookes, D. and Milligan, P. and Scott, N. S. and Kilpatrick, P. L. and Morrow, Philip J.", editor= "Muntean, Traian", pages = "80--95", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{McBurneySleep87, title = "{E}xperiments with a transputer-based diffusion architecture", author= "McBurney, D. and Sleep, M. R.", editor= "Muntean, Traian", pages = "96--107", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Dodd87, title = "{M}ultilayer perceptrons on transputer networks", author= "Dodd, N.", editor= "Muntean, Traian", pages = "108--119", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{JohannetLoheac87, title = "{A} transputer based neurocomputer", author= "Johannet, A. and Loheac, G. and Personnaz, L. and Guyon, I. and Dreyfus, G.", editor= "Muntean, Traian", pages = "120--127", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{MartoranaMigliore87, title = "{P}arallel implementations of a molecular dynamics program for {L}ennard-{J}ones particles on transputer network", author= "Martorana, V. and Migliore, M. and Fornilli, S. L.", editor= "Muntean, Traian", pages = "128--134", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Welch87, title = "{M}anaging real-time demands on transputers", author= "Welch, Peter H.", editor= "Muntean, Traian", pages = "135--145", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Burns87, title = "{O}ccam's priority model and deadline scheduling", author= "Burns, A.", editor= "Muntean, Traian", pages = "146--159", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{CaponWest87, title = "{M}onitoring occam channels by program transformation", author= "Capon, Peter C. and West, Adrian J.", editor= "Muntean, Traian", pages = "160--169", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{MunteanTricot87, title = "{O}perating models for (reconfigurable) transputer networks", author= "Muntean, Traian and Tricot, C.", editor= "Muntean, Traian", pages = "170--185", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{MeierWespi87, title = "{A}n analysis and reconfiguration tool for mapping parallel programs onto transputer networks", author= "Meier, D. Ch. and Wespi, A. and Boillat, J. E. and Kropf, P. G.", editor= "Muntean, Traian", pages = "186--194", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{BartonEdwards87, title = "{A}n occam architecture for reconfigurable systems", author= "Barton, M. H. and Edwards, N. J.", editor= "Muntean, Traian", pages = "195--209", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{MevenkampStreitz87, title = "{T}ransputer and parallel computation at the {GMD}", author= "Mevenkamp, M. and Streitz, S.", editor= "Muntean, Traian", pages = "210--220", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Reynolds87, title = "{T}ransputers and parallel prolog", author= "Reynolds, J.", editor= "Muntean, Traian", pages = "221--228", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{BosleyMortimer87, title = "{A} real time prolog compiler for multi- transputer architectures for knowledge based systems applications", author= "Bosley, D. and Mortimer, J.", editor= "Muntean, Traian", pages = "229--238", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Dixon87, title = "{D}ata structures for parallel architectures in artificial intelligence", author= "Dixon, A.", editor= "Muntean, Traian", pages = "239--251", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{HarpWebber87, title = "{I}mage processing on the reconfigurable transputer processor", author= "Harp, J. G. and Webber, H. C.", editor= "Muntean, Traian", pages = "252--260", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Kerridge87, title = "{DRAT} -- {A} proposal for a dynamic reconfigurable array of transputers to support database applications", author= "Kerridge, Jon", editor= "Muntean, Traian", pages = "261--271", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{StepneyGRAIL87, title = "{GRAIL} -- {G}raphical representation of activity, interconnection and loading", author= "Stepney, S. and GRAIL, ", editor= "Muntean, Traian", pages = "272--280", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{KermarrecRannou87, title = "{A} transputer network simulator", author= "Kermarrec, Y. and Rannou, R.", editor= "Muntean, Traian", pages = "281--296", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{MeriauxAtamenia87, title = "{A} transputer-based architecture for graphics", author= "Meriaux, M. and Atamenia, A. and Lepretre, E.", editor= "Muntean, Traian", pages = "297--306", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Gorton87, title = "{A} distributed architecture for simulating microprocessor systems", author= "Gorton, I.", editor= "Muntean, Traian", pages = "307--317", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{BakkersRooij87, title = "{D}esign of a real-time operating system ({RTOS}) for robot control", author= "Bakkers, Andr\`{e} W. P. and Rooij, R. Van and James, L.", editor= "Muntean, Traian", pages = "318--327", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{TianXu87, title = "{U}se of occam and the transputer architecture for matrix inversion", author= "Tian, S. and Xu, G. and Pao, Y-H. and Schultz, W. L.", editor= "Muntean, Traian", pages = "328--338", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{MicheauxMaurin87, title = "{C}omputational statistics on a multi-transputer architecture", author= "Micheaux, D. Lafaye de and Maurin, A.", editor= "Muntean, Traian", pages = "339--364", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{FavreCoray87, title = "{A} parallel processing architecture for {ODE}s", author= "Favre, J. M. and Coray, C. S.", editor= "Muntean, Traian", pages = "365--377", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{CosnuauPoirel87, title = "{S}ome numerical experiments on transputer networks", author= "Cosnuau, A. and Poirel, O.", editor= "Muntean, Traian", pages = "378--388", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{AlvesOwen87, title = "{U}sing transputers in finite elements calculations: {A} first approach", author= "Alves, J. S. R. Filho and Owen, D. R. J.", editor= "Muntean, Traian", pages = "389--401", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{WybransKurver87, title = "{T}he development of a parallel {C} compiler", author= "Wybrans, K. and Kurver, R.", editor= "Muntean, Traian", pages = "402--410", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Garnett87, title = "{HELIOS} -- {A}n operating system for the transputer", author= "Garnett, N. H.", editor= "Muntean, Traian", pages = "411--419", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Hilhorst87, title = "{P}arallelisation of computational algorithms for a transputer network: {A}n approach", author= "Hilhorst, R.", editor= "Muntean, Traian", pages = "420--424", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{NiarGoncalves87, title = "{T}he occam process of the {N}-{ARCH} {K}ernel", author= "Niar, S. and Goncalves, G. and Lecouffe, M. P. and Toursel, B.", editor= "Muntean, Traian", pages = "425--432", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Patry87, title = "{O}ptical character recognition on a network of transputers", author= "Patry, P.", editor= "Muntean, Traian", pages = "433--448", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Call87, title = "{T}he knapsack solver: {A} benchmark for parallel computing systems", author= "Call, D.", editor= "Muntean, Traian", pages = "449--466", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{GasilloudMignot87, title = "{R}ay-tracing on super-node", author= "Gasilloud, D. and Mignot, B.", editor= "Muntean, Traian", pages = "467--472", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{AnsadeCornuEmie87, title = "{S}imulation fonctionnelle d'une architecture parallele en occam", author= "Ansade, Y. and Cornu-Emieux, R. and Lattard, D. and Mazare, G. and Objois, Ph.", editor= "Muntean, Traian", pages = "473--479", booktitle= "{OUG}-7: {P}arallel {P}rogramming of {T}ransputer {B}ased {M}achines", isbn= "90 5199 0073", year= "1987", month= "sep", } @InProceedings{Morrow88, title = "{A} comparison of two notations for programming image processing applications on transputers", author= "Morrow, Philip J.", editor= "Kerridge, Jon", pages = "1--10", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{HortonTurner88, title = "{D}ynamic processes in occam", author= "Horton, I. A. and Turner, Stephen J.", editor= "Kerridge, Jon", pages = "11--22", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{Culloch88, title = "{P}arallel programming toolkit for 3{L} -- {C} {FORTRAN} and {P}ascal", author= "Culloch, Alan D.", editor= "Kerridge, Jon", pages = "23--30", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{Winder88, title = "{P}arallel processing with the disputer", author= "Winder, C. P.", editor= "Kerridge, Jon", pages = "31--44", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{GowardLeler88, title = "{PIX}: {N}e{WS} for parallel computers", author= "Goward, P. and Leler, W.", editor= "Kerridge, Jon", pages = "45--52", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{HendrikxHacking88, title = "{O}ccam and transputers for industrial applications", author= "Hendrikx, H. A. M. and Hacking, R. J.", editor= "Kerridge, Jon", pages = "53--54", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{MillsONeill88, title = "{T}ransputer instrumentation applied to electrostatic powder flow measurement", author= "Mills, E. and O'Neill, Brian C.", editor= "Kerridge, Jon", pages = "55--62", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{EllisonNatanson88, title = "{A} talking bee on the transputer", author= "Ellison, D. and Natanson, L.", editor= "Kerridge, Jon", pages = "63--76", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{NormanFisher88, title = "{S}urface tracking within three dimensional datasets using a generalised message-passing system", author= "Norman, M. G. and Fisher, R. B.", editor= "Kerridge, Jon", pages = "77--82", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{TanRichards88, title = "3{D} medical graphics -- using the {T}800 transputer", author= "Tan, A. C. and Richards, R. and Linney, A. D.", editor= "Kerridge, Jon", pages = "83--90", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{Heal88, title = "{T}ransputer implementation of a graphics pipeline for octree encoded objects", author= "Heal, B. W.", editor= "Kerridge, Jon", pages = "91--100", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{DowningBennett88, title = "{M}ulti-transputer based parallel implementation of feature extraction for object recognition", author= "Downing, D. W. and Bennett, I. B.", editor= "Kerridge, Jon", pages = "101--112", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{Cok88, title = "{A} medium grained parallel computer for image processing", author= "Cok, R.", editor= "Kerridge, Jon", pages = "113--124", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{Cormack88, title = "{R}eal-time processing of large volume data from photographic plate measurements", author= "Cormack, W. A.", editor= "Kerridge, Jon", pages = "125--136", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{BowlerMorse88, title = "{A}daptive routing techniques in simulated computer networks", author= "Bowler, M. C. and Morse, M. J. and Frydas, N.", editor= "Kerridge, Jon", pages = "137--146", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{NicoleLloyd88, title = "{S}witching networks for transputer links", author= "Nicole, Denis A. and Lloyd, E. K. and Ward, J. S.", editor= "Kerridge, Jon", pages = "147--166", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{Peel88, title = "{U}sing transputers in an ethernet environment", author= "Peel, Roger M. A.", editor= "Kerridge, Jon", pages = "167--172", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{Richards88, title = "{I}mplementation of back-propogation on a transputer array", author= "Richards, G.", editor= "Kerridge, Jon", pages = "173--180", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{HullBell88, title = "{C}oncurrency in database management systems design and implementation", author= "Hull, M. E. C. and Bell, F. J.", editor= "Kerridge, Jon", pages = "181--204", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{Wylie88, title = "{C}ellular automaton lattice gas hydrodynamics on a parallel supercomputer", author= "Wylie, B. J. N.", editor= "Kerridge, Jon", pages = "205--214", booktitle= "{OUG}-8: {D}evelopments {U}sing {O}ccam", isbn= "90 5199 002 4", year= "1988", month= "feb", } @InProceedings{Bakkes88, title = "{V}irtual memory management for the transputer", author= "Bakkes, P. J.", editor= "Askew, Charlie", pages = "1--6", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "During the last decade a number of microprocessors appeared on the market with operating system mechanisms designed into the firmware e.g. the Intel 80286 which supports segmented memory management and the 80386 supporting segmentation and paging. The idea was very attractive as protection amongst users could be enforced by the hardware. The support of multi-users on one processor implied the conventional strategy of sharing the scarce processor resource amongst more than one user. The limitations in processing power of microprocessors did however limit their multi-user exploitation." } @InProceedings{Grimsdale88, title = "{CDL} -- {A} distribution language for {HELIOS}", author= "Grimsdale, C. H. R.", editor= "Askew, Charlie", pages = "7--12", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "Helios is an Operating System designed to exploit highly distributed systems. The central goal of such a distributed system, is not only to provide increased fault tolerance, but also increased performance. This necessitates adequate support for parallelism at the application level. It is proposed that instead of extending an existing language, or producing a completely new language, parallelism can be defined at the distribution phase. A high level Component Distribution Language has been designed, which allows simple sequential components to be combined by simple parallel constructors to form more complex parallel structures. The implementation language is irrelevant thus providing consistent support for standard sequential languages in a distributed environment." } @InProceedings{CroweStrainCla88, title = "{A} concurrent approach to the {T}owers of {H}anoi", author= "Crowe, W. D. and Strain-Clark, P. E. D.", editor= "Askew, Charlie", pages = "13--22", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "The tower of Hanoi problem has long been known to have a closed (ie non-recursive) solution. In this paper we analyse two approaches to this solution which involve concurrency. This is not an end in itself, but serves to introduce the main ideas and notations of CAP (Communicating Asynchronous Processes) - a revision of CSP which the authors have used successfully to develop correct Occam programs. In turn, CAP is part of a wider development method (ODM) which is being studied with the intention of prototyping software tools to assist developers of concurrent software." } @InProceedings{Zhang88, title = "{A}n {OCCAM}@ implementation of prolog and its preliminary performance", author= "Zhang, Kang", editor= "Askew, Charlie", pages = "23--36", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "The paper presents an execution model for Prolog, which attempts to exploit the parallelism mainly at the argument level through the unification operation. The model, consisting of a number of virtual machine instructions, has been implemented in Occam2 on a Transputer Development System (TDS). The performance of the pure software implementation has been evaluated in real-time. The speed, as assessed by running a few hand compiled benchmark programs on the TDS with a single transputer, ranges from 7-18 KLIPS. The paper gives some details of the performance, and then proposes a dataflow-based functionally distributed configuration of the multitransputer system." } @InProceedings{BarrettGoldsmith88, title = "{T}he meaning and implementation of {PRI} {ALT} in occam", author= "Barrett, Geoff and Goldsmith, Michael and Jones, Geraint and Kay, A.", editor= "Askew, Charlie", pages = "37--46", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "This paper describes what we believe to be an error in the implementation of PRI ALT on the Inmos transputer, and exhibits anomalous behaviour of that implementation. A correct implementation of comparable complexity is described, and some of the properties of the construct are described. Finally, an attempt is made to describe circumstances in which the behaviour of the existing implementation is adequate for the correctness of a program which uses it." } @InProceedings{PatelBentley88, title = "{S}imulation of gas pipeline networks", author= "Patel, Minesh and Bentley, Paul and Hughes, Clifton", editor= "Askew, Charlie", pages = "47--52", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "As part of the Alvey ParSiFal project, Logica Cambridge has been developing a model of a significant gas distribution network, in order to explore the potential for improvements in modelling speed using large numbers of transputers.There are two basic approaches to continuous simulation - the explicit and the implicit. The implicit approach models an entire system as a set of equations. Current implementations are well suited to conventional mono-processor machines but it is difficult to parallelize the algorithm and consequently to fully exploit the potential of transputers.The explicit approach models components such as pipes as individual objects which can be directly mapped into parallel processes, making it ideally suited to the transputer/occam architecture. However, explicit simulation is inherently expensive in terms of computational resources. To enhance performance we are also working on improvements to the model.We have developed a system using an explicit algorithm and have simulated networks ranging from 20 to 500+ objects. Preliminary results indicate that the explicit algorithm can efficiently exploit high degrees of parallelism." } @InProceedings{GreenPaddon88, title = "{A}n extension of the processor farm using a tree architecture", author= "Green, S. A. and Paddon, Derek J.", editor= "Askew, Charlie", pages = "53--70", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "For problems that require a small database a processor farm model was proposed by May and Sheppard, and has subsequently had much success. Here, we assume that the database is too large to store completely at each node of the farm and consequently, data must be communicated throughout the network during the execution of a problem. The processor farm model is extended to allow work tasks to be completed when data items not resident locally at a node can be obtained by making a request for data across the network. The farm model is further extended by configuring the system as a tree topology. The extended farm topology is evaluated by using a set of graphics benchmark problems. Benchmark results are given for a tree farm of upto fifteen worker processors." } @InProceedings{OharaIizuka88, title = "{A} preprocessor to augment the description of occam processes for multitransputer machines", author= "Ohara, Hiromi and Iizuka, Hajime", editor= "Askew, Charlie", pages = "71--80", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "This paper describes a preprocessor which is designed to make the description of parallel processes of Occam easier. It takes a source program written in ordinary Occam language and a description of the configuration of the hardware on which it is intended to run. The programmer need not consider the particular hardware structure. The preprocessor assigns each process to an appropriate processor and produces the Occam program with process-to-processor allocation statements. Design philosophy, implementation details and some results are shown." } @InProceedings{QiangTurner88, title = "{R}andomised routing: \"{H}ot potato\" simulations", author= "Qiang, Xu Ming and Turner, Stephen J.", editor= "Askew, Charlie", pages = "81--90", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "In this paper, we describe experiments which simulate communication in a network of processors organised as a hypercube. A stochastic model o\pounds communication has been implemented in which each processor chooses at random another processor in the network with which to communicate. Deterministic and randomized routing algorithms are compared with respect to both the time taken for packets to reach their destinations and the space required for packet queues. A mixed strategy is discussed and evaluated which combines some of the advantages of each method. Questions of fault tolerance are also discussed and possible solutions presented." } @InProceedings{LauShea88, title = "{M}apping a process network onto a processor network", author= "Lau, Francis C. M. and Shea, K. M.", editor= "Askew, Charlie", pages = "91--100", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "This paper addresses the problem of mapping an Occam program onto a transputer network. This mapping is essentially a graph embedding (or related) problem: i.e., find a function f: N -\> \{ 1, 2.....\textbar M \textbar\} such that certain performance criteria would be satisfied, where N is the set of processes in the Occam program (the graph) and M is the set of processors in the transputer network. Depending on the complexity of the graph as well as the target transputer network, many of these problems are NP-complete [1,2]. This paper addresses not the mapping algorithm and how it may achieve optimality, which is a policy matter, but the mechanism of mapping - that is, given a mapping algorithm, what exactly do we do to transform the program into an equivalent program that is ready to be downloaded onto the transputer network. Our answer is a precompiler which we have successfully implemented. We discuss several important problems that occurred in our construction of the mapping procedure, and briefly describe the actual implementation of the precompiler." } @InProceedings{JonesMurta88, title = "{S}upport for occam channels via dynamic switching in multi-transputer machines", author= "Jones, Peter and Murta, Alan", editor= "Askew, Charlie", pages = "101--112", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "The authors are motivated by the disparity between the arbitrarily large degree of inter-process connectivity allowed in the occam model of computation (by means of occam channels) and the implementation of that model on the Inmos transputer (under the familiar four links per processor constraint). A communication technique has been developed and implemented on the ParSiFal machine which addresses this problem. The method involves a novel use of switching hardware. In normal use, links between transputers in a variable topology array such as the ParSiFal machine are arranged using switching hardware to form a static network before the application is loaded. This study explores the run-time reconfiguration of the switch network under the direction of transputers executing user code, by means of a request-resource / relinquish-resource protocol." } @InProceedings{Renterghe88, title = "{T}he computing tower: {A} supercomputer for real- time simulation of continuous systems", author= "Renterghem, Patrick van", editor= "Askew, Charlie", pages = "113--124", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "Computer simulation of systems (e.g. magnetic fusion, nuclear power plants, weather forecasting, ...) will have a strong impact on theoretical and experimental research in the future, because experiments on real systems are impossible due to the danger, the cost or the duration of the experiment. Computer simulation of a system is therefore an attractive alternative. Generally, large and complicated systems are simulated, so this requires an enormous amount of computing power. In this paper, we describe the possibility to use a home-built multitransputersystem, The Computing Tower, for system simulation and methods to implement a block-structured simulation language on this system the most efficient way." } @InProceedings{SinclairKelly88, title = "{T}he application of transputers and occam to an industrial energy management system", author= "Sinclair, Andy and Kelly, Paul", editor= "Askew, Charlie", pages = "125--134", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "The work described here is part of a larger project to provide a knowledge-based decision support system to offer advice on the control and utilisation of energy within a large integrated steel works. It is concerned with the electricity power generation subsystem of the steelworks. The aim of this work is to produce a decision support system that will give advice on the steam distribution required to maximise the power output of three turbines when viewed as a system. This paper is concerned with the practical details of implementing such a system in an industrial environment" } @InProceedings{Skillicor88, title = "{F}ast prototyping of architectural designs using transputers", author= "Skillicorn, David B.", editor= "Askew, Charlie", pages = "135--138", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "The existence of a processor with on-board communication facilities, such as the transputer, makes it possible to prototype new hardware designs by emulating their functional units on networks of transputers. This gives better information about performance and appearance than simulation and can be considerably easier to build. It also permits software to be built and executed with performance that approximates the final system-hence, software prototyping is also possible. We describe our experiences with two different systems: an object-based vision system and an implementation of the functional language Lucid." } @InProceedings{StephensoBoudillet88, title = "{GECKO}: {A} graphical tool for the modelling and manipulation of occam software and transputer hardware topologies", author= "Stephenson, Marc and Boudillet, Olivier", editor= "Askew, Charlie", pages = "139--144", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "This paper outlines some of the work undertaken at the Polytechnic of Central London (PCL), within the framework of the Alvey supported Parsifal project. The aim of this work is to help the user with the problems of: conceptualising, designing, fine tunning and configuring occam applications." } @InProceedings{TurnerBeton88, title = "{A} state-of-the-art radar pulse deiterleaver", author= "Turner, S. P. and Beton, Rick D. and Upstill, C.", editor= "Askew, Charlie", pages = "145--152", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "This paper discusses the conversion and development of a serial implementation of a state-of-the-art radar deinterleaving algorithm into a full-scale parallel implementation using occam2 and the transputer." } @InProceedings{DewHolliman88, title = "{T}echniques for rendering solid objects on a processor farm", author= "Dew, Peter M. and Holliman, Nick and Morris, David and Pennington, Alan de", editor= "Askew, Charlie", pages = "153--168", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "Collaborative research by Leeds University and the IBM UK Scientific Centre has resulted in an experimental parallel solid modeller called MISTRAL, based on the Constructive Solid Geometry (CSG) representation of solid objects. This paper gives an overview of the CSG rendering algorithms implemented in MISTRAL, a description of the MISTRAL modeller itself, and describes how several different kinds of parallelism may be exploited using a processor farm. It concludes by discussing some of the issues involved in writing complex parallel programs in OCCAM2." } @InProceedings{CarmichaeHewson88, title = "{A} prototype simulator output movie system based on parallel processing technology", author= "Carmichael, N. and Hewson, D. and Vorst, J. van der", editor= "Askew, Charlie", pages = "169--175", booktitle= "{OUG}-9: {O}ccam and the {T}ransputer -- {R}esearch and {A}pplications", isbn= "90 5199 010 3", year= "1988", month= "sep", abstract= "New parallel processing technologies potentially offer immense computing power at a very reasonable price. However it is not yet clear how best this potential may be realised for the large class of applications of concern to the Shell computing community. Shell U.K. (Expro) Ltd., as one of that company's ninth licensing round initiatives, decided to purchase a parallel processing machine (a member of the \"computing surface\" range from Meiko Ltd.,a Bristol ,U.K., based company). In order to test the abilities of the machine and its suppliers, dynamic \"movie style\" display of oil or gas reservoir simulator output (ie. changing fluid distributions within the reservoir) was chosen as an application example. The presentation will give a brief description of the application and of how it is placed on the machine. These devices are now being routinely used by reservoir engineers.Operational usage of the system will be discussed (a video of an interactive session will be available) and some more general remarks about the placement of such technology within an extensive heterogeneous computing environment will be made." } @InProceedings{Capon89, title = "{E}xperiments in algorithmic parallelism", author= "Capon, Peter C.", editor= "Bakkers, Andr\`{e} W. P.", pages = "1--14", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{EudesMenneteau89, title = "{PDS}: {A}dvanced program developement system for transputer based machines", author= "Eudes, J. and Menneteau, F. and Mugwaneza, L. and Muntean, Traian", editor= "Bakkers, Andr\`{e} W. P.", pages = "15--28", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{KerridgeWright89, title = "abstracts data types and occam", author= "Kerridge, Jon and Wright, Sue and Oates, Richard J.", editor= "Bakkers, Andr\`{e} W. P.", pages = "29--45", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{CrollManson89, title = "{C}onfiguration tools for a transputer workstation", author= "Croll, Peter R. and Manson, Gordon A.", editor= "Bakkers, Andr\`{e} W. P.", pages = "46--58", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{CaiTurner89, title = "{H}ighly transparent monitoring of parallel systems using \"logical clocks\"", author= "Cai, Wentong and Turner, Stephen J.", editor= "Bakkers, Andr\`{e} W. P.", pages = "59--70", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{LangenkamElgershui89, title = "{A} transputer based visual system", author= "Langenkamp, A. A. J. and Elgershuizen, P. M. and Huiskamp, W. and Lieshout, P. L. J. van", editor= "Bakkers, Andr\`{e} W. P.", pages = "71--81", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{HuiskampElgerhuiz89, title = "{V}isualization of 3{D} emperical data: {T}he {VOXEL} processor", author= "Huiskamp, W. and Elgerhuizen, P. M. and Langenkamp, A. A. J. and Lieshout, P. L. J. van", editor= "Bakkers, Andr\`{e} W. P.", pages = "82--94", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{BrownRygol89, title = "{M}arvin -- {M}ultiprocessor {A}rchitecture for vision", author= "Brown, Chris R. and Rygol, Michael", editor= "Bakkers, Andr\`{e} W. P.", pages = "95--107", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{AdmiraalCarmichae89, title = "{M}emory managers for transputing networks", author= "Admiraal, J. C. and Carmichael, N.", editor= "Bakkers, Andr\`{e} W. P.", pages = "108--113", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{BriatFavre89, title = "{PARX}: {A} parallel operating system for transputer based machines", author= "Briat, J. and Favre, M. and Fort, D. and Gonzalez-Valenzuela, N. and Langue, Y. and Muntean, Traian and Waille, Ph.", editor= "Bakkers, Andr\`{e} W. P.", pages = "114--142", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{RoebbersVlot89, title = "{A} communication processor on the transputer", author= "Roebbers, Herman and Vlot, Marnix", editor= "Bakkers, Andr\`{e} W. P.", pages = "143--151", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{Peel89, title = "{I}ssues raised while implementing a layered protocol using occam and the transputer", author= "Peel, Roger M. A.", editor= "Bakkers, Andr\`{e} W. P.", pages = "152--164", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{Heaps89, title = "{A}n occam-2 implementation of higher-level network protocols: {A} case study in interfacing a multi-user multi-transputer system to a local area network", author= "Heaps, Mark", editor= "Bakkers, Andr\`{e} W. P.", pages = "165--177", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{BaudeCarre89, title = "{T}opologies for large transputer networks: {T}heoretical aspects and experimental approach", author= "Baude, Francoise and Carre, Francoise and Clere, Pascal and Naquet, Guy Vidal-", editor= "Bakkers, Andr\`{e} W. P.", pages = "178--197", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{Welch89a, title = "{TRANSNET} -- {A} transputer-based communications service", author= "Welch, Peter H.", editor= "Bakkers, Andr\`{e} W. P.", pages = "198--212", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{DjahanguiGeffroy89, title = "{U}se of occam for the validation of distributed discrete event driven simulation", author= "Djahanguir, A. H. and Geffroy, J. C.", editor= "Bakkers, Andr\`{e} W. P.", pages = "213--221", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{Nevison89, title = "{D}iscrete event simulation using occam", author= "Nevison, Christopher H.", editor= "Bakkers, Andr\`{e} W. P.", pages = "222--230", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{Cosnuau89, title = "{A} structural dynamics problem on a network of transputers", author= "Cosnuau, A.", editor= "Bakkers, Andr\`{e} W. P.", pages = "231--255", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{Renterghe89, title = "{A}pplicability of a 16-node transputer array without external memory", author= "Renterghem, Patrick van", editor= "Bakkers, Andr\`{e} W. P.", pages = "256--263", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{BalboniGiandonat89, title = "{PIPES}: {A} transputer-based parallel architecture for {AI} real time applications", author= "Balboni, G. P. and Giandonato, G. and Melen, R.", editor= "Bakkers, Andr\`{e} W. P.", pages = "264--279", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{ReehorstWijbrans89, title = "{BIONIVISION} {A} laserscanner with transputers", author= "Reehorst, G. ter and Wijbrans, K. C. J.", editor= "Bakkers, Andr\`{e} W. P.", pages = "280--288", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{VermeulenBoterenbr89, title = "{A} novel architecture for data-aquisition and on-line analysis in high-energy physiscs experimentation", author= "Vermeulen, J. C. and Boterenbrood, H. and Goble, S. C. and Jong, S. J. de and Kieft, G. N. M. and Uijterwall, H. A. J. R. and Wiggers, L. W. and Waard, A. J. de", editor= "Bakkers, Andr\`{e} W. P.", pages = "289--295", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{StringerWaring89, title = "{T}ransputer based database organisation -- an example protien database implemented using pipeline and hypercube configurations", author= "Stringer, K. S. and Waring, L. C.", editor= "Bakkers, Andr\`{e} W. P.", pages = "296--300", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{BuitenwerDam89, title = "{A}n operational pattern recognition system on transputers", author= "Buitenwerf, E. and Dam, J. R. van and Nieuwenhuis, L. J. M.", editor= "Bakkers, Andr\`{e} W. P.", pages = "301--309", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{Welch89b, title = "{G}raceful termination -- graceful resetting", author= "Welch, Peter H.", editor= "Bakkers, Andr\`{e} W. P.", pages = "310--317", booktitle= "{OUG}-10: {A}pplying {T}ransputer {B}ased {P}arallel {M}achines", year= "1989", } @InProceedings{VerhulstLauwerein89, title = "{TROS}: {A} {R}eal {T}ime {K}ernel for a {F}ault-{T}olerant {M}ulti-{P}rocessor {C}omputer {B}ased on {A}rgument {F}low", author= "Verhulst, Eric and Lauwereins, R. and Cuyvers, R. and Peperstraete, J.", editor= "Wexler, J.", pages = "1--13", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "The design and realisation of a fault tolerant load balancing real time kernel for a multi-transputer system is considered. The system will be able to recover from software as well as from hardware failures. This is made possible by applying the argument flow program organisation. Argument flow programs are a mixture of normal control flow at the lowest level and of data flow at the higher levels. Hence, load balancing can be executed automatically.In the next part, the architecture of the runtime kernel and the use of argument flow is considered." } @InProceedings{MillotVautherin89, title = "{D}ynamicity through {O}ccam and {TDS}", author= "Millot, D. and Vautherin, J.", editor= "Wexler, J.", pages = "14--22", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "A parallel program running on a parallel machine involves a logical network of processes and a physical network of processors. When both networks are known at design time, a static mapping of the logical network on the physical one can take place. Dynamicity arises when one of the networks is not entirely determined before execution starts. This can happen for instance when the logical network involves dynamic creation of processes, or when the physical topology cannot be defined at design time (this is the case in a multi-user context, as the configuration a user gets is affected by the other users' computations, or when the programmer wants to develop a generic program that can be executed on any physical topology).When using Occam to design a network of processes that has to be mapped on transputers, things have to be decided before execution starts :- the network of processes should be composed of an explicitly bounded number of processes due to the fact that, unlike CSP, Occam does not allow recursion,- the topology of the transputer network should be known, for processes are explicitly mapped onto processors. One has to investigate the physical topology in order to write the configuration statements, and a change in the topology entails modifications in these statements. An application is therefore dedicated to a configuration. It would nevertheless be very attractive to design software that could run on an unidentified topology, trying to make the best of available processors. Such software has to realize a dynamic placement and therefore includes a phase supposed to investigate the configuration, load the different codes on the appropriate processors, then dynamically start their execution.Our aim is to develop suitable tools to write that kind of application. As a first step, we investigate the potentiality of Occam and TDS in this field." } @InProceedings{CroweHasson89, title = "{A} {CASE} {T}ool for {D}esigning {D}eadlock-{F}ree {OCCAM} {P}rograms", author= "Crowe, W. D. and Hasson, R. and Strain-Clark, P. E. D.", editor= "Wexler, J.", pages = "23--35", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "This paper describes a Computer Aided Software Engineering (CASE) tool aimed at producing correct OCCAM programs. We use variants of CSP and OCCAM2 notation , a strong form of protocols on channels and standard forms for processes in order to lessen the combinatorial problems which arise while investigating deadlock. The CASE tool is graphical in nature and two versions of it are currently being implemented. One version is written in PROLOG and runs on Mackintosh computers while the another is written in a mixture of PROLOG and C and runs on Sun workstations." } @InProceedings{JoosenVerbaeten89, title = "{A} {D}eadlock {D}etection {T}ool for {O}ccam", author= "Joosen, Wouter and Verbaeten, Pierre", editor= "Wexler, J.", pages = "36--54", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "A problem that occurs frequently during the development of parallel programs is deadlock.In the domain of transputer technology (and of parallel computing in general) run time debugging software still is a problem. This increases the value of verification tools based on static analysis, even if the functionality is sometimes limited.In this paper we present our approach to static analysis. The analyzer reduces an occam program to the relevant actions hi the context of this problem (communication, possibly through guards: PAR constructions...), and subsequently examines the program, reporting possible problems that could occur during real execution. The tool goes beyond the purpose of detecting deadlocks only: other infinite wait situations are also reported." } @InProceedings{DavyDew89, title = "{T}owards a {S}oftware {A}rchitecture for {S}olid {M}odelling {S}ystems on {P}rocessor {N}etworks", author= "Davy, J. R. and Dew, Peter M. and Holliman, Nick and Mallon, D.P. and Pennington, Alan de", editor= "Wexler, J.", pages = "55--68", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "Our experience programming transputer-based systems for the visualisation of solid models has highlighted the need to separate the issues of program decomposition, task and data scheduling and low level communication. In this paper we propose a three level software architecture for multicomputer to support geometrical computations. The architecture takes into account current and emerging hardware to support communications and scheduling." } @InProceedings{XuTurner89, title = "{A}n {I}rregular {D}istributed {S}imulation {P}roblem with a {D}ynamic {L}ogical {P}rocess {S}tructure", author= "Xu, Ming Q. and Turner, Stephen J. and Pin, Nie", editor= "Wexler, J.", pages = "69--79", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "This paper describes a modeling problem which exhibits many features of more advanced distributed simulation: the simulation of biological population dynamics — \"Host-parasite interactions\". It is a dynamical simulation in which certain species of hosts and parasites live, move randomly, breed and (as far as parasites are concerned) infect the hosts in a two-dimensional ocean. Apart from its relevance to realistic biological studies, this simulation program does serve to illustrate many crucial ideas in dynamic time and event driven simulations. Our approach to the parallel implementation of this simulation requires the simulation objects (in this case, hosts and parasites) to be organised as LPs (Logical Processes) which can be created and destroyed dynamically at run time to reflect the birth/death of these simulation objects. In addition to their dynamical features, LPs must preserve the temporal aspects of the real world system. In other words, a global ordering of LP interactions (referred to here as actions) must be ensured to preserve the causality principle [1]. Also, the computational load can become imbalanced because the real world system or rather, the distribution of hosts and parasites in the underlying space is changing with time. The methods for counteracting this dynamical load imbalance will be described.We shall begin with the specification of the dynamical rules governing the behaviour of the hosts and parasites during the simulation." } @InProceedings{ElGiarHopkins89, title = "{A} {G}enerally {C}onfigurable {M}ultigrid {I}mplementation for {T}ransputer {N}etworks", author= "El-Giar, Osama and Hopkins, Tim", editor= "Wexler, J.", pages = "80--88", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "This paper describes the performance of a multigrid method implemented on a transputer-based architecture. We show that the combination of fast floating-point hardware, local memory and fast communication links between processors provide an excellent environment for the parallel implementation of multigrid algorithms. The gain in efficiency obtained by increasing the number of processors is shown to be nearly linear and comparisons are made with published figures for a parallel multigrid Poisson solver on an Intel iPSC 32-node hypercube." } @InProceedings{Shen89, title = "{S}elf-{A}djusting {M}apping: {A} {H}euristic {M}apping {A}lgorithm for {M}apping {P}arallel {P}rograms onto {T}ransputer {N}etworks", author= "Shen, Hong", editor= "Wexler, J.", pages = "89--98", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "The problem of mapping parallel programs onto multiprocessor system is a fundmental problem of great significance in parallel processing, but it is NP-hard in general. In this paper we propose a fast heuristic algorithm to solve this problem on transputer networks. Our mapping algorithm consists of three modules: grouping, placement and routing, where grouping groups processes in the program into tasks which can be placed onto processors in the transputer network in a way of one-to-one, placement places the grouped tasks onto the processors and routing produces physical communication paths for logical communication requirements. The three modules work co-operatively in a way of progressive self-adjusting, and finally produce a satisfactory solution for the mapping problem." } @InProceedings{CandlinLuo89, title = "{T}he {I}nvestigation of {C}ommunications {P}atterns in {O}ccam {P}rograms", author= "Candlin, Rosemary and Luo, Qiangyi and Skilling, Neil", editor= "Wexler, J.", pages = "99--108", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "The performance of a concurrent computation running on a multiprocessor system may depend critically on the way in which the program is decomposed and placed on the machine. In order to exploit the potential of parallel processors, it is necessary to balance the advantage of spreading the computational load as thinly as possible over the processors, with the disadvantage that increased communication delays may slow down the computation. In general, there is no satisfactory theoretical model of the complex interaction between the amount of computation carried out by the individual processes, their frequency of communication and the topology of the underlying machine. For many programs, it is not easy to see in advance how computation will interact with communication, and placement strategies which depend only on a static analysis of the program structure may not be sufficient. The work described here is an attempt to provide useful tools for the occam programmer which can be used to investigate communications patterns, and to explore different configurations rapidly.We think that this approach will be particularly valuable for programs which can be decomposed in a natural way into a fairly large number of top-level occam processes, so that the preliminary parallelization arises out of the nature of the application, and the main problem is to place these processes on a smaller number of physical processors. This is often the case for programs which model real-time systems, and we have taken as an example an application from chemical engineering. In programs like this, there is natural concurrency in the real world which can be easily represented in terms of occam processes. At the moment, we do not attempt to extract parallelism automatically, or handle shared data, though there are a number of systems that have tackled these problems (see, for example [1] and [2]). Our main aim at this stage is to provide a programmer with profiling tools, and see to what extent they can help to produce an efficient implementation of the program." } @InProceedings{ChalmersPaddon89, title = "{A} {S}ystem {C}onfiguration for very large {D}atabase {P}roblems [{E}xtended {A}bstract]", author= "Chalmers, Alan G. and Paddon, Derek J.", editor= "Wexler, J.", pages = "109--112", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "In the past many applications have ensured success by restricting the size of the application, or by increasing the number of processors and memory size to enable the full database to be supported. Here, we specify that databases of arbitrary sizes should be supported and not be restricted by the memory size of individual processors.The ability to cope with very large databases was easily achieved in many of the early MIMD systems by using a shared memory model. However, the transputer and Occam process model restricts us from using this approach, instead we may share data [7].Unlike shared memory systems, we cannot globally address data in a message passing system. However, if data items carry unique identifiers, we can share single or multiple copies of those data items across many processors. Indeed, adopting this system of shared data reference allows us the same memory flexibility for read-only data, as would be obtained in a shared memory system, without the bus contention problems associated with that class of processor. In its degenerate form, a shared data system has only private data, which is never available at any other processor. The simple processor farm of May and Shepherd [8] is a typical example, where data and tasks are assigned to specific processors without the need for data to migrate to other processors. In many applications, such as the ray tracing of very complex computer images, a static allocation of data is inappropriate. Here, a database is managed at each node in a similare manner to a cache memory. Shared data systems for a tree based system architecture, and for very large data base problems are described by Green, Paddon and Lewis [7], and Green and Paddon [3, 4, 5, 6], where these systems were applied to image synthesis using the ray tracing method." } @InProceedings{JongStiles89, title = "{A} {C}omparison of {P}arallel {I}mplementations of {F}lux {C}orrected {T}ransport {C}odes", author= "Jong, Jing-ming and Stiles, G. S.", editor= "Wexler, J.", pages = "113--128", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "We present the results of comparing implementations of the Flux Corrected Transport (FCT) method on transputers and several other parallel and sequential machines. FCT is a finite difference scheme used to solve fluid dynamics problem which may involve steep gradients or shocks; it has proven useful for both one- and two-dimensional problems in plasma physics, atmospheric sciences, and detonation studies. The method vectorizes very well and hence runs quickly on supercomputers. Since the calculations at each point involve only a small number of neighbors, the method can also be efficiently implemented on multi-processor systems. We have run one- and two-dimensional problems on Transputers and several other systems, including a VAX 8650, a SUN 4/280, a four-processor Ardent Titan, an eight-processor Alliant FX/8, and a four-processor Silicon Graphics 240GTX. We shall also compare our results to those obtained by Gustafson (1988) on the NCube/ten.If, in the 1-d problem, we consider the speed of a single T800 to be 1.0, the SUN 4/280 ranks at 3.8, the VAX 8650 at 4.0, 8 TSOOs at 7.9, the Silicon Graphics 240GTX at 27.0, the FX/8 at 56.9, and the Titan at 64.4. On the 1-d problem, again taking one T800 to have a speed of 1.0, the SUN comes in at 3.6, 16 NCube nodes at 4.0, the 8650 at 4.3, 8 TSOOs at 7.7, the Titan at 65.3, and the FX/8 at 101.4. The transputer ranks highest if we calculate the cost-effectiveness of the various systems by dividing the relative speed by the approximate cost. If we assume the 8 TSOOs have a cost-effectiveness of 1.0 on the 1-d problem, the Titan is second at 0.52, followed by the 240GTX at 0.17, the FX/8 at 0.094, the SUN at 0.081, and the VAX at 0.021." } @InProceedings{VanhalaKaski89, title = "{S}imulating {N}eural {N}etworks in a {D}istributed environments", author= "Vanhala, Jukka and Kaski, Kimmo", editor= "Wexler, J.", pages = "129--141", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "Two artificial neural network models are compared. They are the Hopfleld neural network model and the Sparse Distributed Memory model. Distributed algorithms for both of them are designed and implemented. The run time characteristics of the algorithms are analyzed theoretically and tested in practise. The storage capacities of the networks are compared. Implementations are done using a distributed multiprocessor system." } @InProceedings{KuiperDijkstra89, title = "{A}ttribute {E}valuation on a {N}etwork of {T}ransputers", author= "Kuiper, Matthijs F. and Dijkstra, Atze", editor= "Wexler, J.", pages = "142--149", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "The structure and construction of parallel compilers that run on a network of transputers is discussed. The compilers are automatically generated from an attribute grammar definition of the source language. This work illustrates that parallelism can also be used in non-numeric computations. As part of implementing parallel compilers we have constructed a general message passing kernel for transputers. This kernel can also be used in other applications. First results indicate that parallel compiling on transputers is feasible and that 4 to 16 transputers can be used in parallel compilers." } @InProceedings{Chalmers89, title = "{A}n {O}bject {O}riented {S}tyle for the {C}omputing {S}urface", author= "Chalmers, Matthew", editor= "Wexler, J.", pages = "150--158", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "During the development of a ray tracer on a Meiko Computing Surface, problems with poor flexibility of configuration and slow software development were encountered. In order to overcome these difficulties, and in order to facilitate experimental programming on the Meiko, a system to support an object-oriented style for Occam' programming was developed. The aim was to create a set of library modules that would allow user code to be quickly developed and integrated into existing programs, to support better debugging facilities than were currently available, and to allow program design to be based on a more flexible and dynamic model of concurrency than the process modelThis system has been rewritten in order to introduce new features and to take advantage of the availability of C. The new system is described, with the emphasis on how experience with the system influenced its redesign, and on the details of newer elements such as the improved facilities for monitoring and debugging." } @InProceedings{Adamo89, title = "{C}\_{NET} {A} {C}++ {B}ased {L}anguage {F}or {D}istributed {A}nd {R}eal {T}ime {P}rogramming", author= "Adamo, Jean\_Marc", editor= "Wexler, J.", pages = "159--170", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "C\_NET is a high level C++ based language devoted to multiprocessor architecture programming. It has been designed so as to offer concepts of object-oriented programming, communicating processes and exception handling, all within the same language. The purpose of this paper is to describe how merging these concepts into C\_NET has been organized. Consequently, the paper is divided into three parts. The first is concerned with discussing the different roles that the notions of class object and process are intended to play within the language. It is argued that these roles are in fact orthogonal, since the first two notions are primarily concerned with data structuring, encapsulation and inheritance, whereas the last one is mainly concerned with threads of control and synchronization. The second part is devoted to describing the exception handling system, which makes it possible to derive process preemption mecanisms by combining exceptions with parallelism. Process preemption raises some atomicity problems, which are discussed at the end of the second part. Finally the last part provides information on the state of the project development and on future perspectives." } @InProceedings{SmithWelch89, title = "{R}eal-{T}ime {T}ransputer {M}odels of a {L}ow-{L}evel {P}rimate {V}ision", author= "Smith, Andrew B. and Welch, Peter H.", editor= "Wexler, J.", pages = "171--181", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "It is believed from psychophysical experiments that human vision operates in two stages: a parallel preattentive stage which extracts simple visual features and a sequential attentive stage in which local features of the scene are analysed. A processing model of the early preattentive stage has been developed. This model is computationly intensive making it unsuitable for implementation on sequential computer architectures. The development of a real-time parallel transputer vision system based on this processing model is explained.The current implementation performs edge filtering over four separate resolution/field-of-view levels from 256 by 256 monochrome images. Eight T800-20 transputers deliver over 40 frames per second. The software — hardware architecture is scalable so as to support higher resolutions and additional features (such as auto-focusing, movement detection, and tracking) through the addition of extra transputers, whilst maintaining at least camera frame rates." } @InProceedings{Wong F.S.Seng89, title = "{ICR}: {A} {T}ransputer-{B}ased {I}ntelligent {C}haracter {R}eader", author= "Wong F.S., Francis and Seng, Koh Liang", editor= "Wexler, J.", pages = "182--189", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "This paper presents the design of a transputer-based Intelligent Character Reader (ICR). The implementation of the ICR is based on two algorithms. The Filtered Projection Technique (FPT) is a modification of the conventional projection profile techniques - it filters out and projects the structural information of a visual pattern into several components along several directions, such that some salient structural information can be extracted from these components easily. The Structural Complexity Index (SCI) algorithm determines the structural complexity of a visual pattern and produces the corresponding index to indicate its relative complexity. The ICR is capable of recognizing printed characters, such as the Chinese characters printedon the local newspapers, accurately, despite the presence of noise due to printing, scanning, slight font variations and misalignment. The ICR prototype is implemented on Occam II and C, and run on an array of transputers." } @InProceedings{CosnuauDesbois89, title = "{S}olving {P}artial {D}ifferential equations via {C}ellular {A}utomata: {A} {B}inary and {S}tatistical {A}pproach", author= "Cosnuau, A. and Desbois, F. and Morchoisne, Y.", editor= "Wexler, J.", pages = "190--195", booktitle= "{OUG}-11: {D}eveloping {T}ransputer {A}pplications", isbn= "90 5199 020 0", year= "1989", month= "sep", abstract= "Cellular automata are used to solve partial differential equations (PDE) discretized on a non-regular grid. Boolean representations of real numbers are introduced and logical intrinsic computer functions are used to achieve algebraic operations of the finite difference algorithm. In a first step the method is briefly explained and then implementation is described. For diffusion or convection problems, preliminary computations on a Cray-XMP18 and on a network of T800 Transputers were done." } @InProceedings{Cole90, title = "\"{D}o it yourself\" shared memory instruction sets in occam", author= "Cole, M. I.", editor= "Turner, Stephen J.", pages = "1--10", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "We present an approach to the task of \"civilising\" distributed memory architectures, in which the programmer is presented with a shared memory computational model, augmented with application specific shared memory instructions. We note that this model can ease the dimculty of designing and justifying algorithms, and that occam provides a suitable medium for its distributed implementation." } @InProceedings{GallizziCannataro90, title = "{A} deadlock-free communication system for a transputer network", author= "Gallizzi, E. and Cannataro, M. and Spezzano, G. and Talia, Domenico", editor= "Turner, Stephen J.", pages = "11--21", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "The design and an implementation overview of a communication system which provides deadlock-free operation in a tightly coupled message-passing multicomputer system is presented. Furthermore, routing simulation results for a 4x 10 computer array are described. The communication system has many positive characteristics including provable deadlock-freedom, guaranteed message arrival, and automatic local congestion reduction. This system has been implemented in Occam 2 on a network of Transputers." } @InProceedings{Lee90, title = "{A} parallel semantic net engine and its application to data modeling", author= "Lee, Y. N.", editor= "Turner, Stephen J.", pages = "22--33", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "Although the use of Fourth Generation Languages has greatly increased the efficiency of the system development process, the validation of system specifications is still considered to be complicated and time-consuming. A \"Parallel Semantic Net Engine (PSNE)\" has been developed as part of a research project carried out in the Department of Computer Science at Exeter University to investigate into this area. This project was initiated by a software house, Softwright Systems Ltd., which has made extensive use of Fourth Generation Languages.The purpose of this project was to construct an engine which would be fast enough to validate a system specification in realtime, giving immediate feedback to the user when constraints are violated. The areas of knowledge representation and parallel processing were explored. A Parallel Semantic Net Engine was proposed in order to take advantage of the richness of semantic networks in representing complicated relationships and the power of transputers in speeding up the processing. Figure 1 shows the general model of the PSNE.The model is distributed over of a host PC and a network of transputers. On the PC side, there are the application generator, generated applications and a standard relational database which stores the application data. A front-end would be developed running on the PC to act as the gateway for data passing between the PC and the transputers." } @InProceedings{GrayPoole90, title = "{P}arallel-{DB}4{GL}: {A}n implementation of a self-describing object-oriented database application generator on transputer hardware", author= "Gray, J. P. and Poole, F.", editor= "Turner, Stephen J.", pages = "34--49", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "In general, this research project is concerned with the use of transputer based parallel hardware to improve the performance of database software. Specifically, the aim of the project is the enhancement of a database application generation system, Data Base 4th Generation Language (DB4GL), by converting the DB4GL generated database applications to run on transputer networks.A prototype Parallel-DB4GL (P-DB4GL) system has been designed and implemented. In P-DB4GL, the application code modules generated by DB4GL have been redesigned as concurrent Occam [InmosSSb] processes. A number of DB4GL data access code modules (entity handlers and schema handlers) have been implemented, and used to construct simple database applications. Additionally, simulations of DB4GL modules not yet implemented (for example, User Processes and Filer Processes) have been written, and used in the testing of these simple database applications.The P-DB4GL applications have been test run on a number of different transputer configurations. Results have been obtained which show significant performance improvements when applications are run on small (one to four processors) transputer networks. The principal benefit comes from the ability to perform multiple concurrent disc input/ouput, thus increasing disc throughput, and hence improving overall application performance. Development and testing of the prototype P-DB4GL has confirmed the feasibility of using transputer based parallel hardware for DB4GL applications. It has indicated how and where significant performance gains can be obtained in the full working version of P-DB4GL, currently under development." } @InProceedings{CrambUpstill90, title = "{U}sing {T}ransputers to {S}imulate {O}ptoelectronic {C}omputers", author= "Cramb, I. and Upstill, C.", editor= "Turner, Stephen J.", pages = "50--59", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "In this paper we present the results of our simulation and study of an optoelectronic SIMD architecture on a medium sized transputer array (18 processors). The particular optoelectronic architecture we have simulated is a Binary Image Algebra (BIA) Processor of considerable computational power -processing data at rates well in excess of those currently achievable using electronic computers. Considering the inherent parallelism of such an architecture, along with the need for very large amounts of data processing in order to perform realistic simulation, the simulator was implemented in occam on a transputer array. The process model of computing adopted by occam is also most appropriate to the optoelectronic architecture which we have designed because of its modularity: we have been able to design process structures which have the same topology as the processing modules in our architecture. In the optoelectronic architecture, data are transmitted to a set of processing modules, one of which is chosen to perform a particular operation; the data pass through that module and are are transformed as they do so; in our simulator the processing takes place in a very similar way: data are transmitted from the controller to the farm; a particular process/module of code is called, and the data are passed through it, using occam channels, and are processed as they do so.We begin with a description of BIA itself. The core of the paper is a description of the logical architecture we have adopted; we include an account of a method for reducing the limiting effect of the transputer link bandwidth on the performance of farming computationally undemanding tasks. The paper is concluded with a brief description of our design for an optoelectronic SIMD architecture." } @InProceedings{MacfarlanEast90, title = "{A}n investigation of several parallel genetic algorithms", author= "Macfarlane, Donald and East, Ian R.", editor= "Turner, Stephen J.", pages = "60--67", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "Genetic algorithms (GAs) are important search and optimisation techniques with a wide range of applications. The demand for GAs with fast response times has led to the investigation of parallel implementations. Three parallel GAs are designed, implemented on a transputer network, and compared over several benchmark problems. It is believed that a fine-grained approach to parallel genetic algorithms is the most promising." } @InProceedings{KumarBasu90, title = "{A}n efficient global convergence detection scheme for parallel algorithms on transputer network", author= "Kumar, K. G. and Basu, A. and Srinivas, S. and Paulraj, A.", editor= "Turner, Stephen J.", pages = "68--79", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "The paper discusses a novel and efficient scheme for the detection of global convergence in parallel iterative algorithms. Convergence information is maintained as processes which execute concurrently with computations of the algorithm and exploit the asynchrony inherent in the progress of most executions of such algorithms towards global convergence. The scheme treats messages signalling convergence as having a lower priority as compared to those signalling non-convergence. It minimizes the waiting time at the end of iterations for convergence related communications. Analytical results indicate that the global convergence detection scheme proposed in this paper is faster than the methods proposed earlier [3]. The scheme is particularly suited for implementation on Transputer based parallel machines. An OCCAM implementation of the scheme on a torus of Transputers is described together with a method for experimental verification of the analytical results." } @InProceedings{Jacquemin90, title = "{I}mplementing {R}ecursion on a {D}ouble {R}ing {T}opology", author= "Jacquemin, J. L.", editor= "Turner, Stephen J.", pages = "80--84", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "The widespread recursion problems can become much more time-efficient if they are processed with the help of a parallel algorithm. The authors have shown that transputer networks are able to bring an outstanding efficiency in the case of a double ring topology. A special care is given to load balancing, performance enhancement techniques and optimization of interprocessor communication.The method presented here can be implemented on any number of processors by merely changing a single parameter: The number of processors involved." } @InProceedings{CunhaMedeiros90, title = "{A} {D}istributed {L}ogic {P}rogramming {L}anguage and its {I}mplementation on {T}ransputer {N}etworks", author= "Cunha, Jos\`{e} A. Cardoso and Medeiros, Pedro A. Duarte and Pereira, Luis M.", editor= "Turner, Stephen J.", pages = "85--96", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "Currently there is a trend towards the development of programming tools and mechanisms for the support of heterogeneous multi-agent systems on paralell computer architectures. This paper presents a contribution to this area, as far as logic programming on a distributed execution environment is concerned. We discuss the main issues on the design and implementation of the logic programming language Delta Prolog [2] [3] [6] [7] [11], extending Prolog with constructs for concurrency and communication. The work described is one of the research components of a project on the development of mechanisms for parallel logic programming support on parallel architectures, currently running in this University [8]." } @InProceedings{SchulzeKr90, title = "{CS}-{P}rolog -- {P}arallel programming in logic with transputers", author= "Schulze-Kremer, Steffen", editor= "Turner, Stephen J.", pages = "97--110", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "This paper describes the parallel features of CS-Prolog, an extension of standard Prolog languages. CS-Prolog employs the local virtual time concept and allows parallel evaluation of several Prolog goals making use of a variable number of transputers on an IBM-AT compatible. Further, written in CS-Prolog a program MolSIM is presented, that can carry out knowledge-based simulation of molecularbiological regulatory processes." } @InProceedings{SarrafanWelch90, title = "{T}ransputer models for a high-performance local area network bridge", author= "Sarrafan, A. M. and Welch, Peter H.", editor= "Turner, Stephen J.", pages = "111--121", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "Bridges interconnecting Local Area Networks can experience heavy loads. Traditional implementations of such devices have typically achieved high throughput rates by implementing the device at low protocol levels, thus keeping the functionality of the device quite simple in nature. For bridges that are required to have a higher degree of intelligence and for gateways between different networking technologies (which must be implemented at higher protocol levels), the problem is to maintain high throughput rates in a processing intensive component This paper describes an expandable and parallel solution to the problem. The methodology is demonstrated in an occam implementation of a Cambridge Ring bridge. The prototype is tested on several different transputer configurations and the results are reported. To put the figures into context, performance figures for an equivalent sequential implementation, currently operational at the University of Kent, are also quoted." } @InProceedings{KaziHockman90, title = "{D}esign of a {H}igh {P}erformance {P}rotocol {A}nalysis system using transputers", author= "Kazi, Sarvajna and Hockman, Robert D.", editor= "Turner, Stephen J.", pages = "122--131", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "The Problem : Managing Enterprise Networks Consisting of LANs and WANs.PCs and workstations are the tools of choice for many-work-group applications. When attached to increasingly large and complex Local Area Networks (LANs), they can efficiently share their own resources and those in diverse distributed servers. Increasingly, enterprises with widely distributed locations are linking these diverse LAN work-groups via a variety of Wide Area Networks (WANs). The resulting heterogeneous networks form a geographically distributed LAN/WAN with a large number and diversity of computing and communication components. ...." } @InProceedings{Peel90, title = "{H}ost-independent access to transputers", author= "Peel, Roger M. A.", editor= "Turner, Stephen J.", pages = "132--137", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "Most Transputer development software is designed to run on Transputer hardware. The most common access mechanism to such facilities uses a Transputer card plugged directly into the expansion bus of a personal computer, workstation or minicomputer. The problem with this scheme is that the host machine must pass all communications to the Transputer, and thus must be involved even if the communication originated on another computer networked to this host. In addition, there is a physical limit to the number of Transputer cards which may be accommodated and individually controlled within each host.In order to support large populations of users economically, the author has developed a Transputer-based Ethernet peripheral which can communicate directly with networked host processors, and supports multiple target Transputers, each running an enhanced version of the standard INMOS Iserver. Each target Transputer is therefore capable of running the Transputer Development System and the standalone Toolkit compilers, as well as user's application programs. In addition, capabilities are provided for reserving clusters of client Transputers for the execution of multi-Transputer applications." } @InProceedings{CalTurner90, title = "{E}xperimental studies of conservative distributed discrete-event simulation on transputer networks", author= "Cal, W. and Turner, Stephen J.", editor= "Turner, Stephen J.", pages = "138--147", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "Computer-based discrete-event simulation has a relatively long history. Traditionally, it has been performed in a sequential manner: the event-list simulation mechanism ([1]) is a typical example. The idea of distributed simulation was proposed by Chandy in 1977 and is now being developed mainly along two directions - the conservative approach (deadlock avoidance ([2]) and deadlock recovery ([3])) and the optimistic approach (time warp ([4])).Distributed simulation explores the potential parallelism inherent in most simulation applications. Each physical process (PP) in the application is simulated by a logical process (LP) in the simulation model. Events in the physical system are simulated by message transmissions between IPs. Since many simulation applications contain a high degree of parallelism, simulation seems to be a natural candidate for parallel processing. But, the causality constraint of the simulation, that is, events simulated by an LP must have a nondecreasing simulation time, is not easily maintained by distributed processing. Many strategies have been proposed: however, experimental studies need to be conducted in order to discover how much speed-up is achieved with a distributed simulation as compared to sequential methods. Previous performance studies by other researchers ([5,6]) have mainly been carried out on shared-memory parallel processors. In this paper, a set of experimental results is presented, designed to evaluate the effectiveness of conservative distributed simulation strategies on message-passing parallel processors such as transputers." } @InProceedings{WoodhamsPrice90, title = "{A} {T}ransputer-based {W}orkstation {A}ccelerator for {O}ptimisation {A}lgorithms", author= "Woodhams, F. W. D. and Price, W. L.", editor= "Turner, Stephen J.", pages = "148--153", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "This paper discusses the design of a transputer-based accelerator for both combinatorial and global optimisation algorithms. Combinatorial optimisation has engineering applications in, for example, placement and routing of VLSI circuits. This type of problem is known to be in the complexity class NP-complete 1. For the solution of these problems some form of random search heuristic is often required. One such heuristic is the simulated annealing algorithm\^{}. This algorithm is usually too slow for the interactive user and is normally run on a mainframe computer." } @InProceedings{YuMuntean90, title = "{O}ccam program synthesis for execution on parallel machines: {T}owards a transformational approach", author= "Yu, Xiaobo and Muntean, Traian", editor= "Turner, Stephen J.", pages = "154--167", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "In this paper, we present a parallel program synthesis system which provides formal, methods and techniques for derivation and correct construction of implementations of occam programs on networks of transputers. The transformation rules are represented by a set of powerful algebraic laws of occam in order to perform the necessary transformation steps towards abstract forms representing models of execution of associated virtual machines.The program synthesis system can be applied to various aspects of parallel programming in a distributed environment, from the communication protocol design and correctness proof of implementation to parallel program construction, program optimisation, mapping strategies etc.Special emphasis is put on the transformation control strategies and guidance combined with information of the machine configuration, in order to achieve program optimisations, increasing parallelism granularity, altering inter-process communication patterns, for efficient execution on the physical parallelism offered by target transputer machines. An example of application of the transformation system to the distributed implementation of global synchronisations is given." } @InProceedings{HofstedeLensink90, title = "{A} {D}ynamic {S}witch for {T}ransputer {L}inks", author= "Hofstede, Jaap and Lensink, Andre", editor= "Turner, Stephen J.", pages = "168--178", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "One of the goals of the Esprit project Pangloss wa" } @InProceedings{TregidgoDownton90, title = "{P}rocessor {F}arm {A}nalysis and {S}imulation for {E}mbedded {P}arallel {P}rocessing {S}ystems", author= "Tregidgo, R. W. S. and Downton, A. C.", editor= "Turner, Stephen J.", pages = "179--189", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "A brief survey of current Parallel Processing literature reveals a large number of highly application specific architectures [1] [2] [3] [4]. The arrival of the Transputer [5] has done little to alleviate this situation, in fact the only constraint on custom architectures seems to be the number of communication links currently supported by the Transputer. The lack of generality in such architectures is expensive and often makes future system expansion difficult. The objective of this paper is to show that by accepting some compromise on performance, general purpose multiprocessor systems can be analytically designed." } @InProceedings{dAciernoPietro90, title = "{A} method for monitoring occam internal channels", author= "d'Acierno, A. and Pietro, Giuseppe de and Villano, Umberto", editor= "Turner, Stephen J.", pages = "190--197", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "In a Transputer environment, where the data exchange and the synchronizations between any two processes are carried out by means of I/O operations, the monitoring of the channels used for implementing the message exchange is of particular interest. In this paper a method is illustrated for monitoring the internal channels of an Occam program. This method introduces little CPU overhead, no additional communication cost, and preserves the synchronization behaviour of the two communicating processes. Its characteristics have been attained by means of a particular monitoring mechanism, based upon a rather unusual use of some Transputer machine language instructions, canonically used to implement guarded communications within the Occam ALT construct." } @InProceedings{EdwardsSillitoe90, title = "{T}he design of a real time three demensional vision system for object idenification", author= "Edwards, Janet and Sillitoe, Ian P. W.", editor= "Turner, Stephen J.", pages = "198--205", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "The paper describes the design and analysis of a transputer based application, written in Occara-2 and implemented on a network of transputers. The system generates volumetric representations of industrial objects in real time from a set of multiple views and forms a testbed for the investigation of various identification techniques to be used within an experimental industrial robotic workcell.The paper outlines the algorithm, its implementation and the efficacy of various design techniques used to increase the response of the system. It also makes recommendations for further work and useful tools to assist in writing efficient Occam code more effectively." } @InProceedings{StavenuitRoebbers90, title = "{C}ontrol of a servo loop for a vision system", author= "Stavenuiter, Tonny and Roebbers, Herman", editor= "Turner, Stephen J.", pages = "206--218", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "Transputers enable the implementation of complex control algorithms for robot systems at high sampling rates. With these new algorithms the need is felt for a better interaction between the robot and its environment Vision is an attractive sensor for the establishment of this interaction. This paper describes the development of a system, in which vision is used to track the tip of a robot link." } @InProceedings{AllenWang90, title = "{A}n application of ultrasonic signal processing in a mixed system of transputers and digital signal processors", author= "Allen, Alastair R. and Wang, Dalan", editor= "Turner, Stephen J.", pages = "219--222", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "A system is described in which a floating-point digital signal processor is incorporated into a transputer array. The resulting combination provides a significant resource which is being used to process ultrasonic echoes to determine surface roughness." } @InProceedings{DimondHassan90, title = "{I}ncremental behavioral simulations on a network of transputers", author= "Dimond, Keith and Hassan, Samir", editor= "Turner, Stephen J.", pages = "223--231", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "Simulation plays an important role in the design process for modern digital and analogue systems. There are many different types of simulators capable of representing the behaviour of the system at a number of different levels of abstraction. Because of its vital importance there is an ever increasing need to enhance the performance of simulators. Enhancements can occur in many different aspects. These may be in the speed of simulation, or in the accuracy of modelling. This paper describes a relatively new enhancement that of incremental operation which has the advantage of allowing the simulator to respond very rapidly to design changes in addition to providing an enhanced rate of simulation.The simulator which is described in this paper operates at the behavioural level. This allows the designer to specify, using suitable code segments descriptions of the behaviour of the functional blocks which make up the design. This approach may be used to model a digital system at the gate level, where signal values correspond to standard logic levels. In addition this mode of simulation has the attraction of being able to model very complex blocks which might very well have inputs and outputs which are most conveniently represented by complex data structures. This simulator is able therefore to model a complete system, some parts represented at this nigh-level of abstraction whilst other parts may be modelled at the lower levels of abstraction where greater detail is required." } @InProceedings{WestCapon90, title = "{A} high level software and environment for transputer based systems", author= "West, Adrian J. and Capon, Peter C.", editor= "Turner, Stephen J.", pages = "232--242", booktitle= "{OUG}-12: {T}ools and {T}echniques for {T}ransputer {A}pplications", isbn= "90 5199 029 4", year= "1990", month= "mar", abstract= "At Manchester we have a rack of Transputers that we use for research into parallel architectures[CGK86,AEK89]. These architectures are investigated by simulation, and some experience of this has already been gained. Currently, simulations are written in occam and drive the rack directly; a coding process that is rather slow, error prone and requires particular knowledge of the Manchester rack.We intend to provide a higher level environment that allows a more rapid and secure development to be achieved. As occam has been found to be a natural and flexible medium for expressing functional simulations, it has been retained in preference to a dedicated simulation language. The tools discussed in this paper are therefore applicable to occam programming generally, and will be used for the development of applications other than simulation." } @InProceedings{TayhBor90, title = "{RT}-{DOS} -- {A} real-time distributed operating system for transputers", author= "Tayh, M. and Bor, M. and Benmaiza, M. and Eskicioglu, M. R.", editor= "Zedan, Hussein S. M.", pages = "1--11", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "This paper describes the design philosophy of a real-time operating system, RT-DOS, and its architecture. RT-DOS is a generic name given to a prototype operating system, which is a fully-distributed, message-based system designed to run on a network of transputers. The main objective of RT-DOS is to provide a dynamically reconfigurable work platform that adapts to dynamic changes in workloads, allows system maintainability and dynamic upgrading, and increases system reliability and availability." } @InProceedings{JonesCha90, title = "{O}n the {F}easibility of {R}un-{T}ime {P}rocess {M}igration in {M}ulti-transputer {M}achines", author= "Jones, Peter and Cha, Hojung", editor= "Zedan, Hussein S. M.", pages = "12--27", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "A number of techniques for the amelioration of message transport costs in networked multiprocessor machines have been explored. Among these are established approaches such as (i) software implementation of message through routing systems, (ii) run-time installation of point-to-point physical connections between otherwise remote processors and (iii) pre-load manipulation of the machine topology to bring communicating processors close together. A further technique is proposed. This technique requires the run-time transport of processes, between processors, in order to reduce the distance over which communication must take place. This paper investigates the feasibility of such an approach for multi-transputer machines and indicates ways in which it can be implemented in practice." } @InProceedings{Gresser90, title = "{B}roadcast communication in fault tolerant multicomputer systems", author= "Gresser, K.", editor= "Zedan, Hussein S. M.", pages = "28--34", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "Fault tolerance can be achieved by means of redundancy. Multicomputer architectures allow duplicated tasks to run on multiple processors. In this paper we focus on multicomputer systems consisting of a small number of processors (4 to 16). Fault tolerance instrumented in the operating system level tolerates hardware faults. This type of fault tolerance is known as software implemented fault tolerance. The information exchange of the computers requires a powerful communication system with fault tolerance properties. Since no standard system meets all requirements a new design was necessary. This paper describes concept, hardware, firmware and performance of the transputer based broadcast communication system (BCS)." } @InProceedings{BeersLeibenspe90, title = "{T}ransputer performance issues using the trollius operating system", author= "Beers, James R. Jr. and Leibensperger, Ros and Braner, Moshe and Fielding, David", editor= "Zedan, Hussein S. M.", pages = "35--50", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "The Trollius Opeiating System for distributed multicomputer offers different types of message-passing services, incorporating different amounts of overhead. Each of the operating system activities required for interprocess communication is designed as an individual module or layer. The different types of Trollius communication can be accessed by turning operating system services on or off, or by directly utilizing different layers of communication.Basically, there are three layers of internode communication. The network layer can be used from any node to any other node; the data link layer is for nearest-neighbor communication; and Ihe physical layer uses the hardware in the most efficient way possible, but requires exclusive use of the link. A separate level, the kernel level, is used for intranode communication. Operating system services that can be turned on or off include buffering and virtual circuits.Two different types of benchmarks are used to evaluate the performance of the different types of Trollius message-passing. The first type calculates message-passing lime as the sum of the limes required for each individual service or component of Ihe process. The decrease in message-passing lime obtained when turning off services can ihus be easily measured. The second benchmark measures throughput, the amount of information that can be sent from one node to another in a given amount of time, for different layers of message-passing, utilizing different sendees. This is the more accurate measure when series of messages are sent from one node to another. The throughput measurements demonstrate the value of the physical layer and of virtual circuits." } @InProceedings{HarleyLevy90, title = "{H}igh performance event and {I}/{O} handling on the transputer", author= "Harley, R. G. and Levy, D. C. and Hemme, A. W. M. and Webster, M. R.", editor= "Zedan, Hussein S. M.", pages = "51--60", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "If transputers are to be used in high performance control applications it is essential that the I/O and event handling capabilities of the transputer are well understood. This requires insight into the hardware architecture and the low level language (guy code) of the transputer. The interface between the transputer executing the corresponding control process, and the external event generating devices can be divided into two main processes, namely interrupt or event handling and the I/O or data handling. For maximum performance these processes must be handled as quickly and efficiently as possible. Some of the issues involved in using occam to establish an interrupt handler are discussed in [1]. This paper extends that work to show how better performance and multiple event handling can be obtained efficiently. Several methods of achieving this real world interface are examined and, based on an actual design, the paper concludes with some recommendations to make the event handler more efficient." } @InProceedings{AvramovKnowles90, title = "{E}valuation of two systems for distributed message passing in transputer networks", author= "Avramov, N. N. and Knowles, A. E.", editor= "Zedan, Hussein S. M.", pages = "61--73", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "While special chips for message transfer in multi-transputer machines do not yet exist, there are several software solutions which may be used. Dynamic link reconfiguration is fastest but requires additional switching hardware and a sophisticated common bus to control requests from all network nodes. Through-routing of messages via the network is slower but the method is applicable to any transputer network. This paper makes a comparison between two through-routing solutions for distributed message passing and shows how the parameters of a software implementation influence the communication throughput. Several conclusions about the improvement of particular through-routing software are made and the results of the experimental performance evaluation under different conditions are given." } @InProceedings{PietroVillano90, title = "{A}n environment for transputer {CPU} load measurements", author= "Pietro, Giuseppe de and Villano, Umberto", editor= "Zedan, Hussein S. M.", pages = "74--82", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "In a multiprocessor system an uneven load balancing can usually dramatically reduce the performance of the parallel program running on it Hence it is of paramount importance to be able to estimate the CPU and communication loads of every task before the program is actually executed so that the optimal application partitioning can be found. In this paper the problem of CPU load measurement is tackled, and a measurement environment is illustrated in which the processes to be allocated to the processors in the network are run in quasi-concurrence on a single Transputer. A technique based on active process list manipulation makes it possible to perform a fairly accurate measurement of the CPU activity of the parallel processes in the application using the Transputer internal tinier as a reference clock." } @InProceedings{WijbransTillema90, title = "{A}n operating environment for control systems", author= "Wijbrans, K. C. J. and Tillema, H. G. and Bakkers, Andr\`{e} W. P. and Schoute, Albert L.", editor= "Zedan, Hussein S. M.", pages = "83--94", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "This article describes an operating environment for control systems. This operating environment contains the basic layers of a distributed operating system. Typical for this operating environment is that it is designed according to the needs of control systems. To do this, first the general requirements of a controller have been investigated. Based on the requirements posed by controllers as they can be found in complex systems, the requirements of the operating environment have been derived. This operating environment has been implemented on transputers. To test the performance of the operating environment, performance indicators were chosen and performance measurements were carried out for several different strategies. Due to the demanding nature of real-time control systems, special attention has been paid to an efficient implementation of a basic kernel." } @InProceedings{TambwekarShukla90, title = "{L}i{BRA} -- {A} load balancing tool for a reconfigurable parallel computer", author= "Tambwekar, Sanjay and Shukla, U. S. and Paulraj, A.", editor= "Zedan, Hussein S. M.", pages = "95--107", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "Load balancing in MIMD message-passing parallel computers is essential to make efficient use of the system resources and reduce the program runtime. For parallel computers that also provide topological \^{}configurability, it is necessary for the load balancing strategy to not only find an optimum distribution of tasks to processors, but also to determine the best-suited interconnection pattern for the processors. In this paper, we present an off-line tool, LiBRA, that will assist in automating the process of load balancing. The user specifies his problem in terms of a computation graph and the machine characteristics. LiBRA uses simulated annealing with an automatic annealing schedule to generate the optimal configuration." } @InProceedings{NieuwenhuBlom90, title = "{F}ault tolerant computing with transputers and occam", author= "Nieuwenhuis, L. J. M. and Blom, G. D.", editor= "Zedan, Hussein S. M.", pages = "108--118", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "In this paper the results of a case study with Transputers and Occam for a systematic approach of fault tolerant computing is presented. An arbitrary Transputer system can be transformed into a fault tolerant version without using additional special hardware. Fault tolerance is based on software implemented replication. The fault tolerant version consists of copies of the original system. Processes on the original Transputers can automaticly be transformed into versions which can be executed by the Transputers of the fault tolerant system. The reliability of the resulting system is optimal and performance optimizing properties of the original system are preserved." } @InProceedings{Barrett90, title = "{T}he {D}evelopment of occam: types, classes and sharing", author= "Barrett, Geoff", editor= "Zedan, Hussein S. M.", pages = "119--147", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "The proposed extensions to the occam* language are aimed at providing • a more comprehensive type system• support for a modular programming style• a facility for sharing between processes.The type system is similar to that of many modern programming languages but with a careful treatment of union types and without recursive types.Although it is possible to describe shared objects in occam2, the required idiom has an implementation whose complexity is linear in the number of users. By introducing a special sort of shared bus of channels, this problem can be overcome.The class system is designed in such a way as to allow for separate compilation and alien code classes to be used in occam programs with little overhead and to provide some of the abstraction mechanisms which have been recognised as beneficial in object-oriented languages.There are also a number of new language features which do not significantly change the nature of the language but which do enhance its general expressiveness.The first part of this paper presents proposed changes to the occam2 reference manual ([1]). The second part is a commentary on the decisions which had to be made in order to produce the proposal. The section numbers of the manual changes correspond to the section numbers of the occam2 reference manual where a ' denotes a change to an existing section and a letter denotes the insertion of a new section." } @InProceedings{DuVidalNaqu90, title = "{C}ombining configuration and allocation", author= "Du, Dong-Hui and Vidal-Naquet, Guy", editor= "Zedan, Hussein S. M.", pages = "148--157", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "This paper describes a method which makes hardware configuration transparent to Occam/Transputer users by doing automatic configuration of Transputer networks and allocation of programs. Some heuristic algorithms of combining network configuration with task allocation have been put forward. From an Occam program and an initial network topology, these algorithms construct a network topology which fits best the structure of the program, and allocate the program on the network so that its completion time is minimized." } @InProceedings{DebbageHill90, title = "{T}owards a distributed implementation of occam", author= "Debbage, Mark and Hill, Mark and Nicole, Denis A.", editor= "Zedan, Hussein S. M.", pages = "158--167", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "Progress has been made in providing a reasonable distributed implementation of the occam language. Primarily, this has involved the development of a routing kernel with a latent channel connection retaining occam syntax. Channel semantics are maintained by a message acknowledgement scheme and unrestricted message lengths. This provides the user with the potential for fully connected process communication without restrictions on node valencies or explicit PLACEment of any hard links.In addition the user program has been severed from any dependency on the topology by allowing multiple configuration level PROCESSORS to map onto a single transputer. Thus the user code can be run on any network which has been configured for the virtual channel router.Further development of the system has allowed us to implement the dynamic primitives that will be required by a compiler for distributed full occam. These include dynamic channel creation, remote procedure calls and facilities for moving channel ends." } @InProceedings{EastJassim90, title = "{C}ayley graphs and transputer network configuration", author= "East, Ian R. and Jassim, Sabah", editor= "Zedan, Hussein S. M.", pages = "168--174", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "The nature and use of Cayley graphs in understanding network topology design will be explained. The hypercube topology will be presented in group-theoretic form as an illustration and its isomorphism with tori, up to order four, will be shown. It will also be shown how to use the Cayley graph formulation to scalably configure a hypercube (with node process independent of identity within network). Lastly, we discuss the application of the Cayley formalism to infer and investigate new topologies which exhibit superior scaling of size and density to that of the hypercube, but which retain degree four and hence are suitable for transputer networks." } @InProceedings{SunterWijbrans90, title = "{C}ooperative priority scheduling in occam", author= "Sunter, Johan P. E. and Wijbrans, K. C. J. and Bakkers, Andr\`{e} W. P.", editor= "Zedan, Hussein S. M.", pages = "175--185", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "In this paper a scheduler for variable priority scheduling is presented. This scheduler assumes that the processes being scheduled cooperate with the scheduler. This cooperation introduces some latency in the scheduling of the processes. Analytic expressions describing the effect of this latency are derived. A variable priority scheduler was implemented and results from actual program executions are given. These results show that the scheduler can be used to schedule control algorithms with simple sequential processes with sample frequencies not higher than 2 kHz." } @InProceedings{CapraniKristense90, title = "{I}mplementation of real-time scheduling algorithms in a transputer environment", author= "Caprani, Ole and Kristensen, Jens E. and M\ork, Claus and Pedersen, Henrik Bo and Rasmussen, Finn R.", editor= "Zedan, Hussein S. M.", pages = "186--197", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "A variety of real-time scheduling algorithms is considered. Each algorithm is implemented on the transputer either in pure Occam or in Occam supplied with a few low level assembly procedures to manipulate the workspace queues. The algorithms used are non-preemptive non-priority scheduling, time-sliced non-priority scheduling, preemptive fixed priority scheduling (rate-monotonic scheduling) and preemptive dynamic priority scheduling (deadline scheduling). Furthermore, it is shown how access to shared data can be scheduled to meet time constraints. All the implemented scheduling algorithms have been assessed through experiments in order to estimate the overhead introduced." } @InProceedings{Welch90, title = "{M}ulti-priority scheduling for transputer-based real-time control", author= "Welch, Peter H.", editor= "Zedan, Hussein S. M.", pages = "198--214", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "A major requirement of real-time control applications is a set of cyclic processes — one for each \"control-law\". Each process must be managed so that it completes each cycle within a fixed time. The rate at which each process cycles will be constant, but will generally be different for different processes.Current transputer hardware provides very fast pre-emptive scheduling for two static priority levels, with \"round-robin\" management within each level. This is not sufficient to manage securely more than one such control-law per transputer — even at very low processor loadings. Efficient classical solutions (e.g. \"rate-monotonic\" or \"deadline\" scheduling) require multiple and time-varying priorities.This paper shows how to implement such solutions simply, and with an acceptable level of overhead, on the existing (and future) generation of transputer. Other promising scheduling methods are discussed. All solutions are expressed in occam with no assembler inserts and no security rules violated — the intended applications are safety-critical! Real performance figures are reported.Finally, a method of proving (or dis-proving) the security of any particular set of process loadings, operating under any particular scheduling algorithm, is described." } @InProceedings{MayThompson90, title = "{T}ransputers and routers: {C}omponents for concurrent machines", author= "May, David and Thompson, Peter", editor= "Zedan, Hussein S. M.", pages = "215--231", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "A transputer is a complete microcomputer integrated in a single VLSI chip. Each transputer has a number of communication links, allowing transputers to be interconnected to form concurrent processing systems. The transputer instruction set contains Instructions to send and receive messages through these links, minimising delays in inter-transputer communication. Transputers can be directly interconnected to form specialised networks, or can be interconnected via routing chips. Routing chips are VLSI building blocks for interconnection networks: they can support system-wide message routing at high throughput and low delay." } @InProceedings{VerhulstThieleman90, title = "{P}redictable response times and portable hard real-time systems with {TRANS}-{RTX}c on the {T}ransputer", author= "Verhulst, Eric and Thielemans, Hans", editor= "Zedan, Hussein S. M.", pages = "232--240", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "The transputer is a flexible processor, very well suited for applications where modularity and distributed operation are prime requirements, like in process control. Nevertheless, its basic FIFO-scheduling algorithm, makes its application for real-time processing quite difficult. This problem has now been solved by the development of a preemptive scheduling algorithm. This algorithm was used to port an existing real-time kernel to the Transputer. In addition, by taking account of the specific nature of the Transputer, much better performance and flexibility have been obtained." } @InProceedings{HartFlavell90, title = "{P}rototyping transputer applications", author= "Hart, E. and Flavell, S.", editor= "Zedan, Hussein S. M.", pages = "241--247", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "The design is discussed of a toolset capable of estimating the performance of a transputer application at the design stage, prior to detailed code being available. The Transim/Gecko package from the Polytechnic of Central London is discussed in detail as an example of such a toolset. The methodology of the package is discussed, its input language, output format and the transputer scheduling model to which it adheres. An example is described of a real transputer application where the tool has been successfully used to improve performance." } @InProceedings{MorseWelch90, title = "{D}iffusion limited aggregation: {A}n example of real-time parallelisation", author= "Morse, D. R. and Welch, A. M. and Welch, Peter H.", editor= "Zedan, Hussein S. M.", pages = "248--261", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "The simulation of the growth of Diffusion-Limited Aggregates (DLA) is representative of a class of 'shared' data-structure computations that does not yield to traditional parallelisation methods (such as 'farming', 'geometric decomposition' and 'data-flow'). The difficulty is that the shared data-structure is large and evolving, the required access to it from each processor is random and very high, and the computation per access is very low. These conditions also make these problems most unsuitable for shared-memory parallel computers.This paper presents a parallelisation technique that does give linear speed-up for this problem (at least, for up to 32 transputers). The cost-effectiveness of the solution compares favourably with those published that use vector-processing machines.The success of the parallelisation depends on real-time issues associated with keeping each worker transputer sufficiently up-to-date with all its colleagues. Some 'quasi-relativistic' effects need to be taken into account as well!The speed-ups achieved through this parallelisation are used to investigate the effect of various parameters (such as stride length and background drift) on the kind of DLA growth that is obtained. These studies would not be practical without the savings in time that have been realised from a parallel implementation of the DLA simulation.Finally, we characterise the features of those applications for which this parallelisation method is relevant." } @InProceedings{RoantreeClint90, title = "{A} formal top-down developement method for occam programs", author= "Roantree, Donal and Clint, Maurice", editor= "Zedan, Hussein S. M.", pages = "262--286", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "This paper describes a formal development method for mathematical applications in occam. Refinement rules form the basis of the method. A traces model is defined and used to give a formal semantics to occam. The rules are proved sound with respect to this semantics." } @InProceedings{BurnsWellings90, title = "{A}n assessment of the use of occam for dependable real-time systems", author= "Burns, A. and Wellings, A. J. and Zedan, Hussein S. M.", editor= "Zedan, Hussein S. M.", pages = "287--294", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "As occam based technology matures, and more transputer implementations evolve, new application domains will open up. This in turn will place fresh requirements on the language. In some instances occam, in its current form, will be unsuitable and language changes will be inevitable. This is, of course, at odds with producing a \"standard\" and \"stable\" language definition.The purpose of this paper is to identify the outstanding issues that must be discussed in the short, medium or long-term, if occam (and the transputer) is to be used for a wide range of dependable real-time applications in current and future systems. Our approach is to start with application requirements, from these to indicate occam problem areas and then, if appropriate, offer potential solutions. The areas considered are those associated with hard real-time, software reliability, mode changes, dynamic change management and fault management." } @InProceedings{Nowinski90, title = "{M}emory access synchronization in series expansion methods of parallel image reconstruction", author= "Nowinski, W. J.", editor= "Zedan, Hussein S. M.", pages = "295--304", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "The paper is concerned with parallel image reconstruction. The background of parallel image reconstruction has been briefly reviewed. Parallel formulations of series expansion methods expressed in occam exploiting projection and ray parallelisms have been presented. Two types of mapping of the projection space onto the image space influencing a simultaneous memory access have been defined. Finally, several ways of synchronizing the activities of processes when accessing the memory have been discussed." } @InProceedings{HopkinsVowden90, title = "{D}istributing matrix eigenvalue calculations over transputer arrays", author= "Hopkins, Tim and Vowden, Barry", editor= "Zedan, Hussein S. M.", pages = "305--312", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "We discuss the parallel numerical solution of the matrix eigenvalue problem for real symmetric tridiagonal matrices. Instances occur frequently in practice. Two implementations of the Sturm sequence algorithm on transputer arrays are described. For the first the maximum size of matrices which may be accommodated is restricted by the amount of local memory available. The second implementation removes this constraint but requires an increased execution time." } @InProceedings{ChalmersFiddes90, title = "{P}arallel panel methods", author= "Chalmers, Alan G. and Fiddes, Steven P. and Paddon, Derek J.", editor= "Zedan, Hussein S. M.", pages = "313--321", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "The nature of panel methods makes parallelisation difficult, unless effective methods can be found that minimise the number of messages required to calculate the interaction of all panels in the problem domain. Here, we use a minimal path configuration of processors to give an effective solution and show its performance superiority over a solution obtained from a ring configuration of processors. A detailed description of the numerical model and the numerical methods that are used for a typical panel method problem is given.The importance of balancing the message generating parts of an algorithm are established by examining the influence matrix set-up time and the matrix solution time. The scalability and maximum performance characteristics of the algorithm and system configuration are analysed and reported." } @InProceedings{RainaWarren90, title = "{S}hared virtual memory on transputers via the data diffusion machine", author= "Raina, Sanjay and Warren, David H. D. and Cownie, James", editor= "Zedan, Hussein S. M.", pages = "322--330", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "The Data Diffusion Machine (DDM) is a novel multiprocessor architecture which is scalable to an arbitrary number of processors and at the same time provides a shared virtual address space. There is no fixed home location for data - instead data migrates from one processor to another on demand. A cache coherence protocol maintains memory consistency allowing replication, migration and replacement of data.In order to evaluate the DDM we are developing an emulator on the Meiko Computing Surface. This paper describes the DDM emulator together with additional support to turn the emulator into a platform for running real shared memory applications. We describe how the bus based snoopy protocol of the DDM can be modified to suit point-to-point interconnection networks." } @InProceedings{AbdennadhAngue90, title = "{A}m interactive graphical debugger for occam programs", author= "Abdennadher, N. and Angue, J. C.", editor= "Zedan, Hussein S. M.", pages = "331--338", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "Parallel programs are usually described informally, and these descriptions are implemented on parallel computer systems. When the program does not work correctly, it is difficult to detect the semantic error: deadlock, starvation, etc ... We propose in this paper an interactive graphical debugger of parallel programs written in OCCAM and executed and developed on Transputer Network which is implemented on IBM PC motherboard. The debugger provides the programmer a graphical representation of the dynamic behaviour of the OCCAM programs." } @InProceedings{AdamoBonnevill90, title = "{V}irtualising communication in the {C}-{NET} high level programming environment", author= "Adamo, Jean\_Marc and Bonneville, J. and Bonello, C.", editor= "Zedan, Hussein S. M.", pages = "339--349", booktitle= "{OUG}-13: {R}eal-{T}ime {S}ystems with {T}ransputers", isbn= "90 5199 041 3", year= "1990", month= "sep", abstract= "A tool for virtualising communication on the SuperNode machine is presented. The tool provides four facilities: virtual interprocessor communication channels, Transputer links multiplexing, link load-balancing, and consistent termination of aborted interprocessor communication." } @InProceedings{EdwardsLawson91, title = "{T}he advancements of transputers and occam", author= "Edwards, Janet and Lawson, Philip", editor= "Edwards, Janet", pages = "1--12", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "In our eagerness to promote Occam and Transputers on the World stage, we must not forget that the now common place jargon of the Occam User Group may be very new to those practitioners that are entering this realm for the first time. For the benefit of students, old and young alike, who have missed out on the hype that surrounded the transputer in the 1980s, what follows should provide a brief insight into this complex field. Beyond introducing the current transputer hardware and Occam software, a glimpse of things to come is provided by a pre-release view of the IMS T9000 transputer and the next generation of the Occam language. This overview concludes with a short pr\`{e}cis of each of the papers that contributed to this, the 14th World Occam and Transputer User Group technical meeting." } @InProceedings{KerridgeOates91, title = "{A}spects of database machine design using the {H}1, {C}104 and {O}ccam91", author= "Kerridge, Jon and Oates, Richard J.", editor= "Edwards, Janet", pages = "13--27", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "In this paper we explore the design of a database machine that is already being implemented using T series transputers to determine the benefits of using the T9000 series transputer togeher eith its associated routing chip, the C104, and occam91. The language occam91, a superset of occam2, contains language features that directly support the exploitation of hardware features that have been incorporated into the T9000 transputer. We briefly introduce the underlying design of the database machine. The way in which the C104 routing chips can be used is then described in conjunction with a planar approach to the interconnection of nodes in the machine. Finally, we give fragments of occam91 that demonstrated how its features can be used in two different parts of the database machine. The first application considers the problems of allocating resources to a user query and the second looks at how recovery features can be specified." } @InProceedings{SunterBakkers91, title = "{P}erformance of post-game analysis on transputers", author= "Sunter, Johan P. E. and Bakkers, Andr\`{e} W. P.", editor= "Edwards, Janet", pages = "28--38", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "In this paper the performance of a Post-Game Analysis system is studied. For this purpose several simple cases have been designed. These cases consist of a number of processes which have to be distributed over a network of transputers. The final distributions for these cases are compared to the optimal ones, which can be easily derived for these simple cases. Performance measures considered include the number of iterations required to reach the final distribution, and the overhead caused by monitoring the program behaviour." } @InProceedings{PhillipsCapon91, title = "{S}trategies for workload distribution", author= "Phillips, Iain and Capon, Peter C.", editor= "Edwards, Janet", pages = "39--51", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "If large distributed systems, such as transputer networks, are to be exploited fully, effective workload distribution strategies are required. For such systems to be successfully scalable, decision making in such strategies will need to be both dynamic and distributed. The choice of strategy depends on many factors, including the size and topology of the network together with the nature of the application. The success of any particular strategy is measured by comparing the time taken to execute the application on many processors with the time taken on few processors." } @InProceedings{BakerMilner91, title = "{A} process migration harness for dynamic load balancing", author= "Baker, S. A. and Milner, K. R.", editor= "Edwards, Janet", pages = "52--61", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "In order to attain high efficiency and maximum throughput from MIMD architectures, it is necessary to have a balanced load with all processors being utilised. If the optimum program configuration is data-dependent, the process distribution will have to be performed at run time, i.e. dynamically. A message-passing harness has been developed with a process migration capability for dynamic loca-balancing on transputer-based machines. This paper describes the process migration harness and the way in which it is integrated with the user's application, gives a brief survey of the types of dynamic load balancing algorithm currently under investigation and concludes with some preliminary performance results." } @InProceedings{Robinson91, title = "{A} simple parallel algebraic multigrid", author= "Robinson, Guy", editor= "Edwards, Janet", pages = "62--75", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "This paper describes an \"algebraic multigrid\" scheme which can be applied to a wide range of matrix based problems. Multigrid schemed offer significant gains in both numerical performance and runtimes compared to conventional solvers. The equations for the hierachy of grids are generated solely from the equation for the fine mesh without generating the intermediate grids or relying on geometrical features of the fine mesh. The development of the code for distributed memory Multiple Instruction Multiple Data architectures is detailed. The numerical and run time performance is described for simple linear equation sets and as a linear solver for coupled equations as part a 3D computational fluid dynamics code." } @InProceedings{KhanStephens91, title = "{F}ast fourier transform on transputers", author= "Khan, Aman and Stephens, Nelson", editor= "Edwards, Janet", pages = "76--84", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "The fast evaluation of the Discrete Fourier Transform on a system with a large number of transputers is considered. The implementation uses a configuration of the transputers which leads to a very high performance. The design and implementation incorporate several new features. Tables of this performance, in terms of actual times and speed-up as the number of data points and transputers vary, are presented. Implementation aspects of the radix-2 and higher radix DFT in one and two dimensions are considered. The timings are compared with those for other computers and found to be favourable." } @InProceedings{CunhaHopkins91, title = "{A} new adaptive algorithm for the solution of systems of linear equations", author= "Cunha, Rudnei Dias da and Hopkins, Tim", editor= "Edwards, Janet", pages = "85--99", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "We present a comparison between serial and parallel implementations of some iterative methods to solve systems of linear equations. The basic vector arithmetic operations used in the implementations are discussed with respect to its parallelization. The iterative methods considered are the Adaptive SOR (A-SOR), the Steepest-descent (G), an adaptive version of the steepest-descent method (A-G), the Richardson's Optimum-Extrapolated (RF-OE), and the Conjugate Gradient (CG)." } @InProceedings{EvansMargariti91, title = "{S}imulation of optical systolic and neural network using occam", author= "Evans, D. J. and Margaritis, K. G.", editor= "Edwards, Janet", pages = "100--110", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "This paper describes the simulation of optical processors for performing optical systolic and neural net algorithms. Occam is used as a simulation langugage and each component of the optical processor is defined as an occam process." } @InProceedings{GeeWorrall91, title = "{D}evelopement methods and occam", author= "Gee, David M. and Worrall, Barry P. and Henderson, W. D.", editor= "Edwards, Janet", pages = "111--122", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "Existing structured methods for real-time systems are critically reviewed with respect to their suitability for direct implementation in occam without transformation. All are found to have weaknesses in some respects; consequently new notations are proposed. Use of these within an appropriate tool framework could assist in the automatic generation of occam code." } @InProceedings{DebbageHill91, title = "{A} general-purpose parallel programming environment", author= "Debbage, Mark and Hill, Mark and Nicole, Denis A.", editor= "Edwards, Janet", pages = "123--132", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "A parallel programming environment has been developed which is superior to many available systems on current generation transputers. The core of the package is a packet router which delivers asynchronous datagrams around arbitrary networks. The router is guaranteed not to deadlock provided that higher levels do not violate the eager-readership edict. This eager0readership can be guaranteed by the use of communication protocols which ensure that packets are never sent to a destination which has insufficient buffer space available. The router has been implemented in C and is applicable to a wide number of loosely coupled multiprocessing architectures. The current implementation has been optimised for transputer networks, on which it achieves impressive communications performance. The implementation of a virtual channel protocol within occam semantics on such a router is discussed. This forms the basis of version 2.0 of the popular Virtual Channel Router (VCR) package. The user interface to these channels is the conventional occam syntax for communications but with the configuration restriction of four channel-pairs per processor eliminated. The virtual channels provided by this package can be exploited from other languages through the appropriate Inmos Toolset." } @InProceedings{Villano91, title = "{R}epeatable execution of occam programs", author= "Villano, Umberto", editor= "Edwards, Janet", pages = "133--142", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "Parallel programs are intrinsically non-deterministic, and therefore the techniques of cyclical debugging that are commonly used for sequential programs are not suitable for parallel ones. This paper proposes a method for guaranteeing the repeatability of occam program behaviour. Saving information on the ALT guards selected at run-time allows program replay. i.e. makes it possible to re-execute the program following the same instruction path whatever the speed at which each component process is executed. This enables the software developer to use tools such as debuggers and intrusive monitors to help identify program errors. After a discussion on the possible implementations of the proposed technique, a prototype tools that allows the replat of occam programs within TDS is briefly described." } @InProceedings{CrookesMorrow91, title = "{A} {S}oftware {D}evelopement {E}nvironment for {P}arallel {I}mage {P}rocessing: {I}mplementation techniques and issues", author= "Crookes, D. and Morrow, Philip J. and McClatchey, I. and Rafferty, T.", editor= "Edwards, Janet", pages = "143--149", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "A program development environment has been designed for building transputer based image processing systems. The system has two main components: a library of (parallelised) image processing operations, and a graphical user interface. After introducing the user interface, the paper concentrates on the implementation techniques and issues involved in constructing the environment. The main implementation areas considered are: a flexible and highly parameterised library of image processing routines; the provision of a communications shell which utilises the underlying parallelism without the user having to be concerned about it; and the extensibility of the environment by adding new components to the library." } @InProceedings{BrittanFairhurst91, title = "{I}ntegration of {C}lassification and {E}valuation {P}rocedures in the {I}mplementation of {P}arallel {I}mage {A}nalysis {A}lgorithms", author= "Brittan, P. and Fairhurst, M. C.", editor= "Edwards, Janet", pages = "150--158", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "The requirements of adaptability and high performance often dictate a parallel processing approach for cost-effective algorithm implementation in many real-time applications of image classification. The aim of this paper is twofold. First it seeks to illustrate that by giving careful consideration to the conceptual architecture of the image classifier and its implementation base levels of performance can be achieved. Second, it will discuss the principal features of implementing multi-layer classifier algorithms, performance evaluation processes, and high-speed data handling required for evaluation, over an array of transputers." } @InProceedings{WelchJusto91, title = "{O}n the serialisation of parallel programs", author= "Welch, Peter H. and Justo, G. R. Ribeiro", editor= "Edwards, Janet", pages = "159--180", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "This paper argues that one of the key techniques for making the most efective use of multi-processor architectures is the serialisation of parallel code! Parallel algorithms are presented as having strong engineering merits that will form the natural basis for systems design in the future. Parallelisation of serial code is regarded as having only short-term value (for \"dusty-decks\", whose correctness cannot be verified) as well as being mathematically intractable. Serialisation, on the other hand, is much easier to automate and can be profitably employed today. Several serialising transforms for occam processes are presented and applied to various simulation and image compression tasks." } @InProceedings{SturrockSalmon91, title = "{A}pplication of occam to biological sequence comparisons", author= "Sturrock, Shane S. and Salmon, Ian", editor= "Edwards, Janet", pages = "181--190", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "One of the major uses of computers by molecular biologists is the alignment of protein or DNA sequences. Since the structure and function of proteins and DNA cannot be predicted directly from sequence data alone, the most useful procedure is to compare unknown sequences against a database of known sequences. Those with a high degree of homology are likely to have similar properties. At present, the databases are growing exponentially with doubling in around 20 months. Consequently, comparisons are taking proportionately longer to complete. We have applied various sequential comparative algorithms within a farming harness constructed in occam from a pipeline of transputers. The design of the farming harness for optimum link communication is discussed. The advantage our method offers is scalability; an important consideration as the databases multiply in content. The ability to tailor the algorithm to work on various size networks of transputers also allows the user to weigh time considerations against the total cost of the system. Our present implementation can perform around 600 comparisons per second between a query sequence of 50 residues and a database using 64 worker processors." } @InProceedings{EdwardsConnolly91, title = "{I}mplementing an {A}ctive {C}hart {P}arser on a {T}ransputer {N}etwork", author= "Edwards, Janet and Connolly, John H.", editor= "Edwards, Janet", pages = "191--200", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "Active chart parsing is a well-known technique for the syntactic analysis of natural language. This paper is concerned with the parallel implementation of the relevant algorithm in Occam-2 on a Transputer network. Different parallelisation strategies are compared, and it is concluded that better results are obtained by splitting the grammar associated with the parser than by decomposing the algorithm itself." } @InProceedings{WalterKerridge91, title = "{A} {S}calable {C}ommunication {N}etwork for a {P}arallel {D}atabase {M}achine", author= "Walter, David and Kerridge, Jon", editor= "Edwards, Janet", pages = "201--216", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "The IDIOMS parallel database machine has at its kernel a scalable communications structure. The scalability is fundamental to the database machine because it is intended that the parts which are joined together by the communications network can be added to as demands on the database machine change. The network must be scalable both in terms og the number of user processes which can be supported, and, in order to meet the performance requirements of large systems, it should be possible to scale up the bandwidth of the network by adding further communication processors. The structure of a node in the network is described in terms of itsccam behavior which shows how node control is achieved by a control process that manipulates a set of flags by means of channel communications. The network is shown to be free from the possibility of deadlock. Finally, the performance and operational characteristics of the network are discussed and it is shown that the network is ideally suited for parallel database operation." } @InProceedings{Highfield91, title = "{P}arallel {S}can {L}ine algorithm for {H}idden {S}urface {E}limination", author= "Highfield, Julian C.", editor= "Edwards, Janet", pages = "217--224", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "With the general availability of general purpose parallel computers, there is a need to reconsider scan conversion algorithms with respect to their parallel implementation. This paper considers MIMD parallel implementation of two versions of the scan conversion algorithm, one the common edge table optimisation, and one not. Their suitability for parallel implementation is investigated and their relative performance in multi-processor systems is measured using polygonal scene descriptions of between 150 and 2600 polygons. Dependence upon the size of scene description is measured and results are extrapolated to larger scene descriptions. It is shown that scan conversion algorithms may be efficiently parallelised. It is also shown that the edge table optimisation, while appropriate to the single processor case, becomes useless at around twenty processors, and would actually be a disadvantage in the limiting case of one processor per scan line." } @InProceedings{Shallow91, title = "{P}rocessor {I}ndependant and {E}xtendable {R}outing {S}ystem using a {C}yclic {R}outing {A}lgorithm", author= "Shallow, P. A.", editor= "Edwards, Janet", pages = "225--233", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "PIERS is a deadlock free virtual routing system developed for distributed concurrent applications. It deliberately exploits the advantages gained by allowing cycles to occur in the channel dependency graph and incorporates the cycles into the routing algorithm. It directly interfaces with the user's application and uses the existing OCCAM channel primitives. The paper describes how this cyclic routingalgorithm operates and how deadlock is averted. It describes how the routing system is implemented, presents the performance figures obtained and summarises the network configuration utility written to integrate the communication harness with the user's application." } @InProceedings{Croll91, title = "{D}eterministic {M}essage {R}outing for {S}afety-{C}ritical {A}pplications", author= "Croll, Peter R.", editor= "Edwards, Janet", pages = "234--246", booktitle= "{P}roceedings of {W}o{TUG}-14: {O}ccam and the {T}ransputer-{C}urrent {D}evelopments", isbn= "90 5199 063 4", year= "1991", month= "sep", abstract= "This paper considers a technique of message passing which can be applied in the development of parallel programs for safety-critical applications. The routing algorithm used to ensure that messages will always be able to meet hard real-time constraints and yet cope with some degree of hardware failure. This paper will firstly introduce the routing algorithm, it will indicate what properties can be proved about deterministic message passing and describe how the algorithms cope with hardware failure. From this, the details of possible solutions that the new T9000 family can offer will be presented." } @InProceedings{Talia92, title = "{M}essage routing systems for transputer based parallel computers", author= "Talia, Domenico", editor= "Allen, Alastair R.", pages = "1--12", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "An efficient communication system is an essential component of a transputer-based parallel computer. In the last years many message routing systems for transputer networks have been developed. They allow data exchanging among processes mapped on transputers not directly connected. This paper surveys and compares some of these routing systems with respect to several criteria, such as deadlock freedom, adaptivity, network latency, livelock freedom, and generality." } @InProceedings{PhilipsCandlin92, title = "{A}n environment for investigating the effectiveness of process migration strategies on transputer-based machines", author= "Philips, Joe and Candlin, Rosemary", editor= "Allen, Alastair R.", pages = "13--23", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "This paper describes an experimental system which can be used to study and compare the behaviour of different process migration strategies for occam programs running on transputer machines. The approach taken involves loading the code and data for every process onto every transputer. Processes can then be enabled and disabled to reflect the initial placement and subsequently to reflect process migrations. While simplifying the implementation process this means that the entire program must fit onto a single transputer. A statistics collection mechanism has also been implemented to enable intelligent migration decisions to be made. The system has been verified using a random migration strategy on several candidate programs." } @InProceedings{CaiSkillicor92, title = "{E}valuation of a set of message- passing routines on transputer networks", author= "Cai, Wentong and Skillicorn, David B.", editor= "Allen, Alastair R.", pages = "24--36", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "A major obstacle to the use of parallel computers in ordinary applications, where their price/performance ratio should make them attractive, is the sheer difficulty of parallel programming. One approach which can ease the difficulties is data parallel programming, because of the simplicity of a single-threaded flow of control. Data parallelism also expresses parallelism with enough regularity to be readily implemented across a range of machine types. In this paper, we describe a data parallel model based on a set of second order functions from the Bird-Meertens theory of lists, demonstrate the implementation of these functions as a set of message-passing routines, and evaluate their performance on transputer networks configured as hy-percubes." } @InProceedings{TollenaerRoose92, title = "{P}erformance modelling of a parallel meural network simulator", author= "Tollenaere, Tom and Roose, Dirk", editor= "Allen, Alastair R.", pages = "37--48", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "A model program structure is presented for parallel applications with local interactions between the data elements, such as neural networks simulations and the solution of partial differential equations. The performance of this model program is analyzed both theoretically by means of classical performance models, and experimentally using a parallel neural network simulator program. The program runs on a Meiko transputer array, and uses the Meiko CSTools libraries for its communications. The comparison of both analyses allows to predict applications performance on new and other machines, and indicate what parts of an application are worth optimizing. Moreover, it is shown that classical theoretical models not always capture the behavior of a real machine." } @InProceedings{Day92, title = "{F}arming: {T}owards a rigorous definition and efficient transputer implementation", author= "Day, Warren", editor= "Allen, Alastair R.", pages = "49--62", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "The technique of the processor farm has become a very widely used for parallelising applications, often being mentioned without reference to any source.The goal of this work has been to put together a complete and rigorous understanding of what the technique can be used for and what is needed in order to arrive at an efficiently farmed application. This paper consists of these two parts.We have shown, via the UNITY theory of programming, that the basic structure of the processor farm may be used to parallelise a much wider domain of applications than has generally been considered.Second, we show by example, how to build efficient implementations for the first generation of INMOS Transputers. This work is new in that it is the first that has been able to test farming harnesses by taking an abstract view of the application.This paper has been written in a semi-\"instruction manual\"\" style. Also it should serve as an introduction to the subject." } @InProceedings{Culloch92, title = "{P}orting the 3{L} {P}arallel {C} environment to the {T}exas {I}nstruments {TMS}320{C}40", author= "Culloch, Alan D.", editor= "Allen, Alastair R.", pages = "63--76", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "The TMS320C40 ('C40) is a transputer-like parallel processor from Texas Instruments. It is an order of magnitude faster than the T800 transputer. Parallel C is a popular programming environment for the transputer. The properties of both the 'C40 and Parallel C are described and the significant differences between the 'C40 and the transputer are pointed out. The techniques used to overcome these obstacles to porting Parallel C are presented. These include building a new real-time kernel and reusing existing software packages from industry and academia. The suitability of the 'C40 for parallel applications is discussed." } @InProceedings{SoraghamGan92, title = "{T}ransputer based adaptive signal processing", author= "Soragham, John J. and Gan, Woon S. and Goh, Kwong H. and Stewart, Robert W. and Durrani, Tariq S.", editor= "Allen, Alastair R.", pages = "77--96", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "Transputer based adaptive signal processing systems are considered. Efficient use of data communication networks requires adaptive equaliser structures that are efficient and have fast mean square error (MSE) convergence rates. The transputer based non-canonical least mean square (NCLMS) algorithm is implemented using a variant of the standard finite impulse response (FIR) filter,called the non-canonical FIR (NCFIR). Simulation results are given which show areduced excess mean square error level and an improved performance in an impulsive noise environment for the NCLMS over the conventional least mean square (LMS) algorithm. Simulation results comparing the LMS and NCLMS are presented.The equaliser structure based on the Kalman Filter has convergence rates that are independent of the channel's characteristics. A transputer based Kalman Equaliser and fast Kalman Equaliser are described. Speed-up curves for a variety of topologies for both systems are included." } @InProceedings{DodgeRoss92, title = "{A} transform accelerator for a transputer system", author= "Dodge, C. J. and Ross, P. G. B. and Undrill, P. E. and Allen, Alastair R.", editor= "Allen, Alastair R.", pages = "97--111", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "A DSP based image transform accelerator for a transputer system is described. The formal specification language Z has been employed in the accelerator design, examples of which are presented including aspects of the refinement process and some of the problems encountered in working with a combined hardware/software specification." } @InProceedings{SmithWelch92, title = "{A} transputer based active vision system", author= "Smith, Andrew B. and Welch, Peter H.", editor= "Allen, Alastair R.", pages = "112--121", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "The visual detection and tracking of moving targets is computationally intensive and any but the most simple tasks are beyond the ability of single processor architectures. Many algorithms that are parallel in nature have been suggested for the recognition and tracking of moving targets. Implementing these algorithms on parallel computer systems requires the transcription of a massively parallel architecture onto a system with fewer physical processors. This, of course, is a much easier transformation than the reverse process: distributing a serial algorithm effectively over multiple processing elements.This paper describes a parallel Transputer implementation of a vision tracking system. The system is able to track a designated target by the physical movement of the camera. The camera is mounted on a pan and tilt unit and its movement and lens are under full control of the system. The system is modular in nature having been designed in three stages: i) the pre-processing of the image and extraction of edge information, ii) the control of the focus and gain of the lens, and iii) the detection and tracking of moving targets. The system operates in real-time (i.e. 25 frames/second)." } @InProceedings{Stokar92, title = "{SYDAMA}-2: a heterogeneous multiprocessor system for real time image processing", author= "Stokar, Dieter", editor= "Allen, Alastair R.", pages = "122--128", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "In this paper we will present the architecture of SYDAMA-2 and its programming environment as well as early experiences gained in developing applications with it. The goal of this project was to find and develop an architecture that was capable of executing entire applications in the domain of real time image processing. The architecture consists of two parts: one for low level preprocessing and one for intermediate and high level postprocessing.The preprocessing subsystem is based on the direct mapping of static dataflow graphs onto hardware. While highly specialized processing elements can be implemented for reasons of efficiency most of them consist of lookup tables for the sake of their processing speed and flexibility. All of them are controlled by a transputer that does the housekeeping.The processing elements are interconnected through a communication network which is realized as a pipelined multichannel ringbus that is fully reconfigurable on the fly. The bandwidth is large enough to carry several video streams and because the buses can be subdivided at every stage, the overall bandwidth effectively scales with the number of stages (processing elements).The postprocessing subsystem consists of a standard off the shelf transputer network that is closely connected to the low level subsystem.The programming environment consists of a number of tools that cover the different stages of programming an application: The low level programming interface for the image processing subsystem, a configuration tool and the runtime support that controls and interconnects the different tasks." } @InProceedings{BarrettBarton92, title = "{G}eneral purpose parallel computers: a standard architecture with a standard programming interface", author= "Barrett, Geoff and Barton, Eric and Carden, Trevor and Duval, Dominique and Nicole, Denis A.", editor= "Allen, Alastair R.", pages = "129--138", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "Recent developments in the area of high performance computing are pointing the way to a standard architecture for parallel computers. This architecture contains a number of medium-cost processing elements which communicate with each other through a high-bandwidth, low-latency interconnect. The design of the interconnect eliminates the concerns of \"locality\" which are current in the programming of present-day machines. This \"flat\" topology and common architectural model lead to increased opportunities for establishing portable software for high performance computing. The Esprit GP-MIMD project has exploited these opportunities by developing the architectural model and denning a programming interface for software which runs efficiently on machines with a range of processing power." } @InProceedings{SheaCheung92, title = "{A}n efficient multi- priority scheduler for the transputer", author= "Shea, K. M. and Cheung, M. H. and Lau, Francis C. M.", editor= "Allen, Alastair R.", pages = "139--153", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "Multi-priority scheduling is essential in a spectrum of applications especially those involving real time. We have extended the hardware scheduler in the transputer to support multi-priority scheduling. We did it by implementing a layer of provably safe and efficient queue manipulation primitives and a \"plug-in\" data structure for process queueing on top of the original scheduler. For optimal performance, different data structures for queueing may be plugged into our scheduler to suit different application domains. We tested our scheduler with different process loads (up to 200 processes) and the performance is excellent: overhead due to the scheduler accounts for less than 1\% of a timeslice on a T8." } @InProceedings{MoronZedan92, title = "{T}owards an adaptable scheduler for real-time system", author= "Moron, Celio Estevan and Zedan, Hussein S. M.", editor= "Allen, Alastair R.", pages = "154--166", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "Issues for designing adaptable real-time scheduler are discussed. A general approach that utilises milestones [1] is given and illustrated using the Least Laxity Algorithm. Some performance results are also given (in the form of upper bound of the overhead)." } @InProceedings{Peel92, title = "{TCP}/{IP} on transputers -- the performance implications", author= "Peel, Roger M. A.", editor= "Allen, Alastair R.", pages = "167--179", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "At the 14th WoTUG Technical Meeting at Loughborough University in September 1991, Graeme Tozer from INMOS described the architecture of the IMS B300 Ethernet Interface. This product supports four external transputer networks, providing each with an Iserver interface to Ethernet and connectivity to a host Iserver running on a processor elsewhere on the Ethernet. Performance claims in the range 200-300 kbytes per second were made for raw TCP transfers between a typical Unix workstation and transputers networked to it using the B300. This paper outlines the techniques which the author has used recently to enhance the performance of his own pipelined TCP/IP implementation for Ethernet to achieve throughputs of up to 925 kbytes per second on substantially similar hardware. Many of these techniques are equally appropriate to any large communicating process application." } @InProceedings{BalboniCabodi92, title = "{A} transputer-based accelerator for digital circuits fault simulation", author= "Balboni, G. P. and Cabodi, G. P. and Gai, S. and Reorda, M. Sonza", editor= "Allen, Alastair R.", pages = "180--186", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "Fault simulating digital devices requires powerful tools able to deal with their increased size and complexity. Software simulators are often unable to satisfy the needs of designers and test engineers due to the size of the simulated circuits, and to the large number of faults; hardware accelerators have been proposed to solve the problem. We present a system running on a net of transputers which uses a fault-partitioning strategy to fully exploit the available processors. The results show that this solution can represent a good trade-off between the cost of the system and the obtained speed-up." } @InProceedings{BarrettMay92, title = "{F}ormal methods in the design of the {T}9000", author= "Barrett, Geoff and May, David and Shepard, D.", editor= "Allen, Alastair R.", pages = "187--204", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "The complexity of integrated circuits continues to grow, and chips with over 100,000,000 transistors will be in widespread use by the late 1990s. These chips will combine general purpose processors with subsystems for communications and other specialised tasks. They will be far too complex for the design to be tested, and manufacturing volumes will be far too high for the design to be wrong!Mathematical techniques have already been applied to the design of parts of VLSI chips. Most of this work is experimental, and requires an unusual combination of engineering, mathematical and programming skills. Sometimes new theoretical work is needed, and specialised tools may have to be constructed. Despite these difficulties, mathematical techniques are playing an important role in the design of microprocessors at INMOS and techniques suitable for incorporation in standard computer-aided design systems are emerging." } @InProceedings{MansonCachia92, title = "{H}ow to achieve replication within a {CASE} tool environment", author= "Manson, Gordon A. and Cachia, E. A. and Boyle, A.", editor= "Allen, Alastair R.", pages = "205--217", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "A CASE tool, called ParStP, has been developed at the University of Sheffield. ParStP is built on top an existing open CASE tool called Software through Pictures and it combines design, compilation, running, testing and documentation into one integrated system. This paper shows how ParStP is being extended to cope with replication." } @InProceedings{GmBH.92, title = "{T}he {PARIX} pregramming environment", author= "GmBH., Parsytec", editor= "Allen, Alastair R.", pages = "218--230", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "The new Parsytec GC is a high-performance parallel processing system for scientific and technical applications.Between 64 and 16,384 processors provide a computational performance from 1 to 400 GigaFlops (peak performance, double precision, 190 GigaFlops sustained, double precision) thus meeting even the most extreme demands.In the software environment PARIX, users work with standard compilers for Fortran and C, make use of UNIXdevelopment tools and libraries and have high-performance systems for I/O, backup, graphics and video.The Parsytec GC is based on Inmos T9000 processors which can be structured into random topologies and which communicate both, the Inmos T800/T805 and the, at a maximal rate of 80 MBytes/s." } @InProceedings{DingxingXinmin92, title = "{A}n {O}ptimised {P}arallel {C}ompiler for {E}xecuting {D}eclarative {P}rograms on {T}ransputer {A}rray", author= "Dingxing, Wang and Xinmin, Tian and Weimin, Zheng and Meiming, Shen and Dongchan, Wen", editor= "Allen, Alastair R.", pages = "231--245", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "Many Declarative Programming Languages (DPLs) such as KL1, Prolog, PARLOG, Miranda and SML are considered attractive candidates for artificial intelligent application and execution on parallel architecture. However, there are many issues such as compile-time granularity analysis, partial evalution, task scheduling and load balancing for the efficient implementations of DPLs on multiprocessor system. In this paper, we take the emphasis on the compiling implementation of PARLOG and SML on a distributed memory multiprocessor system (transputer array). Under the graph rewriting framework, a Heterogeneous Parallel Graph Rewritng Execution Model (HPGREM) and corresponding description Language CIL are proposed. Based on the HPGREM, a parallel abstract machine PAM /TGR (Parallel Abstract Machine for Term Graph Rewriting) and corresponding compilation rules to generate PAM/TGR code are presented. Futhcrmore, an optimised parallel compiler for executing declarative programs on transputer array is described. The performance statistic on a 16-nodes transputer array demonstrates the effectiveness of our model, compiling techniques and compiler." } @InProceedings{SeredynskKitajima92, title = "{I}mplementation of learning automata games on a 128-transputer reconfigurable machine using {VCR}1.8c ({V}irtual {C}hannel {R}outer)", author= "Seredynski, Franciszek and Kitajima, Jo\~{a}o Paulo and Plateau, Brigitte", editor= "Allen, Alastair R.", pages = "246--250", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "An implementation of learning automata games on a distributed memory message-passing reconfigurable multiprocessor with 128 Transputers is presented. The game is played using a conjugate exchange process in order to transform the maximal price point into the Nash point. The game was implemented in Occam2 with Virtual Channel Router (VCR), a router developed at the University of Southampton." } @InProceedings{LaakHertzberg92, title = "{N}onconvex continuous optimization experiments on a transputer system", author= "Laak, A. ter and Hertzberger, L. O. and Sloot, P. M. A.", editor= "Allen, Alastair R.", pages = "251--265", booktitle= "{P}roceedings of {W}o{TUG}-15: {T}ransputer {S}ystems - ongoing {R}esearch", isbn= "90 5199 085 5", year= "1992", month= "mar", abstract= "In this paper we investigate the functionality of various parallel implementations of Simulated Annealing on a transputer platform. The optimization problem to be solved is that of efficiently finding the global minimum in continuous spaces. Our work concentrates on the consequences of long-range and short-range interactions on algorithmic and geometric decomposition schemes. We introduce a mixed transputer topology to by-pass some of the inherent time critical operations involved. We show that combining the Fast Simulated Annealing algorithm with a systolic decomposition strategy results in a highly efficient algorithm for continuous optimization problems. Experiments indicate that incorporation of functional decomposition of the energy function results in a near optimal implementation." } @InProceedings{Johnson93, title = "{T}he {INQUEST} {T}ransputer {N}etwork {D}ebugger", author= "Johnson, M.", editor= "Kerridge, Jon", pages = "1--10", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{Thompson93, title = "{G}lobally-{C}onnected {F}ault-{T}olerant {S}ystems", author= "Thompson, Peter", editor= "Kerridge, Jon", pages = "11--24", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{BurgessLivesey93, title = "{A}n {E}xecution {H}arness for {T}ransputer {B}ased {E}mbedded {S}ystems", author= "Burgess, P. and Livesey, M. J. and Allison, C.", editor= "Kerridge, Jon", pages = "25--40", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{JellyMorris93, title = "{M}ixed {L}anguage {P}rogramming for {T}ransputer {N}etworks, {A} {C}ase {S}tudy", author= "Jelly, I. E. and Morris, S. A.", editor= "Kerridge, Jon", pages = "41--53", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{DAvanzoPoli93, title = "{T}ransputer {B}ased {P}ipeline {M}achine and {I}ts {L}anguage in {N}uclear {P}hysics", author= "D'Avanzo, B. and Poli, M. De and Maron, G. and Mazza, M. L. and Scanferlato, S. and Staiano, G. and Tang, X. N. and Vedovato, G.", editor= "Kerridge, Jon", pages = "54--65", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{Morse93, title = "{S}patial {S}imulation {M}odelling of {I}nsect {P}opulation {D}ynamics on a {T}ransputer {N}etwork", author= "Morse, D. R.", editor= "Kerridge, Jon", pages = "66--75", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{Goodeve93, title = "{M}apping {R}evisited", author= "Goodeve, D.", editor= "Kerridge, Jon", pages = "76--90", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{NaimTeruel93, title = "{ANDES}: {A} {P}erformance {A}nalyzer for {P}arallel {P}rograms", author= "Naim, O. and Teruel, A.", editor= "Kerridge, Jon", pages = "91--99", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{CachiaManson93, title = "{CCDM} -- {A} {D}esign {M}ethodology for {M}odelling {C}ommunicating {C}ode in {P}arallel {S}ystems", author= "Cachia, E. A. and Manson, Gordon A.", editor= "Kerridge, Jon", pages = "100--114", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{CaoVel93, title = "{S}upporting a {R}apid {P}rototyping {S}ystem for {D}istributed {A}lgorithms on a {T}ransputer {N}etwork", author= "Cao, J. and Vel, O. de and Wong, Adam K. L.", editor= "Kerridge, Jon", pages = "115--130", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{NixonCroll93, title = "{T}he {F}unctional {S}pecification of {OCCAM} {P}rograms for {T}ime {C}ritical {A}pplications", author= "Nixon, Patrick and Croll, Peter R.", editor= "Kerridge, Jon", pages = "131--144", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{RaoBacon93, title = "{A} {C}oncurrent {A}lgorithm for the {R}econstruction of {N}uclear {M}agnetic {R}esonance {S}canner {I}mages", author= "Rao, D. R. K. and Bacon, R. A.", editor= "Kerridge, Jon", pages = "145--154", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{SheaCheung93, title = "{A} {T}echnique for {F}ast {P}re-emptions in a {M}ulti-{P}riority {E}nvironment", author= "Shea, K. M. and Cheung, M. H. and Lau, Francis C. M.", editor= "Kerridge, Jon", pages = "155--166", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{AraujoRuz93, title = "{P}arallel {E}xecution of {P}rolog on a {T}ransputer-{B}ased {N}etwork", author= "Araujo, L. and Ruz, J. J.", editor= "Kerridge, Jon", pages = "167--181", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{PietroVillano93, title = "{G}lobal {T}ime {M}easurements in {T}ransputer {N}etworks", author= "Pietro, Giuseppe de and Villano, Umberto", editor= "Kerridge, Jon", pages = "182--195", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{NettoGathy93, title = "{T}ransputer {B}ased {A}rchitecture for {R}obot {C}ontrol", author= "Netto, J. and Gathy, L. and Campion, G. and Trullemans, C.", editor= "Kerridge, Jon", pages = "196--208", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{Barrett93, title = "{H}ow {T}o {W}rite a {H}ighly {P}arallel {P}rogram", author= "Barrett, Geoff", editor= "Kerridge, Jon", pages = "209--217", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{StallardDunn93, title = "{D}ynamic {R}eal-{T}ime {S}cheduling for a {P}arallel {P}roduction {S}ystem on an {E}nhanced {T}ransputer {A}rray", author= "Stallard, P. W. A. and Dunn, R. W. and Daniels, A. R.", editor= "Kerridge, Jon", pages = "218--231", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{WaitheKerridge93, title = "{A}n {A}ppreciation of the {S}ubtleties of {S}hared {C}hannels in occam3", author= "Waithe, S. W. and Kerridge, Jon", editor= "Kerridge, Jon", pages = "232--245", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{Spahn93, title = "{V}ision {S}imulation on {D}istributed {S}ystems", author= "Spahn, C-M.", editor= "Kerridge, Jon", pages = "246--252", booktitle= "{P}roceedings of {W}o{TUG}-16: {T}ransputer and {O}ccam {R}esearch : {N}ew {D}irections", isbn= "90 5199 121 5", year= "1993", } @InProceedings{Kerridge94, title = "{D}ynamic {A}llocation of {P}rcesses and {C}hannels in {T}9000/{C}104 {N}etworks {U}sing occam 3", author= "Kerridge, Jon", editor= "Miles, Roger and Chalmers, Alan G.", pages = "1--17", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{PloegSunter94, title = "{D}edicated {M}ulti-{P}riority {S}cheduling", author= "Ploeg, E. and Sunter, Johan P. E. and Bakkers, Andr\`{e} W. P. and Roebbers, Herman", editor= "Miles, Roger and Chalmers, Alan G.", pages = "18--31", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{BattersbyEdwards94, title = "{A} {P}arallel {A}rchitecture for {E}fficient {C}lash {D}etection", author= "Battersby, A. and Edwards, Janet", editor= "Miles, Roger and Chalmers, Alan G.", pages = "32--39", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{DebbageHill94, title = "{S}outhampton's {P}ortable {O}ccam {C}ompiler ({SPOC})", author= "Debbage, Mark and Hill, Mark and Wykes, S. and Nicole, Denis A.", editor= "Miles, Roger and Chalmers, Alan G.", pages = "40--55", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{ElamvazutManson94, title = "{O}ccam, {PVM} and the {A}lternative {C}onstruct", author= "Elamvazuthi, Chandran and Manson, Gordon A.", editor= "Miles, Roger and Chalmers, Alan G.", pages = "56--68", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{MacaulayStringer94, title = "{O}bject {O}rientated {V}ersion {M}anagement on {A} {T}ransputer-{B}ased {A}rchitecture", author= "Macaulay, W. T. and Stringer, K. S.", editor= "Miles, Roger and Chalmers, Alan G.", pages = "69--76", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{MazzeoMazzocca94, title = "{E}fficiency {M}easurements in {H}eterogeneous {T}ransputer {S}ystems", author= "Mazzeo, A. and Mazzocca, N. and Villano, Umberto", editor= "Miles, Roger and Chalmers, Alan G.", pages = "77--86", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{StorerMilford94, title = "{D}eveloping {E}mbedded {A}ppliations in an {A}rray of {S}pecialised {T}ransputer {M}odules", author= "Storer, R. and Milford, D. J. and Dagless, E. L. and Bulas\~{}Cruz, J. A.", editor= "Miles, Roger and Chalmers, Alan G.", pages = "98--112", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{Waithe94, title = "{T}he {I}mplementation of a {S}calable {M}assively {P}arallel {C}oncurrency {C}ontrol {A}rchitecture", author= "Waithe, S. W.", editor= "Miles, Roger and Chalmers, Alan G.", pages = "113--127", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{BattersbySillitoe94, title = "{A}n {MSDOS} {B}ased {G}raphics {L}ibrary for {PC} {H}osted {T}ransputer {S}ystems", author= "Battersby, A. and Sillitoe, Ian P. W. and Edwards, Janet", editor= "Miles, Roger and Chalmers, Alan G.", pages = "128--138", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{TidmusChalmers94, title = "{D}istributed {M}onte {C}arlo {T}echniques for {I}nteractive {P}hoto-{R}ealistic {I}mage {S}ynthesis", author= "Tidmus, Jonathan and Chalmers, Alan G. and Miles, Roger", editor= "Miles, Roger and Chalmers, Alan G.", pages = "139--147", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{PhillipsParish94, title = "{O}n the {U}se of {T}ransputers in a {M}ultimedia {T}eleconferencing {S}ystem", author= "Phillips, Iain and Parish, D.", editor= "Miles, Roger and Chalmers, Alan G.", pages = "148--154", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{JelemenskHudec94, title = "{T}he {Q}uadruple {A}pproach in {F}ault-{T}olerant {T}ransputer {S}ystem {D}esign", author= "Jelemenska, K. and Hudec, L.", editor= "Miles, Roger and Chalmers, Alan G.", pages = "155--163", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{Nixon94, title = "{S}upporting the {P}rototyping of {T}ransputer {B}ased {F}ault {T}olerant {S}ystems", author= "Nixon, Patrick", editor= "Miles, Roger and Chalmers, Alan G.", pages = "164--174", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{B\"{o}ckmannGiese94, title = "{P}roviding {CSP}-{L}ike {F}unctionality in a {H}elios {E}nvironment", author= "B\"{o}ckmann, P. and Giese, H. and Wirtz, G.", editor= "Miles, Roger and Chalmers, Alan G.", pages = "175--189", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{Page94, title = "{A}utomatic {D}esign and {I}mplementation of {M}icroprocessors", author= "Page, Ian", editor= "Miles, Roger and Chalmers, Alan G.", pages = "190--204", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{AroujoRuz94, title = "{A} {T}ransputer-{B}ased {P}rolog {D}istributed {P}rocessor", author= "Aroujo, L. and Ruz, J. J.", editor= "Miles, Roger and Chalmers, Alan G.", pages = "190--204", booktitle= "{P}roceedings of {W}o{TUG}-17: {P}rogress in {T}ransputer and {O}ccam {R}esearch", isbn= "90 5199 163 0", year= "1994", month= "mar", } @InProceedings{Fletcher95, title = "{A} transputer implementation of a runtime timing constraint-monitor", author= "Fletcher, Fergus E.", editor= "Nixon, Patrick", pages = "1--15", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "A transputer implementation of a runtime constraint monitor is described. This monitor -- Sentinel -- uses Real-Time Logic (RTL) for specifying a program's timing constraints. Sentinel is a variant of an existing centralised uniprocessor monitor. In Sentinel," } @InProceedings{PilletLabarta95, title = "{PARAVER}: {A} {T}ool to {V}isualize and {A}nalyze {P}arallel {C}ode", author= "Pillet, V. and Labarta, J. and Cortes, T. and Girona, S.", editor= "Nixon, Patrick", pages = "17--31", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "PARAVER (PARallel Visualization and Events Representation) is a tool to visualize and analyze a parallel trace file. PARAVER can be used in two different ways: Creating its own trace file in accordance with the PARAVER trace format, or using a modified PVM library. PARAVER is based on a simple interface to manage several displaying windows. In fact, PARAVER can be seen as a tape recorder where the trace file is the tape. PARAVER provides many functionalities to see and analyze qualitatively the trace file. Moreover, the user can add his own analysis function to extend the functionality of the tool. This paper discusses the basic concept, design and use of PARAVER. We explain in detail each window. The different functionalities of PARAVER are also examined. Finally we present the future directions of our research." } @InProceedings{Hill95, title = "{P}arallel {I}mperative {F}unctional {P}rogramming", author= "Hill, Steve", editor= "Nixon, Patrick", pages = "33--46", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", } @InProceedings{Cook95, title = "{A} fast {C} {K}ernel for {P}ortable occam {C}ompilers", author= "Cook, Barry M.", editor= "Nixon, Patrick", pages = "47--65", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "This paper describes an experiment in providing explicitly parallel constructs in the style of occam within a functional programming environment. The work is based upon the monadic style proposed and described by Moggi, Wadler, Peyton Jones and others. The approach is pragmatic and conservative in that parallelism is treated as an imperative feature implemented by monadic functions. Overloading is used to provide a class of channel protocols. As in occam, data transmitted over a channel is fully evaluated and must be of ground type. An algorithm for checking channel usage in the presence of dynamic process and channel creation is described. The work can be described as an extension of functional notations allowing for explicit imperative-style parallelism. Alternatively, one could view it as extending the vocabulary of the occam language to allow for recursion, higher-order constructions and dynamic process and channel creation." } @InProceedings{RothwellShaw95, title = "{P}orting the {INMOS} occam {C}ompiler to the {SPARC} {A}rchitecture", author= "Rothwell, K. and Shaw, G. and Smith, A", editor= "Nixon, Patrick", pages = "67--74", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "occam is a relatively uncomplicated programming language designed to efficiently program parallel computer systems. It is not tied to a particular architecture but until recently has only been available for the transputer range of microprocessors. This paper describes a port of the standard INMOS occam 2 toolset Transputer compiler to the Sun SPARC architecture." } @InProceedings{BurgessChalmers95, title = "{O}ptimum {T}ransputer {C}onfigurations for {R}eal {A}pplications {R}equiring {G}lobal {C}ommunication", author= "Burgess, Colin J. and Chalmers, Alan G.", editor= "Nixon, Patrick", pages = "75--85", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "If complex problems are to be solved in reasonable computation times, then large scale parallel processing is necessary. For many of these problems, the density of the global communications dominated the performance of the parallel implementation. In these cases, the design of the interconnection network for the processors is known to play a significant part in the efficient implementation of problems on a large T800 transputer systems. This paper presents a new genetic algorithm for generating optimal configurations, augmented by simulated annealing for selected refinement of difficult cases. These configurations have the further advantage that they satisfy the best known criteria for producing configurations that perform well on real applications. The paper concludes by describing the impact this might have on the design of future T9000 transputer configurations." } @InProceedings{BiriukovUlyanov95, title = "{P}arallel application development with dynamo", author= "Biriukov, A. and Ulyanov, D.", editor= "Nixon, Patrick", pages = "87--95", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "An approach to the development of parallel applications for the distributed memory computers based on the notion of configuration is presented. The configuration introduces a general context for the problems such as source program optimization, load balancing, mapping, processor network development. The paper contains the experimental results obtained with the DYNAMO system based on this approach." } @InProceedings{GreenMorgan95, title = "{P}arallelisation for the progressive refinement radiosity method for the synthesis of realistic images", author= "Green, Peter and Morgan, Ed", editor= "Nixon, Patrick", pages = "97--112", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "This paper discusses strategies for parallelising the radiosity method for image synthesis applicable to message passing architectures, in particular, transputer-based machines. The basic radiosity method, and a number of its developments are reviewed, as are previous parallelisation schemes. A number of parallelisation strategies are then discussed, with emphasis being placed on techniques for maximising the efficiency of the schemes by reducing communications overheads, scene structuring and scene partitioning. Results from the implementation of the various parallelisation approaches on a transputer-based Meiko Computing Surface are presented. The implications of the parallelisation strategies in terms of solution quality are also considered." } @InProceedings{AnandShapcott95, title = "{D}ata {M}ining in {P}arallel", author= "Anand, Sarabjot S. and Shapcott, C. Mary and Bell, David A. and Hughes, John G.", editor= "Nixon, Patrick", pages = "113--124", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "In this paper we discuss the efficient implementation of the STRIP (Strong Rule Induction in Parallel) algorithm in parallel using a transputer network. Strong rules are rules that are almost always correct. We show that STRIP is well suited for parallel implementation with scope at four different levels for the transputer network using different number of transputers. The choice of certain variables (the number and size of samples) in the STRIP algorithm affects the performance (speedup and efficiency) of the implementation." } @InProceedings{DouglasWood95, title = "{L}inda implementation revisted", author= "Douglas, Andrew and Wood, Alan and Rowstron, Antony", editor= "Nixon, Patrick", pages = "125--138", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "Linda is a model for communication and co-ordination of parallel processes. The model provides a virtual shared memory called tuple space, and primitives to place tuples into and remove tuples from tuple space. The style of programming provided by Linda is quite different to the style of, say, occam. We describe a new implementation of Linda across a network of transputers. We provide the four Linda primitives, in, out, rd and eval, together with a new primitive, collect, developed at York. The implementation focusses on two issues. The first issue is that the ordering of out operations in a sequential process must be preserved if we want Linda to act as a co-ordination language. Our implementation provides this. The second issue is the implementation of eval, Linda's mechanism for spawning processes. We outline an implementation which provides arbitrary spawning of processes which execute concurrently, despite the restriction, enforced by the transputer architecture, of declaring a static number of processes at compile time. We provide a small example to show how Linda can be used to write parallel programs, then outline current work being undertaken at York, which focusses on interpretive environments for high level parallel programming techniques. A prototype Linda implementation and ISETL interpreter have already been developed." } @InProceedings{TokhiHossain95, title = "{R}eal-time {P}erformance {E}valuation {I}ssues for {T}ransputer {N}etworks", author= "Tokhi, M. and Hossain, M. and Baxter, M. and Fleming, P. J.", editor= "Nixon, Patrick", pages = "139--150", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "This paper presents an investigation into the critical issues involved in real-time performance evaluation of a transputer network. Issues such as algorithm partitioning, mapping, inter-processor communication, granularity, regularity and compilers efficiency for numerical computation are investigated and presented in this chapter. A finite difference simulation algorithm for a flexible beam in transverse vibration evaluation is made, demonstrating fast processing techniques for real-time implementations." } @InProceedings{Poole95, title = "{U}sing records and pointers with occam 2.5", author= "Poole, Michael D.", editor= "Nixon, Patrick", pages = "151--162", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "The language extensions from occam 2 to occam 2.1 are introduced. A programming project using the language is described. Specific examples of the use of the new named types and record structures including pointers, are described. Some specific and general conclusions are drawn." } @InProceedings{SahibManson95, title = "{M}apping {PCSC} {D}esign {M}odel to {I}nmos {ANSI} {C}", author= "Sahib, S. and Manson, Gordon A.", editor= "Nixon, Patrick", pages = "163--181", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "A methodology for parallel system design called Parallel Communicating Sequential Code (PCSC) is currently being developed. A CASE tool based on this methodology is also being built which automatically generates C code for the PVM environment. Work is currently being carried out to extend the code generator to automatically generate C code for the Inmos toolset. This paper discusses the mapping of the PCSC design model onto Inmos Ansi C to make the automatic code generation possible. Where relevant, comparisons are made with respect to the C-PVM implementation." } @InProceedings{CrollGriffiths95, title = "{M}odelling {R}eal-{T}ime {B}ehaviour of {P}arallel {T}ransputer {S}ystems under {F}ailure {C}onditions", author= "Croll, Peter R. and Griffiths, P. M.", editor= "Nixon, Patrick", pages = "183--195", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "This paper describes work concerning the modelling of transputer The aims and problems of designing real-time systems are introduced. The key features of the model which are relevant to reliability are discussed. Algorithms for scheduling parallel and mono-processor real-time system are explained. Coloured Petri-nets in general are introduced, and then the key features of the CASE tool Design/CPN are covered. Details of how the model has been implemented, and how the model behaves are given. Conclusions from the work so far are presented, and the outstanding areas of work are discussed." } @InProceedings{Hazra95, title = "{A}pplication of {T}ransputer-based {P}arallel {C}omputation in {M}atching {R}eal-{T}ime {C}ontrol {M}odels", author= "Hazra, Tushar K.", editor= "Nixon, Patrick", pages = "197--212", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "Mathematical models describing physical processes can be 'matched' to discrete samples of processes by considering measured input-output data and adjusting coefficient parameters of the model to provide an optimal agreement between the system and model responses. This well known technique has been widely implemented in an off-line basis for many years. The process of matching can be based on standard optimization procedures such as Davidon Fletcher Powell, Fletcher Reeves or even simply Newton Raphson methods. Standard simulation routines such as Runge Kutta or Euler's methods can be used to generate the model responses. However, the procedure for model matching involves intensive computing. This paper offers a number of prospective approaches to the solution based on parallel computing methodologies. Using standardized model matching experiments and simulated noise-free data, performance comparisons for sequential and multiprocessor computations have been evaluated on a transputer-based system." } @InProceedings{ElamvazutManson95, title = "{I}ncorporating {U}se-{C}ase {A}nalysis in {PCSC} {M}ethod", author= "Elamvazuthi, Chandran and Manson, Gordon A.", editor= "Nixon, Patrick", pages = "213--226", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "Use-case analysis is a simple but useful technique for driving the process of analysis in a meaningful manner. It is used, in one form or another, in various object-orientated software development methods notably OOSE, Booch and OMT. In this paper, we explain how use-case analysis has been incorporated into PCSC, a method based on the occam model for developing parallel software systems. To illustrate the usage of use-case analysis in PCSC, we present a simple case study of a Character Sorting System." } @InProceedings{HuangMorgan95, title = "{A} {D}istributed {I}/{O} {C}ommunication {P}rotocol for a {N}etwork of {T}ransputers", author= "Huang, Runhe and Morgan, Mike", editor= "Nixon, Patrick", pages = "227--237", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "This paper describes an asynchronous communication protocol for an embedded network of transputer I/O devices. The aim of the protocol was to allow a message routing infrastructure small enough to fit withing the internal memory of the inexpensize T2 transputer range and yet be flexible enough to cater for all control and message routing requirements of a complex assembly machine. It was also a requirement that the network was scalable without the need to recompile the source code." } @InProceedings{Rabhi95, title = "{A} {P}arallel {P}rogramming {M}ethodology {B}ased on {P}aradigms", author= "Rabhi, Fethi A.", editor= "Nixon, Patrick", pages = "239--251", booktitle= "{P}roceedings of {W}o{TUG}-18: {T}ransputer and occam {D}evelopments", isbn= "90 5199 222 X", year= "1995", month= "mar", abstract= "Todays efforts are mainly concentrated on providing \"standard\" parallel languages to ensure the portability of programs across various architectures. It is now believed that the next level of abstraction that will be addresses is the application level. This paper argues that there is an intermediate level that consists of common parallel programming paradigms. It describes some of these paradigms and explains the basic principles behind a \"paradigm-orientated\" programming approach. Finally, it points to future directions which can make it feasable to build CASE tools that achieveautomatic parallel code generation." } @InProceedings{Walker96, title = "{H}ardware for {T}ransputing without {T}ransputers", author= "Walker, C. P. H.", editor= "O'Neill, Brian C.", pages = "1--10", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{HarrisonBrown96, title = "{D}ynamic {C}reation of {V}irtual {L}inks within {T}9000 {N}etworks", author= "Harrison, S. R. and Brown, Chris R.", editor= "O'Neill, Brian C.", pages = "11--20", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{LakkisJ96, title = "{I}nterconnecting {R}emote {LAN}s via {P}ublic {D}ata {N}etworks by {H}igh {P}erformance {P}arallel {R}outers", author= "Lakkis, A. and J, L Jacquemin and Dumas, M.", editor= "O'Neill, Brian C.", pages = "21--36", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{CravenCurtis96, title = "{C}onflict {F}ree {H}ardware {R}outing for {C}ommunication {B}ound {A}pplications", author= "Craven, M. P. and Curtis, K. M. and Wilde, S. A. and O'Neill, Brian C. and Ellis, J. W.", editor= "O'Neill, Brian C.", pages = "37--50", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{Matic96, title = "{D}esign and {I}mplementation of {C}omplex {T}elecom {P}rocesses using {S}tate {M}achine {C}oncepts", author= "Matic, V.", editor= "O'Neill, Brian C.", pages = "51--58", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{BeckettWelch96, title = "{E}mulating a {S}ecure {M}ulticasting {B}us using occam 2.1", author= "Beckett, David J. and Welch, Peter H.", editor= "O'Neill, Brian C.", pages = "59--74", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{KuklaKerridge96, title = "{A} {P}lug-in {D}isk-{I}nterface {P}rocess for the {WSQL} {D}ata {A}ccess {C}ontroller", author= "Kukla, R. and Kerridge, Jon", editor= "O'Neill, Brian C.", pages = "75--88", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{CookPeel96, title = "{T}he {P}ara-{PC}, {A}n {A}nalysis", author= "Cook, Barry M. and Peel, Roger M. A.", editor= "O'Neill, Brian C.", pages = "89--102", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{Mourney96, title = "{P}arallel {S}olution of {L}inear {ODE}s. {I}mplementation on {T}ransputer {N}etworks", author= "Mourney, G.", editor= "O'Neill, Brian C.", pages = "103--112", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{Chalmers96, title = "{M}emory {M}anagement {S}trategies for {P}arallel {V}olume {R}endering", author= "Chalmers, Alan G.", editor= "O'Neill, Brian C.", pages = "113--126", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{LeclercqFaure96, title = "{G}aussian {P}yramidal {F}ast {F}iltering and {P}arallel {I}mplementation", author= "Leclercq, N. Tonfack E. and Faure, A.", editor= "O'Neill, Brian C.", pages = "127--142", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{WoodWelch96, title = "{T}he {K}ent {R}etargettable occam {C}ompiler", author= "Wood, David C. and Welch, Peter H.", editor= "O'Neill, Brian C.", pages = "143--166", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", abstract= "A generic approach to targeting occam to non-transputer architectures is described. The principle is to build a register-level emulation of the major design elements of the transputer, using native registers of the target hardware, and reuse the standard occam toolset compiler with as little alteration as possible. The porting effort thus reduces to an architectural mapping rather than involvement in the compiler and code-generator. An immediate payoff comes from reuse of a well-developed and sophisticated compiler. An important scientific question, with relevance to efficient and portable parallel computing, is whether the crucial benefits of transputer architecture (such as the very low overheads for the management of processes and events) can be transferred through such emulation. We report some initial results for SPARC-based targets." } @InProceedings{Poole96, title = "{O}ccam for all - {T}wo {A}pproaches to {R}etargetting the {INMOS} {C}ompiler", author= "Poole, Michael D.", editor= "O'Neill, Brian C.", pages = "167--178", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{BakkersOtten96, title = "{I}mplementation of {KR}o{C} on {A}nalog {D}evices \"{SHARC}\" {DSP}", author= "Bakkers, Andr\`{e} W. P. and Otten, G. W. and Schwirtz, M. H. and Bruis, R. and Broenink, Jan F.", editor= "O'Neill, Brian C.", pages = "179--190", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", abstract= "This paper summarises the experiences gained at the Control Laboratory of the University of Twente in porting the Kent Retargetable occam Compiler - KroC - to the Analog Devices’ ADSP21060 SHARC Digital Signal Processor. The choice of porting the KRoC to the DSP processor was in our view both a challenge and an absolute necessity because DSP processors are an important ingredient in modern day control systems. Currently, our implementation contains the most important occam primitives such as channel communication, PAR, ALT, and most of the integer arithmatic. Furthermore, a basic kernel was realised, providing channel-communication based scheduling only. This porting process, using quite straight-forward modifications of the SPARC KRoC-translator, was done within six weeks. A representative benchmark was constructed, showing that the 33Mhz SHARC-KRoC implementation is 40\% faster than the the 25Mhz T800 using the INMOS D7205 Toolset." } @InProceedings{NicoleSivaram96, title = "{SCOTT}: {T}he {S}outhampton {COFF} {T}ools for {T}ransputers", author= "Nicole, Denis A. and Sivaram, R.", editor= "O'Neill, Brian C.", pages = "191--206", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{StoneMorse96, title = "{A} {S}oftware {D}evelopment {T}ool for {P}arallel and {D}istributed {S}ystems", author= "Stone, R. D. and Morse, D. R.", editor= "O'Neill, Brian C.", pages = "207--220", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{RodriguezAlmeida96, title = "{T}he {S}ingle {R}esource {A}llocation {P}roblem: {P}arallel {A}lgorithms on {D}istributed {S}ystems", author= "Rodriguez, C. and Almeida, F. and Morales, D. and Roda, J. L. and Garcia, F.", editor= "O'Neill, Brian C.", pages = "221--232", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{ClaytonWells96, title = "{A}n {E}xtended {V}ersion of {L}inda for {T}ransputer {S}ystems", author= "Clayton, Peter and Wells, George and Chalmers, Alan G.", editor= "O'Neill, Brian C.", pages = "233--240", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{Beton96, title = "{F}rom {O}bject {O}riented {A}nalysis to {I}mplementation using occam", author= "Beton, Rick D.", editor= "O'Neill, Brian C.", pages = "241--254", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{SingletonCook96, title = "{T}he {G}lobalisation of occam", author= "Singleton, Paul and Cook, Barry M.", editor= "O'Neill, Brian C.", pages = "255--270", booktitle= "{P}roceedings of {W}o{TUG}-19: {P}arallel {P}rocessing {D}evelopments", isbn= "90 5199 261 0", year= "1996", month= "feb", } @InProceedings{MartinJassim97a, title = "{A} {T}ool for {P}roving {D}eadlock {F}reedom", author= "Martin, Jeremy M. R. and Jassim, S. A.", editor= "Bakkers, Andr\`{e} W. P.", pages = "1--16", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "We describe a tool, programmed in Java, for the formal verification of the absence of deadlock and livelock in networks of CSP processes. The innovative techniques used scale well to very large networks, unlike the exhaustive state checking method employed by existing tools." } @InProceedings{Delft97, title = "{S}criptic: {P}arallel {P}rogramming in {E}xtended {J}ava", author= "Delft, Andr\`{e} van", editor= "Bakkers, Andr\`{e} W. P.", pages = "17--33", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "Scriptic is an expression based extension to the Java programming language, targeted at user interfaces, simulations and parallel computing on shared memory systems. The extras are mainly founded on the theory of Process Algebra: constructs for non-deterministic choice, parallelism and communica-tion. By default, these parallel constructs have interleaving seman-tics, rather than multi-threading or forking. Specific Java code fragments may run in their own threads or handle events from the windowing system. This makes interactive applications such as arcade games execute as fast as corresponding plain Java versions. GUI components such as buttons and menu items are enabled and disabled when applicable, without additional programming. This paper covers an example application in Scriptic, an overview of the language constructs, the implementation, originality, previous work and current work." } @InProceedings{Demaine97, title = "{H}igher-{O}rder {C}oncurrency in {J}ava", author= "Demaine, Erik D.", editor= "Bakkers, Andr\`{e} W. P.", pages = "34--47", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "In this paper we examine an extension to Hoare's Communicating Sequential Processes model called higher-order concurrency, proposed by Reppy. In this extension, communication algorithms (or events) are first-class objects and can be created and manipulated dynamically. In addition, threads are automatically garbage collected and channels are first-class, that is, they can be passed over other channels. We describe the design of a Java package that implements the main features of higher-order concurrency, with similar ease-of-use to Reppy's Concurrent ML system. Our implementation can be easily extended to use a distributed system, which is a major limitation with Concurrent ML. We also hope to bring the idea of higher-order concurrency to a wider audience, since it is extremely powerful and flexible, but currently only well known to the programming-languages community." } @InProceedings{HilderinkBroenink97, title = "{C}ommunicating {J}ava {T}hreads", author= "Hilderink, Gerald H. and Broenink, Jan F. and Vervoort, Wiek and Bakkers, Andr\`{e} W. P.", editor= "Bakkers, Andr\`{e} W. P.", pages = "48--76", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "The incorporation of multithreading in Java may be considered as a significant part of the Java language, because it provides rudimentary facilities for concurrent programming. However, we belief that the use of channels is a fundamental concept for concurrent programming. The channel approach as described in this paper is a realization of a systematic design method for concurrent programming in Java based on the CSP paradigm. CSP requires the availability of a Channel class and the addition of composition constructs for sequential, parallel and alternative processes. The Channel class and the constructs have been implemented in Java in compliance with the definitions in CSP. As a result, implementing communication between processes is facilitated, the programmer can avoid deadlock more easily, and the programmer is freed from synchronization and scheduling constructs. The use of the Channel class and the additional constructs is illustrated in a simple application." } @InProceedings{Verhulst97, title = "{B}eyond transputing : fully distributed semantics in {V}irtuoso's {V}irtual {S}ingle {P}rocessor programming model and it's implementation on of-the-shelf parallel {DSP}s.", author= "Verhulst, Eric", editor= "Bakkers, Andr\`{e} W. P.", pages = "77--86", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "Virtuoso Classico /VSP is a fully distributed real-time operating system originally developed on the INMOS transputer. Its generic architecture is based on a small but very fast nanokernel and a portable preemptive microkernel. It was further on ported in single and virtual single processor implementations to a wide range of processors. As the basis of any real-time application is a scheduler that allows the developer to use the minimum schedule to satisfy the real-time requirements, a number of derived Virtuoso tools have been developed with complementary functionalities. This paper describes the rationale for developing the distributed semantics of Virtuoso's microkernel and describes some of the implementation issues. The analysis is based on the parallel DSP implementations as these push the performance limits most for hard real-time applications. The Virtuoso tools are being ported and further developed in the DIPSAP-II and EURICO OMI/Esprit projects." } @InProceedings{Gook97, title = "{R}econfigurable {C}omputing", author= "Gook, Roger", editor= "Bakkers, Andr\`{e} W. P.", pages = "87--87", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "The name may be familiar of old to the WoTUG community, but it has now been adopted by one of the fastest growing sectors of the silicon industry. Reconfigurable Computers are computing systems whose hardware architecture can be modified by software to suit the application at hand. The core component is the FPGA. Remarkable performance gains are achieved by placing an algorithm in an FPGA for embedded applications, compared with using a microprocessor or DSP. This is because an FPGA takes advantage of hardware parallelism while reducing the timing overheads needed for general-purpose microprocessor applications. For example the time taken by load/store operations and instruction decoding can be eliminated. Reconfiguration enables the FPGA to provide a problem specific computer for highly optimised application performance. Just as high level programming languages liberated the first microprocessors programming languages will liberate the FPGA. The first of these languages to become commercially available is Handel-C. Handel-C is based on the CSP Model; it was developed by the Hardware Compilation Group at the University of Oxford and is to be marketed by ESL. The Handel-C tools enable a software engineer to target directly FPGAs in a similar fashion to classical microprocessor cross-compiler development tools, without recourse to a Hardware Description Language. Thereby allowing the software engineer to directly realise the raw real-time processing capability of the FPGA. The skills and expertise gained by the WoTUG, provide the group with a competitive advantage to develop the innovative algorithms, applications and products in this domain." } @InProceedings{SingletonCook97, title = "{A}n {O}pen {S}ystems {S}trategy for {D}istributed occam {E}xecution", author= "Singleton, Paul and Cook, Barry M.", editor= "Bakkers, Andr\`{e} W. P.", pages = "88--103", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "We demonstrate the feasibility of distributed execution of occam programs within computer networks which support open systems standards for inter-process communication, remote execution and program hosting (e.g. hardware-independent programming languages and operating-system-independent APIs). We first propose a general architecture, and then describe a constructive proof of its viability (i.e. a prototype). which uses a novel multiplexed virtual channel protocol over UNIX sockets. Finally we summarise some of the opportunities for further development which this project has created." } @InProceedings{WelchWood97, title = "{H}igher {L}evels of {P}rocess {S}ynchronisation", author= "Welch, Peter H. and Wood, David C.", editor= "Bakkers, Andr\`{e} W. P.", pages = "104--129", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "Four new synchronisation primitives (SEMAPHOREs, RESOURCEs, EVENTs and BUCKETs) were introduced in the KRoC 0.8beta release of occam for SPARC (SunOS/Solaris) and Alpha (OSF/1) UNIX workstations. This paper reports on the rationale, application and implementation of two of these (SEMAPHOREs and EVENTs). Details on the other two may be found on the web. The new primitives are designed to support higher-level mechanisms of SHARING between parallel processes and give us greater powers of expression. They will also let greater levels of concurrency be safely exploited from future parallel architectures, such as those providing (virtual) shared-memory. They demonstrate that occam is neutral in any debate between the merits of message-passing versus shared-memory parallelism, enabling applications to take advantage of whichever paradigm (or mixture of paradigms) is the most appropriate. The new primitives could be (but are not) implemented in terms of traditional channels, but only at the expense of increased complexity and computational overhead. The primitives are immediately useful even for uni-processors -- for example, the cost of a fair ALT can be reduced from O(n) to O(1). In fact, all the operations associated with new primitives have constant space and time complexities; and the constants are very low. The KRoC release provides an Abstract Data Type interface to the primitives. However, direct use of such mechanisms still allows the user to misuse them. They must be used in the ways prescribed below else else their semantics become unpredictable. No tool is provided to check correct usage at this level. The intention is to bind those primitives found to be useful into higher level versions of occam. Some of the primitives (e.g. SEMAPHOREs) may never themselves be made visible in the language, but may be used to implement bindings of higher-level paradigms (such as SHARED channels and BLACKBOARDs). The compiler will perform the relevant usage checking on all new language bindings, closing the security loopholes opened by raw use of the primitives. The paper closes by relating this work with the notions of virtual transputers, microcoded schedulers, object orientation and Java threads." } @InProceedings{TidmusMiles97, title = "{P}refetch {D}ata {M}anagement for {P}arallel {P}article {T}racing", author= "Tidmus, Jonathan and Miles, Roger and Chalmers, Alan G.", editor= "Bakkers, Andr\`{e} W. P.", pages = "130--137", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "The particle tracing method uses a stochastic approach for global illumination computation of three-dimensional environments. As with many graphics techniques the computation associated with the image generation is complex. Parallel processing offers the potential of solving the computational complex particle tracing more rapidly. Distributed memory parallel systems are scalable and readily available. However, large environmental models are often bigger than individual node storage capabilities requiring data management to distribute and control the movement of environmental data as computation proceeds. Prefetch data management attempts to reduce idle time associated with remote data fetches by anticipating the latency and requesting required data items prior to their actual use during computation. This paper demonstrates how attention to work division and supply coupled with prefetch data management can be utilised to minimise overheads associated with a parallel implementation and reduce overall image synthesis time." } @InProceedings{HarrisonBrown97, title = "{WEAVE}: {A} {S}ystem for {D}ynamic {C}onfiguration of {V}irtual {L}inks", author= "Harrison, S. R. and Brown, Chris R.", editor= "Bakkers, Andr\`{e} W. P.", pages = "138--151", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "This paper describes Weave, a system which has been developed to support the use of a DS Link (IEEE 1355) based parallel computer architecture. Weave is an extension layer on IIPC (a simple transputer and UNIX parallel processing environment which provides dynamic process management, hardware transparency and message passing.) Although Weave is suitable for any T9000 Transputer network, it has been specifically designed to support the use of the AIVRU DS Link Vision Engine. A brief description is given of this machine, which processes live digital video using a mixture of hardware modules and software processes, all interconnected by DS Links. Weave provides the ability to make virtual link connections between processes on demand at run-time. These connections may be disconnected when no longer required, and hence the whole hardware architecture is dynamically reconfigured automatically to suit the requirements of the software application. A small functional interface provides processes with the ability to alter their own connectivity, and that of other processes. A temporal locking mechanism for each virtual link controls when it may be disconnected, and when pending connection requests can be fulfilled. This locking mechanism is driven by the action of communication over the virtual link. The Weave system supports transparently, the creation and destruction of connections between software processes and the image processing hardware modules (and between hardware modules directly). Also provided transparently by Weave is support for the use of hardware message replicator module(s) that multicast virtual link data to any number of DS Link recipients." } @InProceedings{Cook97, title = "{D}ata-{S}trobe {L}inks and {V}irtual {C}hannel {P}rocessors", author= "Cook, Barry M.", editor= "Bakkers, Andr\`{e} W. P.", pages = "175--188", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "Data-strobe links and message transfer protocols as used by the SGS-Thomson T9000 processor are described, as are the essential characteristics of the supporting virtual channel processor. A method of providing the same functionality without the use of a T9000 is suggested and illustrated by a T225 processor design using a software virtual channel processor and minimal supporting hardware. Finally, differences between the international standard, IEEE 1355, and the T9000 links from which it was derived are described and the implications for virtual channel links highlighted." } @InProceedings{WelchPoole97, title = "occam for {M}ulti-{P}rocessor {DEC} {A}lphas", author= "Welch, Peter H. and Poole, Michael D.", editor= "Bakkers, Andr\`{e} W. P.", pages = "189--198", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "A multi-processor implementation of occam2.1 for interconnected DEC Alpha processors has been derived from the Kent Retargetable occam Compiler. Each Alpha processor is supported over a PCI bus by a T425 transputer, whose links complete the communications fabric. This paper reports on the software mechanisms for supporting these platforms from occam so that they appear just like any transputer system -- a collection of processing nodes connected by channels placed on links. Advantage was taken of a proprietary multi-threading kernel, supplied as part of 3L Parallel C/AXP, to support parallel inter-node communication. occam multi- processing is supported by the KRoC kernel running within one of the 3L threads. The performance of generated code and networked systems has been benchmarked, with particular care being taken to measure the interaction overheads between the Alpha and its communication fabric. An image analysis program was also used in the benchmarking as an example of a real multi-processor application." } @InProceedings{Kalinowsk97, title = "{A} tool for optimisation of program execution in dynamic topology systems", author= "Kalinowski, Tomasz", editor= "Bakkers, Andr\`{e} W. P.", pages = "199--209", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "In this paper, we present a tool for optimisation of execution of parallel programs in distributed memory multi-processor systems with dynamic interconnection networks. The programs are described as Directed Acyclic Graphs (DAGs). The tool allows to compare simulated execution times for different task scheduling heuristics, target system topologies and communication models. A list scheduling algorithm, which has been applied, accounts for dynamic changes of interconnection structure. We demonstrate the efficiency of dynamic networks by comparing schedules obtained for dynamic and fixed topology systems. We propose a method of validating simulation results in a target system composed of T9000 transputers. The method relies on comparison of simulation results with execution times of synthetic OCCAM applications in the target system. The comparison indicates that assumptions taken on program execution and system model hold in the system under investigation." } @InProceedings{SilvaPedroso97, title = "{T}he {D}esign of {JET}: {A} {J}ava {L}ibrary for {E}mbarrassingly {P}arallel {A}pplications", author= "Silva, Luis M. and Pedroso, Hern\^{a}ni and Silva, Jo\~{a}o Gabriel", editor= "Bakkers, Andr\`{e} W. P.", pages = "210--228", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "JET is a parallel virtual machine. It has a dynamic number of processors which may run different proprietary operating systems. The processors communicate through the slowest intercommunication network of the world, do not provide peak performance and in the overall the parallel machine can be a very unstable computing surface. In other words, JET uses the idle CPU cycles of computers that are connected to the Internet, being a really inexpensive supercomputer. This paper presents the design of a Java parallel library that provides support for the execution of embarrassingly parallel applications. It inherits the security, robustness and portability features of Java and includes support for fault-tolerance, scalability and high-performance through the use of parallelism." } @InProceedings{Tudruj97, title = "{F}ine-grained global control constructs for parallel programming environments", author= "Tudruj, Marek", editor= "Bakkers, Andr\`{e} W. P.", pages = "229--243", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "Problems of evolved control in fine-grained parallel programs in distributed memory systems are discussed in the paper. Global control constructs are proposed which logically bind program modules, assign them to worker processors and define the involved flow of control. Implementation methods are discussed which assume control flow processing decoupled from data processing inside executive modules. The proposed constructs are extensions of the OCCAM 2 language. They can be incorporated into an intermediate code generated by a parallel language compiler or can be used by a programmer to define control flow between fine-grained program modules assigned to different processors. Architectural requirements for efficient implementation of the proposed control constructs are discussed." } @InProceedings{RodriguezSande97, title = "{E}xpanding the {M}essage {P}assing {L}ibrary {M}odel with {N}ested {P}arallelism", author= "Rodriguez, C. and Sande, F. and Le\`{o}n, C. and Garcia, F.", editor= "Bakkers, Andr\`{e} W. P.", pages = "244--251", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "A synchronous extension to the library model for message passing (Inmos C, PVM, Parmacs, MPI, etc.) is presented. This extension, provides a comfortable expression of nested parallelism from inside the message passing model. Furthermore of being a valuable tool for the presentation and teaching of parallel algorithms, the computational results prove that an efficiency similar to or even better than the one obtained designing and implementing algorithms using the native language can be achieved." } @InProceedings{Sakellari97, title = "{C}ompile-{T}ime {T}echniques for {M}apping {L}oop {P}arallelism", author= "Sakellariou, R.", editor= "Bakkers, Andr\`{e} W. P.", pages = "244--251", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "A synchronous extension to the library model for message passing (Inmos C, PVM, Parmacs, MPI, etc.) is presented. This extension, provides a comfortable expression of nested parallelism from inside the message passing model. Furthermode of being a valuable tool for the presentation and teaching of parallel algorithms, the computation results prove that an efficiency similar to or even bettern tahn the one obtained designing and implementing algorithms using the native language can be achieved." } @InProceedings{SchrettneJelly97, title = "{D}ynamic {P}rocess {I}nteraction", author= "Schrettner, Lajos and Jelly, Innes", editor= "Bakkers, Andr\`{e} W. P.", pages = "261--273", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "This paper concerns with the design of a building block for parallel and distributed software systems. We start with a very common problem of process interaction and successively derive a building block that can be used to construct systems that are correct by construction. When copies of this building block are connected to each other in an arbitrary fashion, the resulting system is deadlock/livelock free. An application is outlined where this method was used. We also would like to stress that the method of successive refinements used in this paper seems to be a fruitful approach in the design of protocols." } @InProceedings{HaasThornley97, title = "{T}he {M}acram\`{e} 1024 {N}ode {S}witching {N}etwork", author= "Haas, S. and Thornley, D. A. and Zhu, M. and Dobinson, R. W. and Martin, B.", editor= "Bakkers, Andr\`{e} W. P.", pages = "274--281", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "To date, practical experience in constructing switching networks using IEEE 1355 technology has been confined to relatively small systems and there are no experimental results on how the performance of such systems will scale up to several hundred or even several thousand nodes. Some theoretical studies have been carried out for large networks of up to one thousand nodes for different topologies. We present results obtained on a large modular testbed using 100 Mbits/s point to point DS links. One thousand nodes will be interconnected by a switching fabric based on the 32 way STC104 packet switch. The system has been designed and constructed in a modular way to allow a variety of different network topologies to be investigated (Clos, grid, torus, etc.). Network throughput and latency are being studied for various traffic conditions as a function of the topology and network size. Results obtained with the current 656 node setup are presented." } @InProceedings{Welch97, title = "{J}ava {T}hreads in {L}ight of occam/{CSP} ({T}utorial)", author= "Welch, Peter H.", editor= "Bakkers, Andr\`{e} W. P.", pages = "282--282", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "Java provides support for parallel computing through a model that is built into the language itself. However, the designers of Java chose to be fairly conservative and settled for the contepts of threads and monitors. Monitors were developed by Tony Hoare in the early 1970s as a structued way of using semaphores to control access to shared resources. Hoare moved away from this, in the late 1970s, to develop the theory of Communicating Processes (CSP). One reason for this was that the semantics of monitors and threads are not WYSIWIG, so that designing robust parallel algorithms at this level is seriously hard. Fortunately, it is possible to introduce the CSP model into Java through sets of classes implemented on top of its monitor support. By restricting interaction between active Java objects to CSP synchronisation primitives, Jav thread semantics become compositional and systems with arbitrary levels of complexity become possible. Multi-threaded Web applets and distributed applications become simpler to design and implement, race hazards never occured, difficulties such as starvation, deadlock and livelock are easier to confront and overcome, and performance is no worse than that obtained from directly using the raw monitor primitives. The advantages of teaching parallelism in Java purely through the CSP class libraries will be discussed. (These libraries were developed jointly at Kent and Oxford Universities in the UK and the University of Twente in the Netherlands.)" } @InProceedings{Hilderink97, title = "{C}ommunicating {J}ava {T}hreads {R}eference {M}anual", author= "Hilderink, Gerald H.", editor= "Bakkers, Andr\`{e} W. P.", pages = "283--325", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "This document describes a csp package that contains the channel and composition classes in Java according to the CSP paradigm. The csp classes form a complete package that contains the necessary ingredients for concurrent programming with channels in Java. The channel and composition concepts are derived from CSp and are developed according to the object-oriented paradigm. There is a clear pattern of concerns by means of object-oriented techniques using inheritance, delegation, genericity , and polymorphism. This document is meant as a reference manual and gives background information about the realization of the csp classes. The use of the CSP channels in Java is illustrated by means of using building blocks." } @InProceedings{PatrickGreen97, title = "{A} {M}ultiprocessor {OCCAM} {D}evelopment {S}ystem for {UNIX} {N}etwork {C}lusters", author= "Patrick, D. G. and Green, P. R. and York, T. A.", editor= "Bakkers, Andr\`{e} W. P.", pages = "289--198", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "This paper describes the OCCNIX multiprocessor environment, that enables OCCAM program development and testing, on clusters of UNIX workstations. Linked binary level interpreters form a virtual Transputer network that uses the TCP/IP client-server model and provides hardware independent multiple platform access in a similar way to the recently released JAVA. Results show a single processor performance that is half that of an actual Transputer and a four-processor speedup of 0.78. The system also has the ability to run development tools such as the ISPY network debugger." } @InProceedings{MartinJassim97b, title = "{H}ow to {D}esign {D}eadlock-{F}ree {N}etworks {U}sing {CSP} and {V}erification {T}ools -- {A} {T}utorial {I}ntroduction", author= "Martin, Jeremy M. R. and Jassim, S. A.", editor= "Bakkers, Andr\`{e} W. P.", pages = "326--338", booktitle= "{P}roceedings of {W}o{TUG}-20: {P}arallel {P}rogramming and {J}ava", isbn= "90 5199 336 6", year= "1997", month= "mar", abstract= "The CSP language of C.A.R. Hoare originated as a blackboard mathematical notation for specifying and reasoning about parallel and distributed systems. More recently sophisticated tools have emerged which provide automated verification of CSP-specified systems. This has led to a tightening and standardisation of syntax. This paper outlines the syntax and semantics of CSp as it is now used and then describes how to design CSP networks, which are guaranteed to be free of deadlock, throught a succession of increasingly complex worked examples, making use of the verification tool Deadlock Checker." } @InProceedings{Teig98, title = "{PAR} and {STARTP} {T}ake the {T}anks", author= "Teig, Øyvind", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "1--18", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "The article describes how SPoC (Southampton Portable occam Compiler) has been used -- together with hand-written C -- in Autronica's new GL-100 radar-based fluid gauge. The final C-code is running on a Texas TMS320C32 DSP. Some 2600 lines of C code have been automatically translated from the occam sources. SPoC's non-preemptive scheduling filled our needs with a few exceptions. The main problem has been aligning occam 2 and ANSI-C data abstractions. A realtime system based on language support of high-level concurrency abstractions (as opposed to separate real-time kernel and use of library calls without direct language support) is soon to monitor worldwide charging and discharging of oil tankers." } @InProceedings{CoxNicole98, title = "{C}ommodity {H}igh {P}erformance {C}omputing at {C}ommodity {P}rices", author= "Cox, Simon J. and Nicole, Denis A. and Takeda, Kenji", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "19--26", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "The entry price of supercomputing has traditionally been very high. As processing elements, operating systems, and switch technology become cheap commodity parts, building a powerful supercomputer at a fraction of the price of a proprietrary system becomes realistic. We have recently purchased, in support of both our local and national collaborations, a dedicated computational cluster of eight DEC Alpha workstations. Each node has a 500MHz AXP 21164A processor with 256Mb memory running Windows NT 4.0 and cost under 6000 pounds. They are connected by 100Mb/s switched ethernet. In this paper we discuss some of the issues raised by our choice of processor, operating system and interconnection network. The results we present indicate that the cluster is fully competitive with systems from major vendors for a wide range of engineering and science applications, and at a lower cost by at least a factor of three. Indeed the only current area of under-performance relative to these vendors' high-end offerings is the inter-node network bandwidth and latency. We give some initial results indicating how the network performance might be improved under Windows NT." } @InProceedings{GreveSchwirtz98, title = "{A}n {A}/{D} {D}/{A} board using {IEEE}-1355 {DS}-{L}inks for {H}eterogeneous {M}ultiprocessor {E}nvironment", author= "Greve, O. J. and Schwirtz, M. H. and Hilderink, Gerald H. and Broenink, Jan F. and Bakkers, Andr\`{e} W. P.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "27--38", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "In our approach for developing heterogeneous control systems, we have developed a real-time A/D D/A board called \"the Raptor\". The Raptor communicates over high-speed and highly-reliable DS-links (IEEE-1355). To obtain highly accurate analogue conversions, the A/D and D/A converteds have a 12-bit resolution. We measured a maximum sampling frequency of 90.5kHz on each A/D channel. The maximum sampling frequency of each D/A channel has been measured to be approximately 145kHz. For communication with the rest of the control environment, two 100Mbit/s DS-links are available. A data transfer rate of 5.57Mbytes/s has been achieved on each DS-link adapter. The Raptor forms a part of a heterogeneous multiprocessor closed-loop control environment. This new environment can be used, amongst others, for controlling heavy robot applications. The work on this environment takes place in scope of JavaPP (Java Plug and Play) project. The software will be developed together with the CJT-library that provides inherent object-orientated and parallel design patterns, according to CSP paradigm, in Java." } @InProceedings{ONeillCoulson98, title = "{A} {D}istributed {P}arallel {P}rocessing {S}ystem for the {S}trong{ARM} {M}icroprocessor", author= "O'Neill, Brian C. and Coulson, G. C. and Wong, Adam K. L. and Hotchkiss, R. and Ng, J. H. and Clark, S. and Thomas, P. D. and Cawley, A.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "39--48", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "Recent developments in hardware message routing devices have demonstrated significant performance benefits for parallel processing networks. This work describes a system which uses a single chip interface between the high performance StrongARM processor and the existing ICR C416 message routing chip. The ICR C416 is a non-blocking communications routing device. Each device allows concurrent communications with up to 16 processors. A distributed parallel processing system can be constructed using the StrongARM and ICRC416 devices, with features similar to that of a transputer system but with the benefits of the higher clock speed and cache memory of the StrongARM processor." } @InProceedings{BoostenDobinson98, title = "{A} {PCI}-based {N}etwork {I}nterface {C}ontroller for {IEEE} 1355 {DS}-{L}inks", author= "Boosten, Marcel and Dobinson, R. W. and Martin, B. and Stok, P. D. V. van der", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "49--68", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "We have investigated the construction of a parallel computer using IEEE 1355 high-throughput low-latency DS link networks and high-performance commodity processors running a standard operating system. In this context a DS Network Interface Controller (DSNIC) has been developed. The board's hardware, controlled by FPGA firmware, together with the host software, provides a CSP based message passing interface between standard OS processes. This paper describes how the design and realisation of the DSNIC refleat our aim: low-latency high-throughput inter-process communication. We show the benchmark results, their analysis, and suggest further performance gains that might be possible." } @InProceedings{AndersonBoosten98, title = "{IEEE} 1355 {DS}-{L}inks: {P}resent {S}tatus and {F}uture {P}rospects", author= "Anderson, C. R. and Boosten, Marcel and Dobinson, R. W. and Haas, S. and Heeley, R. and Madsen, N. A. H. and Martin, B. and Pech, J. and Thornley, D. A. and Ullod, C. L.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "69--80", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "IEEE 1355 HS-Links and their support devices have been investigated as part of the ESPRIT projects Macram\`{e} and Arches. A description of the HS-Link technology and initial experience with the RCube 8-way packet router and the Bullit HS-Link interface device are presented. A 64 node HS-Link switching network based using these devices is being constructed at CERN. We report on the design and construction of the network testbed." } @InProceedings{AuburyPage98, title = "{A}dvanced {S}ilicon {P}rototyping in a {R}econfigurable {E}nvironment", author= "Aubury, Matt and Page, Ian and Plunkett, Dominic and Sauer, Matthias and Saul, Jonathan", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "81--92", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "A flow is proposed which offers a programming approach to the systems design of application specific micro-controllers. This flow is based on Handel-C, an occam-based language with C-like syntax for hardware compilation. Tools have been developed for compilation and concurrent simulation (co-simulation) of hardware and software parts of a system, and a reconfigurable board has been designed which can be used for rapid prototyping of the application specific micro-controller. The final design can be compiled into a structural VHDL netlist for a standard cell ASIC process." } @InProceedings{MartinJassim98, title = "{A} {T}echnique for {C}hecking the {CSP} sat {P}roperty", author= "Martin, Jeremy M. R. and Jassim, S. A.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "93--110", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "This paper presents an algorithm for checking that a CSP process satisfies a specification defined by a boolean-valued function on its traces and refusals, i.e. P sat f(tr, ref) This is contrasted with the refinement approach, as implemented by the FDR tool, of checking that one CSP process is a possible implementation of another, i.e. P \>= SPEC" } @InProceedings{Lawrence98a, title = "{E}xtending {CSP}", author= "Lawrence, Adrian E.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "111--132", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "CSP, timed or untimed, has not included a general treatment of priority, although the PRI ALT constructor is an essential part of occam. This paper introduces CSPP which includes a generalization of PRI ALT in the form of a prioritized external choice P \<pribox\> Q. PRI PAR is also included. A new denotational semantics is introduced, although only the simplest model is outlined. The work is intended to provide a solid rogorous foundation for hardware-software codesign. And a companion paper describes untimed HCSP which is a further extension of CSP built upon these foundations. It was first presented informally at the Twente WoTUG-20 technical meeting." } @InProceedings{Lawrence98b, title = "{HCSP}: {E}xtending {CSP} for {C}odesign and {S}hared {M}emory", author= "Lawrence, Adrian E.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "133--156", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "HCSP is a variant of CSP adapted to capture the semantics of hardware compilation, among other purposes. It extends CSP in several ways; it includes priority; events can be combined; new synchronization constructors are introduced; and state is explicitly modelled. Including state permits the treatment of shared memory as well as message passing systems. A possible denotational semantics is included here ths allowing proper treatment of such systems. Although most of these extensions were motivated by the needs of hardware compilation, HCSP can be applied more widely including software and thus can form the foundation of a codesign language. HCSP is an extension of CSPP; familiarity of CSPP is assumed here." } @InProceedings{Kalogerop98, title = "{D}eveloping an optimising compiler for occam", author= "Kalogeropoulos, Spiridon", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "157--166", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "occam is a high-level language which got constructs for generating explicitly concurrent processes which communicate using channels. In this paper we present our methodology for developing an optimising occam compiler which consist of a framework to represent concurrency and the semantic properties of an occam program that enables efficient process optimisations, and inter-procedural optimisations to be performed. Furthermore, we tackle the issue of retargeting the optimising occam compiler for different processors of the transputer family." } @InProceedings{SheenAllen98, title = "oc-{X}: an {O}ptimising {M}ultiprocessor occam {S}ystem for the {P}ower{PC}", author= "Sheen, Tim and Allen, Alastair R. and Ripke, Andreas and Woo, Stacy", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "167--186", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "The development of a PowerPC port of the KRoC (portable occam compiler) is described. As well as the basic port, a multiprocessor run time system provides services for user programs, including efficient occam channels between distributed processes, natural access to host file systems and TCP/IP network sockets. Optimization of target assembly code is discussed, with methods for removing the inefficiencies introduced by the KRoC translation process." } @InProceedings{Poole98, title = "{E}xtended {T}ransputer {C}ode -- a {T}arget-{I}ndependent {R}epresentation of {P}arallel {P}rograms", author= "Poole, Michael D.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "187--198", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "The transputer instruction set and its symbolic representation are reviewed. An alternative representation named ETC-code, suitable for an intermediate representation in a retargettable occam compiler, is motivated and described. The translation of such a language into a variety of alternative target languages is discussed. Its use as a representation for programs whose target processor type is not yet known is proposed." } @InProceedings{WongLau98, title = "{MALT}: {A} {M}ultiway {A}lternation {C}onstruct for occam", author= "Wong, Adam K. L. and Lau, Francis C. M.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "199--210", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "The alternation construct in occam provides a form of binary selective communication to the cooperating tasks of a concurrent computation. The use of this construct could lead to increased responsiveness and efficiency of concurrent programs. However, the expressiveness of the construct is restricted in the sense that only two parties can be involved in a communication. We extend the current implementation of the alternation construct to accept an arbitrary number of channel inputs such that multiway (as opposed to binary) selective communication is made possible. A new construct called multiway alternation -- \"MALT\", is proposed for occam and is implemented in the transputer hardware." } @InProceedings{Umland98, title = "{P}arallel {G}raph {C}olouring using {J}ava", author= "Umland, Thomas", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "211--218", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "In this paper a parallel, pipeline orientated version of a well-known sequential graph coloring heuristic is introduced. Runtime and speedup results of an implementation in JAVA on a four processor machine are presented and discussed." } @InProceedings{Sousa CasJr98, title = "{A} {F}ault-{T}olerant {O}n-board {C}omputer for {S}pace {A}pplications", author= "Sousa Castro, Helano de and Jr, Jo\~{a}o Reinaldo Imbiriba and Silveira, Jarbas Aryel N. and Santiago, Valdivino and Monteiro, Ant\^{o}nio Miguel Vieira", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "219--230", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "The first Brazilian microsatellite will be launched at the middle of 1998. The on-board computer, named Trisputer, will play a major part in the mission, since it will perform essential on-board functions, such, as guidance, control of the on-board instrumentation, telemetry/telecommand, and control of some on-board scientific experiments. The Trisputer is a fault-tolerant multiprocessor computer with a high reliability, when compared to such systems as TMR, and Duplex. This paper describes the conception and implementation of the hardware of this computer, as well as it shows its reliability model." } @InProceedings{KatalovKatalov98, title = "{D}esign and {M}onitoring {S}ystems for {P}arallel {P}rogramming", author= "Katalov, Alexander J. and Katalov, Vladimir J. and Nikolaev, Vladimir K.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "231--258", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", abstract= "In this paper we consider computer-based systems for designing, debugging, tuning and optimising parallel programs. The development of such systems is complicated and labour-intensive. Despite this, many interesting projects have been developed in the last few years, which can be effectively used to design and debug programs for parallel architectures. We analyse the current state in this area and the various approaches are compared." } @InProceedings{Welch98, title = "{J}ava {T}hreads in the light of occam/{CSP}", author= "Welch, Peter H.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "259--284", booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications", isbn= "90 5199 391 9", year= "1998", month= "mar", } @InProceedings{KerridgeMcNair99, title = "{PEDFLOW} - {A} {S}ystem for {M}odelling {P}edestrian {M}ovement using occam", author= "Kerridge, Jon and McNair, N.", editor= "Cook, Barry M.", pages = "1--18", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "Road traffic modelling and simulation is currently well provided with a variety of packages dealing with the minute detail of road layouts from single isolated junction models to complete network simulations. There has also been much work in developing assignment models to optimise traffic signal sequences. The same is not true in the pedestrian modelling arena. With the exception of models dealing with railway and airport concourses and models of pedestrian movements around sports stadia there is very little support for the planner or designer of the pedestrian urban environment. The system discussed in this paper provides some insights as to the reasons for this and describes a highly parallel microscopic model called PEDFLOW (PEDestrian FLOW) which attempts to remedy the situation. The model operates on a grid size that is equivalent to the space occupied by a person at rest. The major difference between vehicular and pedestrian movement is that the former really has only one degree of freedom, forwards, whereas a pedestrian has unlimited two-dimensional degrees of freedom. Vehicular travel is governed by a large number of laws and regulations that make it much easier to model. Within the pedestrian urban environment there are very few laws and regulations and those that do apply are related to interactions with vehicles. The design of PEDFLOW is discussed and it is shown how the complex behavioural rules governing pedestrian movement are captured. The parallel architecture underlying the model is described and it shows how the maximum possible parallelism is achieved among all the moving pedestrians at any one time. The performance of the model is then presented and uses to which the model is being put are then briefly presented." } @InProceedings{Teig99, title = "{A}nother {S}ide of {SP}o{C}: occam's {ALT}er {E}go {D}issected with {PC}-lint", author= "Teig, Øyvind", editor= "Cook, Barry M.", pages = "19--36", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "26500 lines of Standard C (ANSI C) generated from occam sources by the Southampton Portable occam Compiler (SPoC) has been analysed by the static analysis tool PC-lint. The target machine is a TMS320C32 DSP where all (the supported) C\'s primitive data types are mapped to 32 bit read and writes. This architecture stretches \"ANSI\" C quite a bit, but the \"portable\" occam compiler promised to handle it. Even if we had experienced no problems with the generated code and it compiled with all error handling enabled, we had to insert some 15-20 different global PC-lint filters plus local filters via in-line C in the occam sources. This was in addition to the base-level filters we also used for hand-written C. It kept PC-lint quiet, for individual C files as well as \"global wrap up\". By discussing each individual filter we arrive at the conclusion that none hid errors in the generated C. The analysis revealed a few points where the occam language definition could have been made stricter. We would like to PC-lint the generated sources with fewer messages disabled - changes to SPoC are therefore suggested. Altogether SPoC seems to have passed this test quite well. Even if we have no expertise to modify the (open) SPoC sources, this report could be considered as contributing to a prospective \"Bazaar\" development model - to bring forward an even more robust compiler for a portable and perhaps prospering occam language." } @InProceedings{LiewONeill99, title = "{A} {P}roposal for an {O}perating {S}ystem for a {M}ulti-{P}rocessor {S}trong{ARM} {S}ystem", author= "Liew, E. W. K. and O'Neill, Brian C. and Wong, Adam K. L. and Clark, S. and Thomas, P. D. and Cant, R.", editor= "Cook, Barry M.", pages = "37--46", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "This paper describes real-time software features to support parallel processing. Synchronized channel communications are implemented as a basic operating system function for a distributed memory multi-processor StrongARM system. Inter-processor communications are handled using the ICR C416 packet router switch, which makes the system scalable. The system will provide a considerable layer of software abstraction and support to the end-users for developing their applications. The kernel layers, inter-process communications, control flow of application software, and the stages involved in application development for end-users, are described here. Some performance considerations are briefly discussed." } @InProceedings{MartinTiskin99, title = "{BSP} {M}odelling of {T}wo {T}iered {A}rchitectures", author= "Martin, Jeremy M. R. and Tiskin, Alex V.", editor= "Cook, Barry M.", pages = "47--56", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "In recent years there has been a trend towards using standard workstation components to construct parallel computers, due to the enourmous costs involved in designing and manufacturing special-purpose hardware. In particular we can expect to see a large population of SMP clusters emerging in the next few years. These are local-area networks of workstations, each containing around four parallel processors with a single shared memory. To use such machines effectively will be a major headache for programmers and compiler-writers. Here we consider how well-suited the BSP model might be for these two-tier architectures, and whether it would be useful to extend the model to allow for non-uniform communication behaviour. " } @InProceedings{MartinMcLatchie99, title = "{S}upercomputing {R}esource {M}anagement - {E}xperience with the {SGI} {C}ray {O}rigin 2000", author= "Martin, Jeremy M. R. and McLatchie, R. C. F. and Measures, K. M.", editor= "Cook, Barry M.", pages = "57--66", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "The Oxford Supercomputing Centre OSC was established in April 1998 to provide high-performance computing services to a consortium of Oxford University research groups. The main computer resource, an 84-processor SGI Cray Origin 2000 known as Oscar, is being deployed in a wide variety of research studies covering biological, medical, chemical, mathematical, physical and engineering topics (including parallel computing itself). In this paper we shall describe the queueing and accounting mechanisms we have developed to facilitate effective use of this powerful resource. We shall also describe innovative work in progress to optimise the performance of this machine, using simulation and genetic algorithms. " } @InProceedings{CookWhite99, title = "{J}ava {J}oins {IEEE}-1355 in the {H}ome {N}etwork", author= "Cook, Barry M. and White, N. H.", editor= "Cook, Barry M.", pages = "67--76", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "Issues concerning Home networks are discussed. The two main areas are the physical connections used and the communications protocols required. Of the physical connections available the IEEE-1355 family is addressed in particular. The software protocol proposed consists of embedding device drivers within the device itself. The device uploads its driver to one or many intelligent units. This approach is achieved here by using Java bytecode. It is argued that this mechanism eliminates the need for a pre-determined all-encompassing protocol, provides a simple and future-proof system and ensures that home networks can be quite literally plug and play. " } @InProceedings{Campbell99, title = "{A}n {A}lgorithm for {C}aching {S}oftware to {C}onfigurable {H}ardware", author= "Campbell, J. D.", editor= "Cook, Barry M.", pages = "77--86", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "In the same fashion that a memory cache arranges for machine instructions and data that are frequently accessed to operate from high speed memory, the functionality cache installs hardware implementations of frequently executed code sequences in reconfigurable hardware. Code sequences become candidates for instantiation as hardware if the benefits outweigh the costs over some accounting period. Algorithms are provided for converting sequences of stack manipulations characteristic of executable Java programs into systolic processing circuitry and mapping that machinery into networks of FPGAs (Field Programmable Gate Arrays)." } @InProceedings{VellaWelch99, title = "{CSP}/occam on {S}hared {M}emory {M}ultiprocessor {W}orkstations", author= "Vella, Kevin and Welch, Peter H.", editor= "Cook, Barry M.", pages = "87--120", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "This paper outlines the design and performance of a system for executing occam programs on multiprogrammed shared memory multiprocessor workstations. In particular, a fast SMP scheduler that executes process code generated by the standard KRoC compiler (originally designed for uniprocessors) is described; new wait-free multiprocessor-safe algorithms for both committed and alternative CSP channel communication operations are presented; a technique for allowing surplus processors to idle altruistically under a multiprogrammed regime is outlined. The run-time performance of the system is measured under a range of process granularities on one to four processors, using a synthetic benchmark. The performance of two real applications, namely Quickersort and matrix multiplication, is then analysed in some detail. Finally, alternative scheduling strategies to further improve the scalability of the system under conditions of very fine process granularity are proposed." } @InProceedings{WoodMoores99, title = "{U}ser-{D}efined {D}ata {T}ypes and {O}perators in occam", author= "Wood, David C. and Moores, James", editor= "Cook, Barry M.", pages = "121--146", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "This paper describes the addition of user-defined monadic and dyadic operators to occam, together with some libraries that demonstrate their use. It also discusses some techniques used in their implementation in KRoC for a variety of target machines." } @InProceedings{Moores99, title = "{CCSP} - {A} {P}ortable {CSP}-{B}ased {R}un-{T}ime {S}ystem {S}upporting {C} and occam", author= "Moores, James", editor= "Cook, Barry M.", pages = "147--169", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "CCSP is a highly portable run-time system that conforms to the ideas of CSP and supports both the C and occam programming languages. Its aim is to further the use of the CSP mind-set in both industrial and academic applications. The run-time system implements a useful and efficient subset of the basic CSP constructs. It allows occam-style designs to be programmed in C, thereby allowing full use of the optimisation phases of standard C compilers. It supports the KRoC occam system for Linux/PC platforms. In addition, a number of features have emerged from industrial collaboration as essential for soft real-time systems in the real world. These include: prioritised scheduling with 32 priority levels, integration of communications hardware to provide support for distributed processing, and access to a highly accurate real-time clock. This paper discusses the high level structure and functionality of the features provided." } @InProceedings{Lawrence99, title = "{H}ard and {S}oft {P}riority in {CSP}", author= "Lawrence, Adrian E.", editor= "Cook, Barry M.", pages = "169--197", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "Parallel systems which include priority can experience conflicts when two concurrent processes assign different priorities to the same actions. There are at least two ways to resolve the difficulty: one is to halt; the other is to declare a draw and allocate all the offending actions the same priority. In CSPP these are called respectively hard and soft priority. Originally CSPP included only hard priority. Here we extend the language to include soft priority as well. The Acceptances semantics which is used to define CSPP does not require modification: it captures both soft and hard behaviours. " } @InProceedings{IvimeyCoo99, title = "{L}egacy of the {T}ransputer", author= "Ivimey-Cook, Ruth", editor= "Cook, Barry M.", pages = "197--211", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "The Inmos transputer was more than a family of processor chips; it was a concept, a new way of looking at system design problems. In many ways that concept lives on in the hardware design houses of today, using macrocells and programmable logic. New Intellectual Property (IP) design houses now specialise in the market the transputer originally addressed, but in many cases the multi-threaded software written for that hardware is still designed and written using the techniques of the earlier sequential systems. The paper discusses the original aims of the transputer as a system design component, how they have been addressed over the intervening decades and where we should be focussing our thoughts for the new millennium." } @InProceedings{CookPeel99, title = "{O}ccam on {F}ield {P}rogrammable {G}ate {A}rrays - {S}teps towards the {P}ara-{PC}", author= "Cook, Barry M. and Peel, Roger M. A.", editor= "Cook, Barry M.", pages = "211--228", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "At the April 1998 WoTUG conference (WoTUG-21), it was reported that ST Microelectronics was ceasing production of most of the transputer family and its associated serial link components. The possibility of WoTUG members producing transputer-like devices to emulate many of the transputer\'s parallel processing and communication concepts was aired. The authors left this meeting with the challenge of designing and implementing their own transputer, preferably to be built in Field Programmable Gate Array (FPGA) devices rather than custom or semi-custom silicon, for ease of prototyping and for flexibility of modification and re-use.\</p\>\<p\> One year later, this paper outlines the progress that has been made. Rather than just producing processor logic using the standard logic design methods, the authors have written a compiler that translates occam into a number of output formats that can be fed to various logic implementation packages. Occam programs may, however, be joined to logic modules designed in a conventional fashion, using synchronised channels in the usual manner. In addition to the DS-Link interface that was announced by 4-Links at WoTUG-21, an OS-Link module has been designed by the authors, and both of these may provide external communication interfaces between occam-based hardware and the outside world.\</p\>\<p\> Although in their early stages, this paper illustrates several designs that show how occam may be used to specify small processors suitable for mapping onto FPGAs. It also shows how occam is an ideal fast prototyping mechanism for peripheral interfaces that connect to INMOS Links. " } @InProceedings{HilderinkBroenink99, title = "{A} {D}istributed {R}eal {T}ime {J}ava {S}ystem {B}ased on {CSP}", author= "Hilderink, Gerald H. and Broenink, Jan F. and Bakkers, Andr\`{e} W. P.", editor= "Cook, Barry M.", pages = "229--242", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "Real-time embedded systems in general require a reliability that is orders ofmagnitude higher than what is presently obtainable with state of the art C programs. Thereason for the poor reliability of present day software is the unavailability of a formalismto design sequential C programs.The use of the CSP channel concept not only provides a formal base for inherentlyconcurrent real-time embedded system design it also adds a parallel dimension to objectoriented programming that is easily understood by programmers.The CSP channels as implemented in Java replaces the hazardous use of multi threadedprogramming with an unambiguous design concept that is easy to reason about. Multithreaded programming is completely removed from the programmer who is merelyrequired to program small sequential tasks that communicate with each other via theseCSP channels. The channel concept that has been implemented in Java deals with singleandmulti processor environments and also takes care of the real-time priority schedulingrequirements. For this, the notion of priority and scheduling have been carefullyexamined and as a result it was reasoned that both priority and scheduling code should beattached to the communicating channels rather than to the processes. Moreover in theproposed system, the notion of scheduling is no longer connected to the operating systembut has become part of the application instead. One has to get used to the idea that manyschedulers may be running in different parts of a program. The software implementationof the Java channel class may be obtained through: http://www.rt.el.utwente.nl/javapp." } @InProceedings{BroeninkBakkers99, title = "{C}ommunicating {T}hreads for {J}ava", author= "Broenink, Jan F. and Bakkers, Andr\`{e} W. P. and Hilderink, Gerald H.", editor= "Cook, Barry M.", pages = "243--262", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "The Java * thread model provides support for multithreading within the language and runtime system of Java. The Java synchronization and scheduling strategy is poorly specified and turns out to be of unsatisfactory real-time performance. The idea of Java is to let the underlying operating system specify the synchronization and scheduling principles. This may possibly result in different behavior on different operating systems whereas Sun claims Java to be system independent – \"write once, run everywhere\". In this paper we present a comprehensive specification for a new thread model for the Java platform.The theory of CSP fully specifies the behavior of synchronization and scheduling of threads at a higher level of abstraction, which is based on processes, compositions and synchronization primitives. The CSP concept is well thought-out and has been proven to be successful for realizing concurrent software for real-time and embedded systems. The Communicating Threads for Java (CTJ) packages that is presented in the paper provides a reliable CSP/thread model for Java. The CTJ software is available from our URL http://www.rt.el.utwente.nl/javapp." } @InProceedings{DobinsonStok99, title = "{F}ine {G}rain {P}arallel {P}rocessing on {C}ommodity {P}latforms", author= "Dobinson, R. W. and Stok, P. D. V. van der and Boosten, Marcel", editor= "Cook, Barry M.", pages = "263--276", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "We present a tight integration of a user-level thread scheduler and a zero-copy messaging system that has been designed and optimized for scalable and efficient fine-grain parallel processing, on commodity platforms, with support for fault-tolerance. The system delivers most of the performance of the underlying communication hardware to a multi-threaded application level, while introducing little CPU overhead. This is demonstrated by a performance analysis of an implementation using off-the-shelf commodity products: PCs, running the Linux operating system, equipped with Fast and Gigabit Ethernet network interface cards." } @InProceedings{BakkersStiles99, title = "{CSP} for {J}ava: {M}ultithreading for {A}ll", author= "Bakkers, Andr\`{e} W. P. and Stiles, G. S. and Welch, Peter H. and Hilderink, Gerald H.", editor= "Cook, Barry M.", pages = "277--279", booktitle= "{P}roceedings of {W}o{TUG}-22: {A}rchitectures, {L}anguages and {T}echniques for {C}oncurrent {S}ystems", isbn= "90 5199 480 X", year= "1999", month= "mar", abstract= "Many internet, real-time and embedded applications are most naturally designed using concurrency. Unfortunately, the design of concurrent (multithreaded) programs has the reputation of being extremely difficult and dangerous, due to the possibility of deadlock, livelock, race hazards, or starvation - phenomena not encountered in single-threaded programs. Lea [1] emphasizes concern for the apparent difficulty: \"Liveness considerations in concurrent software development introduce context dependencies that can make the construction of reusable components harder than in strictly sequential settings.\" Two approaches he suggests for design sound tedious and perhaps risky: \"Top-down (safety first): Initially design methods and classes assuming full synchronization (when applicable), and then remove unnecessary synchronization as needed to obtain liveness and efficiency...Bottom up (liveness first): Initially design methods and classes without concern for synchronization policies, then add them via composites, subclassing, and related layering techniques...\" Both suggest lengthy sessions of patching and testing until the application appears to work as desired. Even those intimately connected with Java seem reluctant to employ more than a single thread. The Swing documentation states \"If you can get away with it, avoid using threads. Threads can be difficult to use, and they make programs harder to debug. In general, they just aren\'t necessary for strictly GUI work, such as updating component properties\" [2]. Oaks and Wong [3], also associated with Sun, are more positive, but note that \"Deadlock between threads competing for the same set of locks is the hardest problem to solve in any threaded program. It\'s a hard enough problem, in fact, that we will not solve it or even attempt to solve it.\" Later they state \"Nonetheless, a close examination of the source code is the only option presently available to determine if deadlock is a possibility...\" and add that no tools exist for detecting deadlock in Java programs. We feel, however, based on fifteen years of experience, that concurrent approaches are the best way to design most programs. Done properly (e.g., using CSP [4]) this results in better understanding of the problem and the solution, and leads to much cleaner implementations. A tremendous amount of work has been done on and with CSP in recent years, and the present state of the language and the tools offers the Java programmer excellent facilities for the design and analysis of multithreaded programs. Furthermore, Java designs based on CSP class libraries can now be verified against formal specifications and checked for deadlock and livelock with CASE tools - prior to implementation. We present the CSP model (processes, channels, events, networks) and its binding into (100\% Pure) Java through the CSP class libraries developed at Kent [5] and Twente [6]. We describe some of the tools associated with CSP (e.g., FDR [7]) and demonstrate, in several practical applications, their use for checking specifications and proving the absence of deadlock. We emphasize that CSP concepts are easy to understand and apply and that the engineering benefits they confer on system design and implementation are significant for both real-time and non-real-time multithreaded systems." } @InProceedings{Sunter00, title = "{C}oncurrency in {I}ndustry ({W}ot, no {CSP}s?)", author= "Sunter, Johan P. E.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "Within an international company such as Philips, systems are made from the very small to the extremely large. And although parallelism is an important aspect of system architecture, it is often overlooked. Due to the wide variety of systems, parallelism presents itself in many different shapes, requiring different design approaches. What approaches have been chosen in the past, and do they have something in common? Can we learn from them how to do it better? What do we need in the future?" } @InProceedings{MartinHuddart00, title = "{P}arallel {A}lgorithms for {D}eadlock and {L}ivelock {A}nalysis of {C}oncurrent {S}ystems", author= "Martin, Jeremy M. R. and Huddart, Yvonne", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "1--14", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "Conventional model-checking techniques for analysing concurrent systems for deadlock or livelock are hampered by the problem of exponential state explosion: the overall number of global states that needs to be checked may grow exponentially with the number of component processes in the system. The state-of-the-art commercial tool FDR provides deadlock and livelock analysis but it is limited at present to analysing systems of up to one hundred million global states. The Deadlock Checker tool is capable of analysing very much larger systems by taking certain short-cuts. But this is achieved at the cost of incompleteness -- there are certain deadlock-free and livelock-free networks that may not be proven so using that tool. Here we investigate a different approach. We present parallelised model-checking algorithms for deadlock and livelock analysis and describe their implementation. The techniques are found to scale well running either on a conventional supercomputer or on a PC cluster." } @InProceedings{ZhouStiles00, title = "{T}he {A}utomated {S}erialization of {C}oncurrent {CSP} {S}cripts using {M}athematica", author= "Zhou, Weiyang and Stiles, G. S.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "15--32", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "This report discusses the design and implementation of a package of Mathematica-based tools for serializing scripts describing the behavior of concurrent systems in CSP. Under some conditions, serialization can yield code that is more efficient than multi-process versions and can better meet processor constraints. Under most conditions concurrent design is easier and more reliable so we prefer to design concurrently and only implement serially when necessary. The tools include a set of definitions and procedures to automatically change concurrent code to serial code. Conversions of the following step laws have been implemented thus far: external choice, generalized parallel, and alphabetized parallel; additional laws will be implemented in the next month or so. The tools support the input of the more formal typeset notation of CSP, which makes the script writing intuitive, and can convert the typeset version to the machine-readable version required by software such as FDR. The correctness of the conversions has been checked with the FDR package. This package should be of use to both those regularly working on concurrent systems and those learning CSP." } @InProceedings{VolkerinkHilderink00, title = "{CSP} {D}esign {M}odel and {T}ool {S}upport", author= "Volkerink, H. J. and Hilderink, Gerald H. and Broenink, Jan F. and Veroort, W.A. and Bakkers, Andr\`{e} W. P.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "33--48", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "The CSP paradigm is known as a powerful concept for designing and analysing the architectural and behavioural parts of concurrent software. Although the theory of CSP is useful for mathematicians, the programming language occam has been derived from CSP that is useful for any engineering practice. Nowadays, the concept of occam/CSP can be used for almost every object-oriented programming language. This paper describes a tree-based description model and prototype tool that elevates the use of occam/CSP concepts at design level and performs code generation for the level of implementation in Java, C/C++, and machine-readable CSP. The tool is a kind of browser that is able to assist modern workbenches (like Borland Builder, Microsoft Visual C++ and 20-SIM) with coding concurrency. The tree description model can be used to browse through the generated source code. The tool will guide the user through the design trajectory using supporting messages and several semantic and syntax rule checks. The machine-readable CSP can be read by FDR, enabling more advanced analysis on the design. Early experiments with the prototype tool show that the browser concept, combined with the tree description model, enables a user-friendly way to create a design using the CSP concepts and benefits. The design tool is available from our URL, http://www.rt.el.utwente.nl/javapp." } @InProceedings{RipkeAllen00, title = "{D}istributed {C}omputing using {C}hannel {C}ommunications in {J}ava", author= "Ripke, Andreas and Allen, Alastair R. and Feng, Y.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "49--62", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "Various methods of connecting CSP channels to external software systems are examined. The aim is to facilitate the implementation of distributed heterogeneous systems using channel communication. The paper concentrates on TCP/IP connections in a Java environment. The approaches used are: custom protocol; object serialization stream protocol; Remote Method Invocation (RMI); Common Object Request Broker Architecture CORBA). Practical systems are described and compared." } @InProceedings{WellsClayton00, title = "{A} {C}omparison of {L}inda {I}mplementations in {J}ava", author= "Wells, George and Clayton, Peter and Chalmers, Alan G.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "63--76", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "This paper describes the implementation of an extended version of Linda in Java. The extensions have been made with a view to increasing the efficiency of the underlying communication mechanisms and the flexibility with which data may be accessed, particularly in the area of distributed multimedia applications. The system is compared with two other recent implementations of Linda for Java: JavaSpaces from Sun Microsystems, and TSpaces from IBM. The comparison is performed both qualitatively, comparing and contrasting the features of the systems, and quantitatively, using a simple communication benchmark program and a ray-tracing program to assess the performance and scalability of the different systems for networks of workstations." } @InProceedings{HilderinkBroenink00, title = "{C}onditional {C}ommunication in the {P}resence of {P}riority", author= "Hilderink, Gerald H. and Broenink, Jan F.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "77--98", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "In this paper the behavior of conditional communication in the presence of priority will be described. In the theory of CSP, conditional communications are expressed by a (external) choice construct (also known as the alternative construct) by which the choice of one communication out of a set of communications is non-deterministic. In practice, some communication can be more important than others, so that, the choice is deterministic. Therefore, one can distinguish two prioritized alternative constructs; a symmetric alternative construct (ALT) and an asymmetric alternative construct (PRIALT). Current formal semantics and implementations of the ALT and PRIALT are based on the priorities of communication and not related to the surrounding priorities of communicating processes. This can result in a structural mismatch that can cause performance problems. In this paper a practical solution for realizing fair and unfair conditional communication in the presence of the PAR and the PRIPAR will be discussed." } @InProceedings{LoveMartin00, title = "{S}teering {H}igh-{P}erformance {P}arallel {P}rograms: a {C}ase {S}tudy", author= "Love, P. J. and Martin, Jeremy M. R.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "99--108", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "Computational steering is the ability to visualise the data from a computation in progress and to modify the future behaviour of the computation in response to this. It is often perceived as being something very difficult to implement, especially for parallel computations. However, given a good visualisation environment, we have found that this is not necessarily the case. We have sought to dispel this myth, using a very simple model which makes it easy to 'wire-up' an existing MPI parallel program for steering. New insights may quickly be gained by continually monitoring and guiding the progress of computational simulations, that were perhaps previously analysed only in their final state." } @InProceedings{CannonDenys00, title = "{A} {S}elf-{C}onfiguring {D}istributed {K}ernel for {S}atellite {N}etworks", author= "Cannon, Scott and Denys, Larry", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "109--120", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "The Space Software Laboratory is developing a self-configuring distributed kernel to be used on future satellite missions. The completion of this system will allow a network of heterogeneous processor nodes to communicate and broadcast in a scalable, self-configuring manner. Node applications software will be transparent to the underlying network architecture, message routing, and number of network nodes. Nodes may halt or be reset and later rejoin the network. The kernel will support in-flight programming of individual nodes." } @InProceedings{VugtBakkers00, title = "{A} {C}ruise {C}ontrol in occam based on an {I}mplementation of {KR}o{C} on the {P}hilips 8051 {M}icrocontroller", author= "Vugt, Frank T. M. van and Bakkers, Andr\`{e} W. P.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "121--136", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "This paper summarises the results of the realisation of a Cruise Control system in occam using an implementation of the Kent Retargettable occam Compiler (KRoC) on the Philips 8051 microcontroller. The increase in complexity of systems designed comes with difficulties that can probably be overcome using concurrent programming languages. occam is such a language, originally developed for use with transputers. The KRoC initiative allows one to translate the transputer assembly produced from a program written in occam into the assembly of another processor. In this case, it was implemented for the Philips 8051 microcontroller, which is an 8-bits processor. The design and realisation in occam of the Cruise Control system of Yourdon demonstrate its proper functioning. The generated code is tested using a real-time in-circuit 8051 emulator and special hardware to represent car and interface. The design process using occam is compared to a regular solution using a language like C. Since this port is the first of its kind inasmuch as it is not targeting 'large' processors like the SPARC, important conclusions can be drawn regarding the power of the CSP-concept. The port is not complete yet, future work on it is recommended." } @InProceedings{SenMuller00, title = "{S}ynchronisation in a {M}ultithreaded {P}rocessor", author= "Sen, Shondip and Muller, Henk and May, David", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "137--144", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "A multithreaded architecture exploits instruction level parallelism by interleaving instructions from disjoint thread contexts. As each thread executes within its own instruction stream with private data (the context registers), there is no interdependency between instructions from different threads. This allows high resource utilisation of a super scalar pipelined processor at a very low cost, in terms of complexity and silicon area. A new synchronisation mechanism for a multithreaded architecture is outlined. Two new instructions have been introduced to perform one to one and n-way synchronisation. The operation allows synchronisations to be requested and actioned efficiently on chip in as little as four clock cycles. Barriers and CSP style channels can easily be constructed with this new synchronisation instruction. A brief examination of performance of this multithreaded architecture shows that the optimum number of contexts per multithreaded processing element is four, based on test programs." } @InProceedings{Barnes00, title = "{B}locking {S}ystem {C}alls in {KR}o{C}/{L}inux", author= "Barnes, Frederick R. M.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "155--178", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "This paper describes an extension to Kent Retargetable occam Compiler (KRoC), which enables the execution of a blocking call, without blocking the occam-kernel. This allows a process to make a blocking system call (eg, read, write), without blocking processes running in parallel with it. Blocking calls are implemented using Linux clones which communicate using shared memory, and synchronise using kernel level semaphores. The usefulness of this is apparent in server applications with a need to handle multiple clients simultaneously. An implementation of an occam web-server is described, which uses standard TCP sockets via an occam socket library. The web-server comes with the ability to execute CGI scripts as well as dispensing static pages, which demonstrates some level of OS process management from within occam. However, this mechanism is not limited to blocking in the Linux kernel. On multi-processor machines, the clones are quite free to be scheduled on different processors, allowing computationally heavy processing to be performed aside the occam world, but still with a reasonable level of interaction with it. Using them in this way provides a coarse-grained level of parallelism from within the fine-grained occam world." } @InProceedings{WoodBarnes00, title = "{P}ost-{M}ortem {D}ebugging in {KR}o{C}", author= "Wood, David C. and Barnes, Frederick R. M.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "179--192", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "A simple post-mortem debugging facility has been added to KRoC, to identify and locate run-time errors, including deadlock. It has been implemented for the SPARC/Solaris and i386/Linux versions of KRoC." } @InProceedings{Wood00, title = "{A}n {E}xperiment with {R}ecursion in occam", author= "Wood, David C.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "193--204", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "An experimental version of KRoC has been written that implements recursion in occam, using Brinch Hansen's algorithm for allocating activation records. It shows that efficient parallel recursion is possible in occam" } @InProceedings{SchallerHilderink00, title = "{U}sing {J}ava for {P}arallel {C}omputing - {JCSP} versus {CTJ}", author= "Schaller, Nan C. and Hilderink, Gerald H. and Welch, Peter H.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "205--226", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "Java provides support for concurrent and parallel programming throughthreads, monitors and its socket and Remote Method Invocation (RMI) classes.However, there have been many concerns expressed about the way in which thissupport is provided, e.g., [1][2], citing problems such as improper implementation ofmonitors and difficulty of programming with threads. Hoare’s CommunicatingSequential Processes (CSP) [3][4][5] model fully specifies thread synchronizationand is based on processes, compositions, and channel communication. It provides amathematical notation for describing patterns of communication using algebraicexpressions and contains formal proofs for analyzing, verifying and eliminatingundesirable conditions, such as race hazards, deadlocks, livelock, and starvation.Two independent research efforts provide a CSP based process-oriented designpattern for concurrency implemented in Java: Communicating Sequential Processesfor Java (JCSP) [6] and Communication Threads in Java (CTJ) [7]. In this paper, wecompare these two packages, looking at the philosophy behind their development,their similarities, their differences, their performance, and their use." } @InProceedings{PeelCook00, title = "occam on {F}ield {P}rogrammable {G}ate {A}rrays - {O}ptimising for {P}erformance", author= "Peel, Roger M. A. and Cook, Barry M.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "227--238", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "This paper shows how the parallel occam code for a graphics application has been compiled to run on a Field Programmable Gate Array (FPGA). This application has stringent timing constraints, and many optimisations to the sequencing of operations and occam constructs have been employed to meet them. In particular, two crucial pipelined processes are shown to operate with no control overhead despite containing parallel and looping constructs and channel communications." } @InProceedings{Beton00, title = "libcsp - a {B}uilding mechanism for {CSP} {C}ommunication and {S}ynchronisation in {M}ultithreaded {C} {P}rograms", author= "Beton, Rick D.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "239--250", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "A C library is described which exists to support synchronisation and communication in the CSP model using the Posix Threads API as its basis. This differs from other notable approaches (e.g. [Moores:1999]) in that it uses Posix Threads. Whilst this approach has drawbacks, its main achievement is being easily adopted by people already familiar with Posix Threads and being useful to a wide range of target platforms." } @InProceedings{Teig00, title = "{CSP}: {A}rriving at the {CHAN}nel {I}sland (an {I}ndustrial {P}ractitioner's {D}iary: in {S}earch of a {N}ew {F}airway)", author= "Teig, Øyvind", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "251--262", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "This paper is a non-academic hands-on log of practical experiences of software engineering problems, where the process leading to the decision to use CSP to program real-time systems is on trial. A new and hopefully objective decision process is instigated. What we have previously learnt by using CSP in embedded real-time process control is used as subjective basis (or bias?) for the new process. The conclusion seems to be that CSP should be sufficiently future-proof to justify its use even in new projects. The term CSP is here used as shorthand for both the CSP language proper and different implementations of subsets." } @InProceedings{Moores00, title = "{N}ative {JCSP} - the {CSP} for {J}ava library with a {L}ow-{O}verhead {CSP} {K}ernel", author= "Moores, James", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "263--274", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "The JCSP library provides a superior framework for building concurrent Java applications. Currently, CSP is a collection of classes that uses the standard Java Threads mechanism to provide low-level facilities such a process scheduling and synchronization. The overheads of using Java Threads can be quite large though, especially for synchronization and context switching. This paper begins by describing various options for increasing performance, and then how the standard Java threads work. The integration of the low-overhead CCSP run-time system into a Linux-based Sun JDK 1.2.1 Java Virtual Machine is then described. This integration provides the low-level support required to dramatically increase the performance of the JCSP library's model of concurrency. The paper then looks at the problem of maintaining backward compatibility by preserving the functionality of the existing threads mechanism on which much legacy code depends. The paper finishes by looking at the performance displayed by the current prototype JVM and contrasting it with the performance of both Green (co-operatively scheduled) and Native (operating-system scheduled) Java Threads." } @InProceedings{WelchMartin00, title = "{F}ormal {A}nalysis of {C}oncurrent {J}ava {S}ystems", author= "Welch, Peter H. and Martin, Jeremy M. R.", editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.", pages = "275--301", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2000", isbn= "1 58603 077 9", year= "2000", month= "sep", abstract= "Java threads are synchronised through primitives based upon monitor concepts developed in the early 1970s. The semantics of Java's primitives have only been presented in natural language -- this paper remedies this with a simple and formal CSP model. In view of the difficulties encountered in reasoning about any non-trivial interactions between Java threads, being able to perform that reasoning in a formal context (where careless errors can be highlighted by mechanical checks) should be a considerable confidence boost. Further, automated model-checking tools can be used to root out dangerous states (such as deadlock and livelock), find overlooked race hazards and prove equivalence between algorithms (e.g. between optimised and unoptimised versions). A case study using the CSP model to prove the correctness of the JCSP and CTJ channel implementations (which are built using standard Java monitor synchronisation) is presented. In addition, the JCSP mechanism for ALTing (i.e. waiting for and, then, choosing between multiple events) is verified. Given the history of erroneous implementations of this key primitive, this is a considerable relief." } @InProceedings{BastenHoogerbru01, title = "{E}fficient {E}xecution of {P}rocess {N}etworks", author= "Basten, T. and Hoogerbrugge, J.", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "1--14", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "Kahn process networks (KPNs) [1] are a popular modeling technique for media- and signal-processing applications. A KPN makes parallelism and commu-nication in an application explicit; thus, KPNs are a modeling paradigm that is very suitable for multi-processor architectures. We present techniques for the efficient ex-ecution of KPNs, taking into account both execution time and memory usage." } @InProceedings{MayMuller01, title = "{C}opying, {M}oving and {B}orrowing {S}emantics", author= "May, David and Muller, Henk", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "15--26", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "In this paper we discuss primitives for mobilising code and communications. We distinguish three types of semantics for mobility: copying (where an identical copy is created remotely), moving (where the original is destroyed), and borrowing (where the original is moved to the target and back to where it came from at defined moments). We discuss these semantics for mobile code and mobile channels. We have implemented Icarus, a language that uses borrowing semantics for mobile code (the on-statement) and moving semantics for mobile channels (first class channels)." } @InProceedings{Moore01, title = "{P}arallel {G}enetic {A}lgorithms to {F}ind {N}ear {O}ptimal {S}chedules for {T}asks on {M}ultiprocessor {A}rchitectures", author= "Moore, M.", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "27--36", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "Parallel genetic schedulers (PGS) are applied to a combinatorial optimisation problem, the scheduling of multiple, independent, non-identical tasks. The tasks are functionally partitioned and must be distributed over a multicomputer or multiprocessor system. As each task completes execution, a result message must be communicated. Communication occurs over a shared bus. This problem is known to be NP-complete [1]. The PGS execute on a shared memory multiprocessor system and on a simulated SIMD torus. Schedules produced by the PGS are compared to each other, to those found by an exponential-time optimal branch and bound algorithm, and to those found by a linear-time opportunistic algorithm. The PGS produce extremely accurate schedules very quickly. When the PGS are executed with increasing numbers of processors, near linear speedups are obtained with no decrease in the quality of the resulting schedules." } @InProceedings{TrigerONeill01, title = "{A}dapted {OS} {L}ink / {DS} {L}ink {P}rotocols for {U}se in {M}utliprocessor {R}outing {N}etworks", author= "Triger, S. and O'Neill, Brian C. and Clark, S.", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "37--48", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "Inter-processor communications play a vital role in the performance of distributed parallel networks. This document analyses various protocol options for high speed, serial, inter-processor communications for use in embedded multiprocessor systems. The protocol is used to pass information in a fault tolerant routing network. The work has resulted in a custom processor interface, which forms the gateway between the processing node and the distributed communications network, building on previous work. The role of the interface is to provide maximum hardware support for communications between the network and the processor. This alleviates the processor from having to oversee communications transactions and allows it to concentrate on program execution. The research focuses on protocol alterations aimed at improving the fault tolerant aspects of the design when dealing with various forms of network failure. By improving the fault tolerance of the network, communications bottlenecks can be avoided and data throughput can be maximised. Previously, communications across the network had used the OS Links protocol and, experimentally, DS Links. These were analysed and adapted to provide the current communications protocol, which is compared with these protocols. This protocol is more efficient, and helps to provide many features to ensure data integrity." } @InProceedings{Lawrence01a, title = "{S}uccesses and {F}ailures: {E}xtending {CSP}", author= "Lawrence, Adrian E.", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "49--66", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "Standard CSP, timed or untimed, does not include a general treatment of priority, although the PRI ALT constructor is an essential part of occam and hardware compilation languages based upon occam. This is a revised version of the original paper which introduced CSPP, an extension of CSP incorporating priority. CSPP is defined by a novel denotational semantics, Acceptances, based on Successes rather than the usual Failures. The idea is to characterise a process by what it successfully accepts, rather than by what it refuses to do. In the light of experience, it might better have been called 'Responses'. The original Acceptances was exploratory, and tried to avoid constraining the sorts of systems, particularly circuits, that could be described. Experience has shown that it can be substantially simplified at very little cost. A new notation makes it much easier to follow, especially for the non specialist. This revision of the original introduction presents the simplified CSPP while retaining most of the motivational material. It is intended to have something of a tutorial flavour: three other papers, are more condensed, and deal with more technical matters. But the core semantics is common to all four. CSPP provides a rigorous comprehensible and simple foundation for compositional hardware-software codesign. HCSP is a further extension which includes extra facilities needed to describe certain circuits. And a further radical extension lifts the usual restrictions of timed CSP, and describes continuous analogue phenomena. CSPP was first presented informally at the Twente WoTUG--20 technical meeting." } @InProceedings{Lawrence01b, title = "{CSPP} and {E}vent {P}riority", author= "Lawrence, Adrian E.", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "67--92", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "CSPP is an extension of CSP which includes priority as used in standard occam. The occam community has often discussed whether those notions are really adequate, a particular concern being the difficulties associated with priority inversion. One idea is to give priority to sets of events considered independently of the processes that perform them. We call this 'event priority'. Event priority is static in this presentation. But it is possible to handle dynamic priority using a global synchronisation when the 'event priority' changes. Obviously there is no problem for a software system with a central scheduler, but the theory here is addressing a far wider class of systems, in particular massively parallel, widely distributed, implemented in either hardware or software or both. It may be that some higher level of abstraction should replace priority: priority is a mechanism for achieving certain properties, often relating to time and limited resources. Here we content ourselves with finding a formal description of a language including event-priority." } @InProceedings{Lawrence01c, title = "{I}nfinite {T}races, {A}cceptances and {CSPP}", author= "Lawrence, Adrian E.", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "93--102", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "There is a long standing problem when infinite traces are included in denotational semantic models of CSP. Full models fail to be Complete Partial Orders under refinement. This paper introduces a novel, but entirely natural, way of representing infinite behaviour in which refinement is a Complete Partial Order when the alphabet of events is finite. Acceptance semantics also solves the problem of infinite behaviour with an infinite alphabet. That requires a different construction based on a metric space and will be described elsewhere." } @InProceedings{TownerMay01, title = "{T}he `{U}niform {H}eterogeneous {M}ulti-{T}hreaded' {P}rocessor {A}rchitecture", author= "Towner, Daniel and May, David", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "103--116", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "Multi-threaded processor architectures are capable of concurrently execut-ing multiple threads using a shared execution resource. Two of their advantages are their ability to hide latency within a thread, and their high execution efficiency. Un-fortunately, single thread performance is often poor. In this paper we present a simple model of a multi-threaded processor, and show how an occam-like language may be compiled into fine grained threads suitable for executing on this processor. These fine grained threads allow all but the most serial programs to be compiled into multiple threads. Thus, poor single thread performance is avoided by ensuring that sufficient threads are always available, even at the instruction level. We call this technique ‘uni-form heterogeneous multi-threading’ (UHM). A compiler implementing UHM has been built, along with a cycle accurate simulator of a UHM processor. We demon-strate that the processor is capable of good performance, whilst being simple to design and build." } @InProceedings{RischelSun01, title = "{E}vent-{B}ased {D}esign of {C}oncurrent {P}rograms with {J}ava {I}mplementation", author= "Rischel, H. and Sun, H.", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "117--128", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "A systematic design approach to safety-critical systems is introduced by means of the Production Cell case study. The design is documented using CSP-style processes, which allow verifications using formal techniques, as well as programming in Java using the JCSP library." } @InProceedings{VinterAnshus01, title = "{U}sing {T}wo-, {F}our- and {E}ight-{W}ay {M}ultiprocessors as {C}luster {C}omponents", author= "Vinter, Brian and Anshus, Otto J. and Larsen, Tore and Bjørndalen, John Markus", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "129--148", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "This work considers the pros and cons of different size SMPs as nodes in clusters. We investigate the Intel SMP architecture and consider the potential of and some problems with larger node-sizes in clusters of multiprocessors. Six applications that represent different classes of parallel applications are developed in versions that support both shared and distributed memory. Performance measurements are done on three different clusters of multiprocessors, with the purpose of identifying how the number of processors in each SMP node impacts the cluster performance. Our results show that clusters using higher order SMPs do not give a clear performance benefit compared to clusters using two-way SMPs. Off the bench mark-suite of six applications, the performance of two turn out to be independent of node-size, two show an advantage of larger node-sizes, as much as 34 percent improvement of eight-way nodes over a dual-system, while the remaining two show an advantage of dual-processor nodes as big as 11 percent over an eight-way cluster." } @InProceedings{YangStiles01, title = "{G}uarenteed {M}essage {D}elivery {T}ime on {R}eal-{T}ime {D}istributed {S}ystems", author= "Yang, T. -Y. and Stiles, G. S.", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "149--166", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "Real-time systems require guaranteed timely delivery of messages; failure to deliver a message on time may result in failure of the system and possible damage to life and property. We describe here an extension and implementation of an algorithm developed by Kandlur et al. for guaranteed message delivery. We extend this by adding two-phase randomized routing in the channel establishment procedure; this scheme requires each route to go first to a randomly chosen intermediate node, and only then to its actual destination. This scheme balances the load demonstrably better than direct routing, with respect to the likelihood of acceptance of each individual channel. Given certain constraints on the generation and size of messages, it is possible to schedule those messages such that messages arrive within their desired deadlines. Experiments on an 8-node network demonstrate the feasibility of the approach, and provide verification of Kandlur's algorithm." } @InProceedings{WattMay01, title = "{A} {P}rogramming {L}anguage for {H}ardware/{S}oftware {C}o-{D}esign", author= "Watt, D. R. and May, David", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "167--178", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "We have developed a programming language that allows programs to be expressed as single specifications in which any number of processes may be tagged for hardware compilation and the rest are compiled into software. We introduce a number of novel transformations that may be arbitrarily applied to an occam process in order to decompose it into two semantically equivalent concurrent processes. Our compiler targets hardware by compiling one of these processes into a field programmable gate array and the other into x86 object code. Furthermore, the compiler integrates a specialised communications protocol between the two programs that consists of a full-duplex channel implementation, multiplexor and buffers that are dependent on the program structure and that guarantee all external communications are free from deadlock. We demonstrate the elegance of our language and the power of our compiler on a small benchmark program." } @InProceedings{Peel01, title = "{A} {R}econfigurable {H}ost {I}nterconnection {S}cheme for {O}ccam-{B}ased {F}ield {P}rogrammable {G}ate {A}rrays", author= "Peel, Roger M. A.", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "179--192", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "This paper reports on the development of an interconnection scheme for field-programmable gate arrays (FPGAs). These FPGAs may be programmed in the Occam parallel programming language. Now, not only may the inter-process communication channels provided by Occam be used on-chip, but they may also be extended to a host processor using the ubiquitous Universal Serial Bus (USB). Bidirectional channels of BYTEs are carried along this bus to a host processor (running Linux) where they are presented to application code using a device driver that provides similar capabilities to the standard B004 card link driver. A unidirectional end-to-end throughput between Linux processes and FPGA processes, across USB, has been measured as high as 1025 kbytes/sec, although this rate is only achieved in favourable circumstances. Similarly, 410 kbytes/sec may be transferred in both directions simultaneously. Unidirectional transmission rates of more than 600 kbytes/sec, and bidirectional rates of 175-300 kbytes/sec in each direction may be achieved in a wide range of circumstances. The paper presents a range of performance figures, explaining which are limited by the underlying characteristics of the USB bus and which are caused by the current implementation. By implementing a transputer OS-Link in the FPGA, it is possible for a USB- enabled computer to communicate with a network of transputers, providing a convenient - and potentially faster - alternative to previous methods." } @InProceedings{McConnellWinser01, title = "{A} 40 {G}bit/s {N}etwork {P}rocessor {D}esign {P}latform", author= "McConnell, R. and Winser, P.", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "193--212", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "As the Internet evolves, the rapidly increasing demand for bandwidth is matched by a greater need for more intelligence with which to manage and meter the flow of that data to sustain economic growth. Conventional processing architectures and hardwired point solutions are not suited to these conflicting demands; there is an emerging need for a new approach for this data flow processing problem. This paper presents ClearSpeed's integrated Network Processor design platform that embodies many different levels of parallel processing. Designed to balance the bandwidth needs with programmability we introduce the MTAP architecture. An area and power efficient, fine-grained, scalable, multi-threaded parallel processor, designed with a 'bandwidth-centric' architecture and programmed in C. Based on the ClearConnect™ bus, an SoC communication architecture with VCI compliant interfaces, a high-bandwidth system architecture including a number of hardware accelerator units is also described. An example 40Gbit/s programmable and scalable classifier/forwarder is presented, embodying the concepts of the platform. To complete the picture, a comprehensive suite of software and hardware development tools is described." } @InProceedings{PascoeLoader01, title = "{W}orking {T}owards the {A}greement {P}roblem {P}rotocol {V}erification {E}nvironment", author= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "213--230", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "This paper proposes the Agreement Problem Protocol Verification Environment (APPROVE) for the automated formal verification of novel solutions to agreement problems in group communication systems. Agreement problems are characterized by the need for a group of processes to agree on a proposed value and are exemplified by group membership, consensus and fault-tolerance scenarios. Due to their fundamental role, it is important that the correctness of new agreement algorithms be verified formally. In the past, the application of manual proof methods has been met with varying degrees of success, suggesting the need for a less error prone automated approach. An observation concerning previous proofs is that often a significant amount of effort is invested in modeling themes common to all such proofs, albeit using different formalisms. Thus, the APPROVE project aims to address these issues, its envisaged culmination being a usable software framework that exploits model re-use wherever possible." } @InProceedings{East01, title = "{W}orking towards a successor to occam", author= "East, Ian R.", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "231--242", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "occam [1] offers features and attributes that make it unique among programming languages, particularly in the ease and security with which one may program concurrency. After a brief summary of occam's strengths, possible additional features are discussed, including recursion, source code modularity, exception response, and the automatic avoidance of deadlock. Consideration is then given to the inclusion of passive ('data') objects and the possibility of their movement between processes. Transfer primitives are proposed, alongside assignment and communication. Discussion is presented with regard to the potential for a new programming language, building on occam, while preserving its security and simplicity." } @InProceedings{BarnesWelch01, title = "{M}obile {D}ata, {D}ynamic {A}llocation and {Z}ero {A}liasing: {A}n occam {E}xperiment", author= "Welch, Peter H. and Barnes, Frederick R. M.", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "243--264", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "Traditional imperative languages (such as C) and modern object-oriented languages are plagued by uncontrolled resource aliasing problems. Add in concurrency and the problems compound exponentially. Improperly synchronised access to shared (i.e. aliased) resources leads to problems of race-hazard, deadlock, livelock and starvation. This paper describes the binding into occam (a concurrent processing language based on CSP) of a secure, dynamic and efficient way of sharing data between parallel processes with minimal synchronisation overheads. The key new facilities provided are: a movement semantics for assignment and communication, strict zero-aliasing, apparently dynamic memory allocation and automatic zero-or-very-small-unit-time garbage collection. The implementation of this mechanism is also presented, along with some initial performance figures (e.g. 80ns for mobile communication on an 800 MHz Pentium 3). With occam becoming available on a variety of microprocessors for GUI building, internet services and small-memory-footprint embedded products, these capabilities are timely. Lessons are drawn for concurrency back in OO languages - and especially for the JCSP (CSP for Java) package library." } @InProceedings{Barnes01, title = "tranx86 -- {A}n {O}ptimising {ETC} to {IA}32 {T}ranslator", author= "Barnes, Frederick R. M.", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "265--282", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "This paper describes tranx86, a program which converts Extended Transputer Code (ETC) from a modified Inmos occam compiler, into IA32 code for execution on the Intel i386 family of processors within the KRoC/Linux system. Several optimisations are employed in an attempt to maximise performance on this family of processors, including optimisations in the CCSP run-time kernel. These include a graph-colouring type register allocation scheme and various inlining of code. While tranx86 is mostly architecture dependent, effort has been made to allow the use of arbitrary schedulers, although currently CCSP is the only fully supported one. Various benchmark programs are used to compare the performance of this translator with the old system, giving significant time wins in some cases. For the commstime benchmark program on an 800 MHz Pentium-3, the old KRoC/Linux system gave 233 ns per communication (2 context switches); the new one, with optimisations and inlining, gives 67 ns per communication -- more than a 3-fold reduction in overheads." } @InProceedings{Teig01a, title = "{F}rom {S}afe {C}oncurrent {P}rocesses to {P}rocess-{C}lasses? {PLUSSING} {N}ew {C}ode by {ROLLING} out and {C}ompile?", author= "Teig, Øyvind", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "283--304", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "This article expands a concurrent language to support implementation inheritance by making block structures of the super process-class pluggable, and to interface inheritance by making the language's protocol inheritable. The parallel 'object-based' concurrent language occam 2 has been used as a catalyst for the concept, causing the language in fact to become (almost?) 'object-oriented' (OO). The result is white-box reuse between a 'process-class' and its sub process-class, and black-box reuse seen from the client side. Since occam is aliasing free and considered a 'safe' concurrent language, the expansion we discuss here keeps those properties - somewhat unusual for an OO system. This new language should be well suited in safety critical systems, since it has inherited the static (compile-time) and analysable properties from occam proper. Basically, two new keywords are defined: PLUSSING and ROLLING. The language feature suggestion is on sketch level only and therefore not complete, no BNF description exists and no compiler has been written." } @InProceedings{Teig01b, title = "{CHAN}nels to {D}eliver {M}emory? {MOBILE} {S}tructures and {ALT}ing over {M}emory?", author= "Teig, Øyvind", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "305--308", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "Memory objects are assigned to processes over a CHANnel like construct. This way one can wait for an object indefinitely, or with timeout in an ALT construct - coexisting with CHANnel inputs. The run-time SYSTEM will handle requests. Alternatively, a user memory handler process may use the underlying SYSTEM and serve other clients. Occam 2 is used as catalyst language." } @InProceedings{PedersenWagner01, title = "{P}rotocol {V}erification in {M}illipede", author= "Pedersen, Jan Bækgaard and Wagner, Alan", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "309--328", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "In this paper we present the MOPED module of the Millipede debugging system. Millipede is a multi-level debugging sytem for parallel message passing programs. MOPED allows the user to specify a protocol to which the communication of the program should adhere, and authomatically have all the messages sent in the system checked against the protocol. The specification language is small and easy to use, yet powerful enough to specify a wide range of protocols. Program variables can be passed easily to the verification module, allowing the construction of mode dynamic protocol specifications. Protocols can be specified incrementally, starting out very general working towards a more complex specification. Finally, the verification module can be run either online, that is, while the application is executing, or offline, using log files generated when the application was executed." } @InProceedings{Locke01, title = "{T}owards a {V}iable {A}lternative to {OO} -- {E}xtending the occam/{CSP} {P}rogramming {M}odel", author= "Locke, Tom", editor= "Chalmers, Alan G. and Mirmehdi, Majid and Muller, Henk", pages = "329--349", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2001", isbn= "1 58603 202 X", year= "2001", month= "sep", abstract= "Object orientation has become the de facto standard for large scale, general purpose software engineering. In this paper various aspects of object orientation that are against good software engineering practice are highlighted. It is then argued that a communicating process model provides a better platform for component based programming without the discussed pitfalls of OO. At the same time, current CSP based programming technology is shown to be seriously lacking when measured against certain aspects of object oriented languages. This paper is chiefly a discussion of ideas, ideas about extensions to the occam/CSP programming model that could advance the paradigm to the point where it provides a viable alternative to object orientation for general purpose, large scale software engineering. Specifically, three ideas are discussed: mobile processes, polymorphism and routable variant channels." } @InProceedings{Butterfie02, title = "{S}emantics of prialt in {H}andel-{C} (tm)", author= "Butterfield, Andrew", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "1--16", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "This paper discusses the semantics of the prialt construct in Handel-C. The language is essentially a static subset of C, augmented with a parallel construct and channel communication, as found in CSP. All assignments and channel communication events take one clock cycle, with all updates synchronised with the clock edge marking the cycle end. The behaviour of prialt in Handel-C is similar in concept to that of occam, and to the p-priority concept of Adrian Lawrence's CSPP. However, we have to contend with both input and output guards in Handel-C, unlike the situation in occam, although prialts with conflicting priority requirements are not legal in Handel-C. This makes our problem simpler than the more general case including such conflicts considered by Lawrence. We start with an informal discussion of the issues that arise when considering the semantics of Handel-C's prialt construct. We define a resolution function (R) that determines which requests in a collection of prialts become active. We describe a few properties that we expect to hold for resolution, and discuss the issue of compositionality." } @InProceedings{Lawrence02a, title = "{A}cceptances, {B}ehaviours and {I}nfinite {A}ctivity in {CSPP}", author= "Lawrence, Adrian E.", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "17--38", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "The denotational semantics presented here defines an extension of CSP called CSPP. It includes a full description of infinite behaviour in one simple model using only finite traces. This is true for both finite and infinite alphabets. The structure is a complete lattice, and so also a complete partial order, under refinement. Thus recursion is defined by fixed points in the usual way. It is also a complete restriction metric space so this provides an alternative treatment of recursion for contraction mappings." } @InProceedings{Lawrence02b, title = "{HCSP}: {I}mperative {S}tate and {T}rue {C}oncurrency", author= "Lawrence, Adrian E.", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "39--56", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "HCSP is an extension of CSPP which captures the semantics of hardware compilation. Because it is a superset of CSPP, it can describe both hardware and software and so is useful for co-design. The extensions beyond CSPP include: true concurrency; new hardware constructors; and a simple and natural way to represent imperative state. Both CSPP and HCSP were invented to cope with problems that arose while the author was trying to prove that the hardware that he had designed correctly implemented channels between a processor and an FPGA. Standard CSP did not capture priority, yet the circuits in the FPGA and the occam processes in the transputer both depended on priority for their correctness. The attempt to extend CSP rigorously to handle such problems of co-design has led to develoments that seem to have a much wider significance including a new way of unifying theories for imperative programming. This paper reports on the current state of HCSP and focuses on handling imperative state and true concurrency. The acceptance denotational semantics is described briefly." } @InProceedings{PascoeLoader02, title = "{C}onsolidating {T}he {A}greement {P}roblem {P}rotocol {V}erification {E}nvironment", author= "Pascoe, James S. and Loader, Roger J.", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "57--78", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "The Agreement Problem Protocol Verification Environment (APPROVE) has become a mature and robust platform for the automated verification of proposed solutions to agreement problems. APPROVE is based on the Spin model checker and leverages the literate programming tool noweb to provide Promela code supplied with LATEX documentation. The APPROVE discussion opened in Communicating Process Architectures 2001 and described the initial project phases and summarised some preliminary results. This paper presents a follow up, providing a canonical report on the development, application and insight gained from the project." } @InProceedings{BrodskyPedersen02, title = "{O}n the {C}omplexity of {B}uffer {A}llocation in {M}essage {P}assing {S}ystems", author= "Brodsky, Alex and Pedersen, Jan Bækgaard and Wagner, Alan", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "79--96", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "In modern cluster systems message passing functionality is often off-loaded to the network interface card for efficiency reasons. However, this limits the amount of memory available for message buffers. Unfortunately, buffer insufficiency can cause an otherwise correct program to deadlock, or at least slow down. Hence, given a program trace from an execution in an unrestricted environment, determining the minimum number of buffers needed for a safe execution is an important problem. We present three related problems, all concerned with buffer allocation for safe and efficient execution. We prove intractability results for the first two problems and present a polynomial time algorithm for the third." } @InProceedings{PedersenVinter02, title = "{J}ava {P}ast{S}et - {A} {S}tructured {D}istributed {S}hared {M}emory {S}ystem", author= "Pedersen, Kei Simon and Vinter, Brian", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "97--108", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "The architecture and performance of a Java implementation of a structured distributed shared memory system, PastSet, is described. The PastSet abstraction allows programmers to write applications that run efficiently on different architectures, from clusters to widely distributed systems. PastSet is a tuple-based three-dimensional structured distributed shared memory system, which provides the programmer with operations to perform causally ordered reads and writes of tuples to a virtual structured memory space called the PastSet. It has been shown that the original, native code, PastSet was able to outperform MPI and PVM when running real applications and we show that the design translates into Java so that Java PastSet is a qualified competitor to other cluster application programming interfaces for Java." } @InProceedings{Petitpier02, title = "{S}ynchronous {A}ctive {O}bjects {I}ntroduce {CSP}'s {P}rimitives in {J}ava", author= "Petitpierre, Claude", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "109--122", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "This paper presents a proposal of a language, based on synchronous active objects that introduces the CSP primitives into Java. The proposal does not use channels to realise the inter-process communications, but is shown to offer the same expressive power as the channel based solutions. The paper also shows that the rendezvous defined by CSP or our synchronous objects are very well adapted to the industrial development of event driven applications, handling simultaneously GUIs and accesses to remote applications." } @InProceedings{Bj\orndalenAnshus04, title = "{C}onfigurable {C}ollective {C}ommunication in {LAM}-{MPI}", author= "Bjørndalen, John Markus and Anshus, Otto J. and Aarsen, Tore and Vinter, Brian", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "123--134", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "In another paper, we observed that PastSet (our experimental tuple space system) was 1.83 times faster on global reductions than LAM-MPI. Our hypothesis was that this was due to the better resource usage of the PATHS framework (an extension to PastSet that supports orchestration and configuration) due to a mapping of the communication and operations which matched the computing resources and cluster topology better. This paper reports on an experiment to verify this and represents on-going work to add some of the same configurability of PastSet and PATHS to MPI. We show that by adding run-time configurable collective communication, we can reduce the latencies without recompiling the application source code. For the same cluster where we experienced the faster PastSet, we show that Allreduce with our configuration mechanism is 1.79 times faster than the original LAM-MPI Allreduce. We also experiment with the configuration mechanism on 3 different cluster platforms with 2-, 4-, and 8-way nodes. For the cluster of 8-way nodes, we show an improvement by a factor of 1.98 for Allreduce." } @InProceedings{DebattistVella02, title = "{C}ache-{A}ffinity {S}cheduling for {F}ine {G}rain {M}ultithreading", author= "Debattista, Kurt and Vella, Kevin and Cordina, Joseph", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "135--146", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "Cache utilisation is often very poor in multithreaded applications, due to the loss of data access locality incurred by frequent context switching. This problem is compounded on shared memory multiprocessors when dynamic load balancing is introduced and thread migration disrupts cache content. In this paper, we present a technique, which we refer to as *batching*, for reducing the negative impact of fine grain multithreading on cache performance. Prototype schedulers running on uniprocessors and shared memory multiprocessors are described, and finally experimental results which illustrate the improvements observed after applying our techniques are presented." } @InProceedings{CavalcantWoodcock02, title = "{A} {P}redicate {T}ransformer {S}emantics for a {C}oncurrent {L}anguage of {R}efinement", author= "Cavalcanti, Ana and Woodcock, Jim", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "147--166", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "Circus is a combination of Z and CSP; its chief distinguishing feature is the inclusion of the ideas of the refinement calculus. Our main objective is the definition of refinement methods for concurrent programs. The original semantic model for Circus is Hoare and He's unifying theories of programming. In this paper, we present an equivalent semantics based on predicate transformers. With this new model, we provide a more adequate basis for the formalisation of refinement and verification-condition generation rules. Furthermore, this new framework makes it possible to include logical variables and angelic nondeterminism in Circus. The consistency of the relational and predicate transformer models gives us confidence in their accuracy." } @InProceedings{Moseley02, title = "{R}econnetics: {A} {S}ystem for the {D}ynamic {I}mplementation of {M}obile {H}ardware {P}rocesses in {FPGA}s", author= "Moseley, Ralph", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "167--180", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "The capacity to utilise FPGA designs in such a way that they are compositional, mobile, and *interactive*, offers many new possibilities. This holds true for both research and commercial applications. With the system described here, hardware becomes as easy to distribute as software and the mediating links between the two domains allow for manipulation of physical resources in real time. Designs are no longer monolithic *images* downloaded at one time, but mobile entities that can be communicated over a distance and dynamically installed at run-time many times and at many places. Such twin domain designs can be as complex as a processor, or as small in scale as a few logic gates. The run-time system, Reconnetics, provides an environment of high-level control over such elements, which requires little knowledge of the underlying hardware technology." } @InProceedings{GreenAbdallah02, title = "{P}erformance {A}nalysis and {B}ehaviour {T}uning for {O}ptimisation of {C}ommunicating {S}ystems", author= "Green, Mark and Abdallah, Ali E.", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "181--190", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "Improving performance is the main driving force behind the use of parallel systems. Models for performance evaluation and techniques for performance optimisation are crucial for effectively exploiting the computational power of parallel systems. This paper focuses on methods for evaluating the performance of parallel applications built from components using the software architecture methodology. Minor differences in the low-level behaviour of functionally equivalent processing elements can have a dramatic effect upon the performance of the overall system; this confounds attempts to predict performance at any step prior to implementation. VisualNets is a tool supporting the construction and graphical manipulation of interacting systems built from components. It makes use of specifications in the formal method CSP, which enables the relevant component behaviours and the linkage between components to be concisely described. The tool allows the behaviour of the whole system over time, and the patterns of interaction between the components, to be visualised through graphical animation. The graphical display produced facilitates the analysis and evaluation of performance, and highlights areas where performance could be improved via better utilisation of parallel resources. VisualNets also allows the timing properties of the components and of the architecture that underlies them to be changed, to represent different component implementations or platform configurations. A case study, based on the dual pipeline architecture, is presented to show how the graphical animation capability of VisualNets can be used, firstly to evaluate performance, and secondly to guide the development of more efficient versions of the parallel system." } @InProceedings{Pugh02, title = "{C}onfiguration {D}iscovery and {M}apping of a {H}ome {N}etwork", author= "Pugh, Keith", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "191--202", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "A home network comprising many heterogeneous devices requires a scaleable interconnect capable of satisfying the often vastly different network resource demands of the devices. In addition, it is likely that over time the configuration of the network will change as new devices are added to the network and older ones removed or replaced. While it is acceptable for enterprise networks to be managed by a trained network administrator it is unreasonable to expect a home owner to have such expertise. Consequently, a free topology network coupled with a capacity for plug and play that allows nodes to be added anywhere, and at any time without interruption to the operation of the networked system are essential requirements. IEEE 1355 standard technology has the potential to satisfy these criteria. The demand for a free topology and a capacity for plug and play require that the configuration of the network is re-discovered and mapped automatically, and at regular intervals. This paper describes such a configuration mapping process." } @InProceedings{WelchVinter02, title = "{C}luster {C}omputing and {JCSP} {N}etworking", author= "Welch, Peter H. and Vinter, Brian", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "203--222", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "Hoare's algebra of Communicating Sequential Processes (CSP) enables a view of systems as layered networks of concurrent components, generating and responding to events communicated to each other through channels, barriers and other (formally defined) synchronisation primitives. The resulting image and discipline is close to hardware design and correspondingly easy to visualise, reason about, compose and scale. JCSP is a library of Java packages providing an (occam) extended version of this model that may be used alongside, or as a replacement for, the very different threads-and-monitors concurrency mechanisms built into Java. The current release (JCSP 1.0) supports concurrency within a single Java Virtual Machine (which may be multi-processor). This paper reports early experiments with JCSP.net, an extension of JCSP for the dynamic construction of CSP networks across distributed environments. The aims of JCSP.net are to simplify the construction and programming of dynamically distributed and parallel systems. It provides high-level support for CSP architectures, unifying concurrency logic within and between processors. The experiments are on some classical HPC problems, an area of work for which JCSP.net was not primarily designed. However, low overheads in the supporting infrastructure were a primary consideration * along with an intuitive and high-level distributed programming model (based on CSP). Results reported show JCSP holding up well against * and often exceeding * the performance obtained from existing tools such as mpiJava and IBM*s TSpaces. The experimental platform was a cluster of 16 dual-processor PIII Linux machines. It is expected that future optimisations in the pipeline for the JCSP.net infrastructure will improve the results presented here. JCSP and JCSP.net were developed at the University of Kent." } @InProceedings{SmithParsons02, title = "{V}iew-{C}entric {R}easoning for {L}inda and {T}uple {S}pace {C}omputation", author= "Smith, Marc L. and Parsons, Rebecca J. and Hughes, Charles E.", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "223--254", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "In contrast to sequential computation, concurrent computation gives rise to parallel events. Efforts to translate the history of concurrent computations into sequential event traces result in the potential uncertainty of the observed order of these events. Loosely coupled distributed systems complicate this uncertainty even further by introducing the element of multiple imperfect observers of these parallel events. Properties of such systems are difficult to reason about, and in some cases, attempts to prove safety or liveness lead to ambiguities. We present a survey of challenges of reasoning about properties of concurrent systems. We then propose a new approach, view-centric reasoning, that avoids the problem of translating concurrency into a se-quential representation. Finally. we demonstrate the usefulness of view-centric reasoning as a framework for disambiguating the meaning of tuple space predicate operations, versions of which exist commercially in IBM*s T Spaces and Sun*s JavaSpaces." } @InProceedings{Hilderink02, title = "{A} {G}raphical {M}odeling {L}anguage for {S}pecifying {C}oncurrency based on {CSP}", author= "Hilderink, Gerald H.", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "255--284", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "In this paper, we introduce a graphical specification language for modeling concurrency in software design. The language notations are derived from CSP and the resulting designs form so-called CSP diagrams. The notations reflect data-flow aspects, control-flow aspects, and they reflect CSP algebraic expressions that can be used for formal analysis. The designer does not have to be aware of the underlying mathematics. The techniques and rules presented provide guidance to the development of concurrent software architectures. One can detect and reason about compositional conflicts (errors in design), potential deadlocks (errors at run-time), and priority inversion problems (performance burden) at a high level of abstraction. The CSP diagram collaborates with object-oriented and structured methods. The CSP diagram is UMLable and can be presented as a new process diagram for the UML to capture concurrent, real-time, and event-flow oriented software architectures. The extension to the UML is not presented in this paper." } @InProceedings{East02, title = "{T}he '{H}oneysuckle' {P}rogramming {L}anguage: {E}vent and {P}rocess", author= "East, Ian R.", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "285--300", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "A new language for programming systems with Communicating Process Architecture is introduced which builds upon the success of occam. Some of the principal objectives are presented and justified. The means employed to express behaviour are then described, including a transfer primitive, which conveys object ownership as well as value, and an alternation construct. The latter replaces PRI PAR and PRI ALT, and affords explicit expression of conflict-free prioritized reactive (event-driven) behaviour, including exception response. HPL also offers source-code modularity, object encapsulation, and the recursive definition of both object and process. Despite such ambition, a primary aim has been to retain simplicity in abstraction, expression, and implementation." } @InProceedings{BroeninkHilderink02, title = "{A} {C}ommunicating {T}hreads {C}ase {S}tudy: {JIWY}", author= "Broenink, Jan F. and Hilderink, Gerald H. and Jovanovic, Dusko S.", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "311--320", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "We strive to allow a control system designer the power of designing control computer code concurrently and generating it efficiently, in spite of her or his lack of skills in software engineering. This is important for many reasons. Nowdays, it is impossible to separate control engineering from software engineering. There is no way of implementing control strategies other than to transform them into computer code for the chosen processing target. Usually, there are not so many general-purpose programmers available in control engineering research teams in companies and universities. In these cases, software development techniques suffer from insufficient knowledge in disciplines of software modelling, concurrency, reusability and testing. This paper develops a case study whose solution is based upon the CSP principles supported by the Communicating Threads libraries developed at Twente and argues why the techniques are accessible to non-computing-specialist control engineers." } @InProceedings{BarnesWelch02a, title = "{P}rioritised {D}ynamic {C}ommunicating {P}rocesses - {P}art {I}", author= "Barnes, Frederick R. M. and Welch, Peter H.", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "321--352", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "This paper reports continuing research on language design, compilation and kernel support for highly dynamic concurrent reactive systems. The work extends the occam multiprocessing language, which is both sufficiently small to allow for easy experimentation and sufficiently powerful to yield results that are directly applicable to a wide range of industrial and commercial practice. Classical occam was designed for embedded systems and enforced a number of constraints * such as statically pre-determined memory allocation and concurrency limits * that were relevant to that generation of application and hardware technology. Most of these constraints have been removed in this work and a number of new facilities introduced (channel structures, mobile channels, channel ends, dynamic process creation, extended rendezvous and process priorities) that significantly broaden occam*s field of application and raise the level of concurrent system design directly supported. Four principles were set for modifications/enhancements of the language. They must be useful and easy to use. They must be semantically sound and policed (ideally, at compile-time) to prevent mis-use. They must have very lightweight and fast implementation. Finally, they must be aligned with the concurrency model of the original core language, must not damage its security and must not add (significantly) to the ultra-low overheads. These principles have all been observed. All these enhancements are available in the latest release (1.3.3) of KRoC, freely available (GPL/open source) from: http://www.cs.ukc.ac.uk/projects/ofa/kroc/." } @InProceedings{BarnesWelch02b, title = "{P}rioritised {D}ynamic {C}ommunicating {P}rocesses - {P}art {II}", author= "Barnes, Frederick R. M. and Welch, Peter H.", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "353--370", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "This paper illustrates the work presented in 'Part I', giving additional examples of use of channel-types, extended rendezvous and FORKs that lean towards real applications. Also presented are a number of other additions and extensions to the occam language that correct, tidy up or complete facilities that have long existed. These include fixing the PRI ALT bug, allowing an unconditional SKIP guard as the last in a PRI ALT, replicator STEP sizes, run-time computed PAR replication counts, RESULT parameters and abbreviations, nested PROTOCOL definitions, inline array constructors and parallel recursion. All are available in the latest release (1.3.3) of KRoC, freely available (GPL/open source) from: http://www.cs.ukc.ac.uk/projects/ofa/kroc/." } @InProceedings{SouzaPfitscher02, title = "{I}mplementing a {D}istributed {A}lgorithm for {D}etection of {L}ocal {K}nots and {C}ycles in {D}irected {G}raphs", author= "Souza, Geraldo Pereira de and Pfitscher, Gerson Henrique", editor= "Pascoe, James S. and Loader, Roger J. and Sunderam, Vaidy S.", pages = "371--386", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2002", isbn= "1 58603 268 2", year= "2002", month= "sep", abstract= "In general, most deadlocks take form of cycles (in database systems) and knots (in communication systems). Boukerche and Tropper have proposed a distributed algorithm to detect cycles and knots in generic graphs. Their algorithm has a message complexity of 2m vs. (at least) 4m for the Chandy and Misra algorithm, where m is the number of links in the graph, and requires O (n log n) bits of memory, where n is the number of nodes. We have implemented Boukerche's algorithm. Our implementation of the algorithm is based on the construction of processes of the CSP model. The implementation was done using JCSP, an implementation of CSP for Java." } @InProceedings{SchallerMarshall03, title = "{A} {C}omparison of {H}igh {P}erformance, {P}arallel {C}omputing {J}ava {P}ackages", author= "Schaller, Nan C. and Marshall, Sidney W. and Cho, Yu-Fong", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "1--16", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "The high-performance computing community has developed numerous Java packages that support parallel and distributed computing. Most of these packages are designed for the typical parallel message passing and shared memory architectural paradigms. This paper presents the results of a recent study that included a web search for such packages, describes the paradigms implemented in them, and evaluates their performance on a parallel, 4-processor SMP machine using three benchmark programs that represent a mix of typical parallel applications, chosen from The Java Grande Benchmark Suite. A brief description of each package and a discussion its ease of installation and use are also provided." } @InProceedings{Petitpier03, title = "{A} {D}evelopment {M}ethod {B}oosted by {S}ynchronous {A}ctive {O}bjects", author= "Petitpierre, Claude", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "17--32", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "This paper presents a novel development method for interactive and distributedapplications. The benefit that this method provides is that the design gives clearguidance towards the implementation. The method is based on three mainelements: a concept of synchronous active objects that is closely related to thatfound in CSP; the Java environment; and a selection of the diagrams defined byUML. This approach alleviates many of the most serious problems that areencountered when using GUI builders, which hide the application structures andso make it difficult to devise sound architectures. The final part of the paper brieflydescribes an application generator that will help a developer to implement a designwhich is developed according to the approach advocated here." } @InProceedings{East03, title = "{T}utorial: {P}rioritised {S}ervice {A}rchitecture using {H}oneysuckle", author= "East, Ian R.", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "33--36", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "An update will be presented on the progress in establishing the Honeysuckleprogramming language [1] and its formal foundations. The latter are formallyaddressed in a paper currently under review for journal publication [2], but willbe summarised. They include formal definitions of service protocol plus servicenetwork/component (SNC) and the PSA design rule (PSADR), from which aproof of a priori deadlock-freedom emerges directly. Freedom from priority conflict(and thus inversion) is also easily guaranteed. Closure in the definition of systemand component guarantees true compositionality under both concurrency andprioritised alternation." } @InProceedings{ArrantssoVinter03, title = "{T}he {G}rid {B}lock {D}evice", author= "Arrantsson, Bardur and Vinter, Brian", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "37--48", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "In this paper we propose a distributed, replicated block device for The Gridbased on the the replication algorithm of Y. Amir[1]. The end goal is to supportapplication-specified semantics, both wrt. replication strategy and the consistencymodel used for reads and writes.We list the proposed features of the Grid Block Device and discuss various methodsof implementation." } @InProceedings{HappeVinter03, title = "{D}istributed {S}hared {M}emory in {G}lobal {A}rea {N}etworks", author= "Happe, Hans Henrik and Vinter, Brian", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "49--62", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "Distributed Shared Memory (DSM) has many advantages in heterogeneousenvironments, such as geographically distant clusters or The Grid. These includes:locality utilization and replication transparency. The fact that processes communicateindirectly through memory rather than directly, is giving DSM these advantages.This paper presents the design of Global PastSet (GPS) which is a DSM systemtargeted at global area networks. GPS is based on the DSM system PastSet [1] that hasbeen very effective in homogeneous cluster environments. GPS utilizes consistencycontrol migration and replication to scale in heterogeneous environments. This hasresulted in a token-based mutual exclusion algorithm that considers locality and analgorithm for locating replicas. GPS has been simulated in multi-cluster environmentswith up to 2048 nodes with very promising results." } @InProceedings{RajuRong03, title = "{A}utomatic {C}onversion of {CSP} to {CTJ}, {JCSP}, and {CCSP}", author= "Raju, V. and Rong, L. and Stiles, G. S.", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "63--81", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "We present tools that automatically convert a subset of machine-readable CSPscript to executable Java or C code. CSP is used to design and verify thecorrectness of large and complex systems of processes that interact only viaexplicit synchronous messages. These systems can be implemented in Javausing CTJ or JCSP, packages that add CSP-like features to Java, or in CCSP, apackage that adds similar features to standard C. Implementation of CSP systemscan be tedious and error-prone when large numbers of processes andcommunications are involved, and sorting out errors in channel naming or theordering of messages can be very time-consuming. The tools we have developedminimize such problems by converting the verified CSP descriptions ofcommunicating processes directly into Java or C code, thus guaranteeing thatchannels are correctly named and the communications occur in the proper order.This process can significantly cut development time." } @InProceedings{ONeillMoore03, title = "{A} {S}ingle {C}hip {S}olution for {D}istributed {P}rocessing {S}ystems", author= "O'Neill, Brian C. and Moore, P.W. and Clark, S.", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "83--90", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "This paper describes a processor and an inter-processor communications interfaceintegrated on a single chip for use in a distributed processing system. The system isbased on work of the electronic systems design and parallel processing group at theNottingham Trent University. The four main elements of the chip design areprocessor, memory, communication interface and packet routing switch all integratedunto one chip. This design is achieved by the use of the ALTERA ARM basedExcalibur system on a programmable chip (SOPC) containing an embedded processorand programmable logic. The paper describes the communication features andimplementation carried out by the research group to achieve this single chip processor." } @InProceedings{SmithHughes03, title = "{T}he denotational {S}emantics of {V}iew-{C}entric {R}easoning", author= "Smith, Marc L. and Hughes, Charles E. and Burke, Kyle W.", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "91--98", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "Both Lawrence’s HCSP [1] and Smith, et al’s VCR [2] (an earlier versionappears in [3]) extend CSP [4] with representations of truly concurrent events. Previously,VCR was described using an operational semantics, while the semantics ofHCSP’s Acceptances model, like those of the predominant CSP models described byRoscoe [5] (e.g., Traces, Failures / Divergences), are denotational. We now present adenotational semantics for VCRand, in so doing, propose an extension toHCSP (andpossibly other existing CSP models) to support View-Centric Reasoning. This workbrings VCR a step closer to being drawn within Hoare and He’s Unifying Theories ofProgramming [6] for further comparisons." } @InProceedings{Lawrence03, title = "{O}vertures and hesitant offers: hiding in {CSPP}", author= "Lawrence, Adrian E.", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "97--109", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "Hiding is an important and characteristic part of CSP. Defining it in thepresence of priority for CSPP needs care. The ideas of overtures and hesitant offersintroduced here arise naturally in the context of Acceptances. They provide clearinsight into the behaviour of hidden processes. And particularly illuminate the originof the nondeterminism which frequently arises from hiding.Keywords: CSP; CSPP; Denotational semantics; formal methods; concurrency; parallelsystems; occam; hardware compilation; priority; hiding." } @InProceedings{HilderinkBroenink03, title = "{S}ampling and timing a task for the environmental process", author= "Hilderink, Gerald H. and Broenink, Jan F.", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "111--124", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "Sampling and timing is considered a responsibility of the environment ofcontroller software. In this paper we will illustrate a concept whereby anenvironmental process and multi-way events play an important role in applyingtiming for untimed CSP software architectures. We use this timing concept forbuilding our control applications based on CSP concepts and with our CSP for C++(CTC++) library. We present a concept of sampling of control applications that isorthogonal to the application. This implies global timing on the basis of timedevents. We also support traditional local timing on the based of timed processes," } @InProceedings{DullerPanesar03, title = "{P}arallel {P}rocessing - the pico{C}hip way!", author= "Duller, Andrew and Panesar, Gajinder and Towner, Daniel", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "125--138", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "This paper describes a new approach to parallel processing within thewell targetted application domain of wireless communications systems, using thepicoArrayTM. The picoArrayTM is a tiled-processor architecture, containing 430 heterogeneousprocessors, connected through a novel, compile-time scheduled interconnect.We show how the features of the picoArrayTM allow deterministic processing tobe achieved, and how the tool chain allows programming to be performed effectivelyin a combination of high level assembly language and C. By handling a wide varietyof types of processing within the picoArrayTM a single design flow can be usedto produce complex communications systems. The effectiveness of this approach isdemonstrated through the use of the picoArrayTM to build a working 3G base-station." } @InProceedings{BrownWelch03, title = "{A}n {I}ntroduction to the {K}ent {C}++{CSP} {L}ibrary", author= "Brown, Neil C.C. and Welch, Peter H.", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "139--156", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "This paper reports on a CSP library for C++, developed over the past yearat the University of Kent. It is based on the OO-design and API of JCSP and thelightweight algorithms of KRoC occam, with extensions to exploit specific C++ capabilities(such as templates). Both user-level and operating system threads are usedto provide a range of implementation options and semantics (e.g. for managing blockingsystem calls intelligently) that run efficiently under eitherWindows or Linux. Thelibrary is presented from the user’s point of view, mainly by way of a tutorial. Implementationdetails are also outlined and some benchmark results given. The performanceof C++CSP is between that of KRoC occam and JCSP — fairly close toKRoC." } @InProceedings{GonzalezBustacara03, title = "{A}gents for {C}oncurrent {P}rogramming", author= "Gonzalez, Enrique and Bustacara, Cesar and Avila, Jamir", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "157--166", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "This paper aims to demonstrate that concepts from Distributed Artificial Intelligence are very useful to design concurrent systems. The BESA framework and the AOPOA methodology are introduced as tools to achieve this goal. The Behavior-oriented, Event-driven and Social-based Agent (BESA) framework combines the concepts of MultiAgent Systems with the design of concurrent systems: an agent can be constructed as a set of behaviors; the notion of behaviors can be directly applied to concurrent systems design using the Agent Oriented Programming paradigm. The internal architecture of a BESA agent integrates two important features: a modular composition of behaviors and an event dispatcher based in a select like mechanism. The Agent Oriented Programming based in an Organizational Approach (AOPOA) methodology provides a systematic procedure to build complex system based in three concepts: a hierarchical recursive decomposition of the system, a goal-oriented role identification, and an evolution of the cooperation relationships linking the system components." } @InProceedings{NicoleEllis03, title = "occam for reliable embedded systems: lightweight runtime and model checking", author= "Nicole, Denis A. and Ellis, Sam and Hancock, Simon", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "167--172", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "We describe some more recent developments of the SPoC system. We describe a new module in the occam compiler which performs substantial simplifications of the run-time demands made by the compiled code. This has been used successfully both to target a simple PIC microcontroller and to generate input for the SMV model checker." } @InProceedings{CampbellStiles03, title = "{T}he {T}rebuchet", author= "Campbell, John and Stiles, G. S.", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "173--183", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "The Trebuchet is a hardware architecture for machines implementedfrom conventional software source programs. It is pseudo-asynchronous in that itdecouples the system clock from the computational logic, reducingelectromagnetic interference, smoothing current draw, and reducing pipelinelatency, key benefits of asynchronous designs. Performance of example programsis given." } @InProceedings{Boosten03, title = "{F}ormal {C}ontracts: {E}nabling {C}omponent {C}omposition", author= "Boosten, Marcel", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "185--197", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "Traditional component interaction is based on interface calls and callbacks. Such interaction can introduce integration faults, i.e., side effects at the moment of component integration. Solutions to such problems can be hard to apply, and may require drastic changes in the design of the involved components. This paper introduces Formal Contracts, a software construct that allows side-effect free component interaction, and thereby avoids the introduction of integration faults. Furthermore, via a state machine representing the inter-component contract, Formal Contracts, in addition to the static aspects, formally specify the dynamic aspects of component interaction. Formal Contracts are a pragmatic software mechanism that supports the full development cycle: from the specification and decomposition until the debugging, composition, and test of a system." } @InProceedings{SchweigleBarnes03, title = "{F}lexible, {T}ransparent and {D}ynamic occam {N}etworking {W}ith {KR}o{C}.net", author= "Schweigler, Mario and Barnes, Frederick R. M. and Welch, Peter H.", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "199--224", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "KRoC.net is an extension to KRoC supporting the distribution of occamchannels over networks, including the internet. Starting in 2001, the development ofKRoC.net has gone through a number of stages, each one making the system moreflexible, transparent and dynamic. It now enables the occam programmer to set upand close network channels dynamically. Configuration has been simplified. All occamPROTOCOLs can now be sent over network channels, without need for conversion.Many of the new dynamic features in occam have been used to improve KRoC.net.Many of the concepts in KRoC.net are similar to those in the JCSP Network Edition(JCSP.net), KRoC.net’s counterpart in the JCSP world. This paper will give an overviewover KRoC.net, its usage, its design and implementation, and its future. It willalso provide some benchmarks and discuss how the new occam features are beingused in the latest KRoC.net version." } @InProceedings{CronieHoeksema03, title = "{A} {CSP}-based {P}rocessing {A}rchitecture for a {F}lexible {MIMO}-{OFDM} {T}estbed", author= "Cronie, H. S. and Hoeksema, F. W. and Slump, C. H.", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "225--233", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "Future wireless communication systems require novel techniques to increasethe bitrate, coverage and mobility. One of these techniques is spatial multiplexingand we have investigated the use of a CSP-based kernel in the implementation ofa spatial multiplexing testbed. It turns out that the use of the CSP-based kernel notonly provides a good way of system modeling, but also provides a very scalable softwarearchitecture for the testbed. In future, we can change several system parameterswithout changing the software architecture. With the testbed we were able to verifythe concept of spatial multiplexing in an office environment." } @InProceedings{OrlicBroenink03, title = "{R}eal-time and fault tolerance in distributed control software", author= "Orlic, Bojan and Broenink, Jan F.", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "235--250", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "Closed loop control systems typically contain multitude of spatially distributed sensors and actuators operated simultaneously. So those systems are parallel and distributed in their essence. But mapping this parallelism onto the given distributed hardware architecture, brings in some additional requirements: safe multithreading, optimal process allocation, real-time scheduling of bus and network resources. Nowadays, fault tolerance methods and fast even online reconfiguration are becoming increasingly important. All those often conflicting requirements, make design and implementation of real-time distributed control systems an extremely difficult task, that requires substantial knowledge in several areas of control and computer science. Although many design methods have been proposed so far, none of them had succeeded to cover all important aspects of the problem at hand. [1] Continuous increase of production in embedded market, makes a simple and natural design methodology for real-time systems needed more then ever." } @InProceedings{Barnes03, title = "occwserv: {A}n occam {W}eb-{S}erver", author= "Barnes, Frederick R. M.", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "251--268", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "This paper presents ‘occwserv’, the occam web-server. This is a highlyconcurrent web-server, written in the occam multi-processing language, that supportsthe majority of the HTTP/1.1 protocol. Dynamic process and channel creation mechanismsare used to create scalable ‘server-farms’, each responsible for a particular webserverfunction - for example, reading client requests or running CGI processes. Thedesign of the web-server is presented, along with some early performance benchmarkresults. Although performance may appear a limiting factor (when compared to otherweb-servers such as Apache), much is gained from the simplicity and security of occam.Extending the web-server with new functionality, for example, is intuitive andlargely trivial - with the guarantees that code is free from race-hazard and aliasingerrors. An experimental non-standard addition, the OGI (occam Gateway Interface),is also presented. This provides a mechanism for dynamically loading and attachingpre-compiled occam processes to the running web-server, that can then handle oneor multiple client connections. A text-based style adventure game is examined briefly,that allows multiple clients to interact within a \"multi-user dungeon\" (MUD) styleenvironment." } @InProceedings{BarnesJacobson03, title = "{RM}o{X}: {A} raw-metal occam {E}xperiment", author= "Jacobsen, Christian L. and Barnes, Frederick R. M. and Vinter, Brian", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "269--288", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "Operating-systems are the core software component of many modern computersystems, ranging from small specialised embedded systems through to largedistributed operating-systems. This paper presents RMoX: a highly concurrent CSPbasedoperating-system written in occam. The motivation for this stems from theoverwhelming need for reliable, secure and scalable operating-systems. The majorityof operating-systems are written in C, a language that easily offers the level offlexibility required (for example, interfacing with assembly routines). C compilers,however, provide little or no mechanism to guard against race-hazard and aliasing errors,that can lead to catastrophic run-time failure (as well as to more subtle errors,such as security loop-holes). The RMoX operating-system presents a novel approachto operating-system design (although this is not the first CSP-based operating-system).Concurrency is utilised at all levels, resulting in a system design that is well defined,easily understood and scalable. The implementation, using the KRoC extended occam,provides guarantees of freedom from race-hazard and aliasing errors, and makesextensive use of the recently added support for dynamic process creation and channelmobility. Whilst targeted at mainstream computing, the ideas and methods presentedare equally applicable for small-scale embedded systems - where advantage can bemade of the lightweight nature of RMoX (providing fast interrupt responses, for example)." } @InProceedings{ArvindSoteloSal03, title = "{S}cheduling for {ILP} in the '{P}rocessor-as-a-{N}etwork'", author= "Arvind, D.K. and Sotelo-Salazar, S.", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "289--304", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "This paper explores the idea of the processor as an asynchronous network,called the micronet, of functional units which compute concurrently and communicateasynchronously. A micronet-based asynchronous processor exposes spatial as well astemporal concurrency. We analyse the performance of the ‘processor-as-a-network’by comparing three scheduling algorithms for exploiting Instruction Level Parallelism(ILP). Schedulers for synchronous architectures have relied on deterministic instructionexecution times. In contrast, ILP scheduling in micronet-based architectures is achallenge as it is less certain in advance when instructions start execution and whenresults become available. Performance results comparing the three schedulers are presentedfor SPEC95 benchmarks executing on a cycle-accurate model of the micronetarchitecture." } @InProceedings{Moore03, title = "{A}ccurate {C}alculation of {D}eme {S}izes for a {P}arallel {G}enetic {S}cheduling {A}lgorithm", author= "Moore, M.", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "305--313", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "The accuracies of three equations to determine the size of populations for serial and parallel genetic algorithms are evaluated when applied to a parallel genetic algorithm that schedules tasks on a cluster of computers connected via shared bus. This NP-complete problem is representative of a variety of optimisation problems for which genetic algorithms (GAs) have been shown to effectively approximate the optimal solution. However, empirical determination of parameters needed by both serial and parallel GAs is time-consuming, often impractically so in production environments. The ability to predetermine parameter values mathematically eliminates this difficulty. The parameter that exerts the most influence over the solution quality of a parallel genetic algorithm is the population size of the demes. Comparisons here show that the most accurate equation for the scheduling application is Cant\`{u}-Paz' serial population sizing calculation based on the gambler's ruin model [1]. The study presented below is part of an ongoing analysis of the effectiveness of parallel genetic algorithm parameter value computations based on schema theory. The study demonstrates that the correct deme size can be predetermined quantitatively for the scheduling problem presented here, and suggests that this may also be true for similar optimisation problems. This work is supported by NASA Grant NAG9-140." } @InProceedings{HilderinkJovanovic03, title = "{A} multimodal robotic control law modelled and implemented by the {CSP} - {GML}/{CT} framework", author= "Hilderink, Gerald H. and Jovanovic, Dusko S. and Broenink, Jan F.", editor= "Broenink, Jan F. and Hilderink, Gerald H.", pages = "315--334", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2003", isbn= "1 58603 381 6", year= "2003", month= "sep", abstract= "We use several formal methodologies for developing control applicationsat our Control Engineering research group. An important methodology we use fordesigning and implementing control software architecture is based on CSP concepts.These concepts allow us to glue multidisciplinary activities together and allow forformal stepwise refinement from design down to its implementation. This paperillustrates a trajectory and shows the usefulness of CSP diagrams for a simplemechatronic system. The simulation tool 20-SIM is used for creating the controllaws and our CTC++ package is used for coding in C++." } @InProceedings{Roscoe04, title = "{F}initary {R}efinement {C}hecks for {I}nfinitary {S}pecifications", author= "Roscoe, A. W.", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "1--18", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "We see how refinement against a variety of infinite-state CSP specifications can be translated into finitary refinement checks. Methods used include turning a process into its own specification inductively, and we recall Wolper's discovery that data independence can be used for this purpose." } @InProceedings{PhillipsStiles04, title = "{A}n {A}utomatic {T}ranslation of {CSP} to {H}andel-{C}", author= "Phillips, Jonathan D. and Stiles, G. S.", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "19--38", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "We present tools that convert a subset of CSP into Handel-C code. Handel-C is similar to the standard C programming language, and can be itself converted to produce files to program an FPGA. We thus now have a process that can directly generate hardware from a verified high-level description. The CSP to Handel-C translator makes use of the Lex and Yacc programming tools. The Handel-C code produced is functional, but not necessarily optimized for all situations. The translator has been tested using several CSP scripts of varying complexity. The functionality of the resulting Handel-C programs has been verified with simulations, and two scripts were further checked with successful implementations on an FPGA." } @InProceedings{Peschansk04, title = "{O}n {L}inear {T}ime and {C}ongruence in {C}hannel-{P}assing {C}alculi", author= "Peschanski, Frederic", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "39--54", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "Process algebras such as CSP or the Pi-calculus are theories to reason about concurrent software. The Pi-calculus also introduces channel passing to address specific issues in mobility. Despite their similarity, the languages expose salient divergences at the formal level. CSP is built upon trace semantics while labelled transition systems and bisimulation are the privileged tools to discuss the Pi-calculus semantics. In this paper, we try to bring closer both approaches at the theoretical level by showing that proper trace semantics can be built upon the Pi-calculus. Moreover, by introducing locations, we obtain the same discriminative power for both the trace and bisimulation equivalences, in the particular case of early semantics. In a second part, we propose to develop the semantics of a slightly modified language directly in terms of traces. This language retains the full expressive power of the Pi-calculus and most notably supports channel passing. Interestingly, the resulting equivalence, obtained from late semantics, exhibits a nice congruence property over process expressions." } @InProceedings{East04a, title = "{P}rioritised {S}ervice {A}rchitecture", author= "East, Ian R.", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "55--70", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "Previously, Martin gave formal conditions under which a simple design rule guarantees deadlock-freedom in a system with service (client-server) architecture. Both conditions and design rule may be statically verified. Here, they are re-arranged to define service protocol, service network (system), and service network component, which together form a model for system abstraction. Adding mutual exclusion of service provision and dependency between service connections enriches abstraction and is shown to afford compositionality. Prioritised alternation of service provision further enriches abstraction while retaining deadlock-freedom and denying priority conflict, given appropriate new design rules." } @InProceedings{DullerPanesar04, title = "{D}ebugging and {V}erification of {P}arallel {S}ystems - the pico{C}hip {W}ay", author= "Duller, Andrew and Panesar, Gajinder and Towner, Daniel", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "71--84", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "This paper describes the methods that have been developed for debugging and verifying systems using devices from the picoArray(TM) family. In order to increase the computational ability of these devices the hardware debugging support has been kept to a minimum and the methods and tools described take this into account. An example of how some of these methods have been used to produce an 802.16 system is given. The important features of the new PC102 device are outlined." } @InProceedings{ClaytonKerridge04, title = "{A}ctive {S}erial {P}ort: {A} {C}omponent for {JCSPN}et {E}mbedded {S}ystems", author= "Clayton, Sarah and Kerridge, Jon", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "85--98", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "The javax.comm package provides basic low-level access between Java programs and external input-output devices, in particular, serial devices. Such communications are handled using event listener technology similar to that used in the AWT package. Using the implementation of active AWT components as a model we have constructed an active serial port (ASP), using javax.comm, that gives a channel interface that is more easily incorporated into a JCSPNet collection of processes. The ASP has been tested in a real-time embedded system used to collect data from infrared detectors used to monitor the movement of pedestrians. The collected data is transferred across an Ethernet from the serial port process to the data manipulation processes. The performance of the JCSPNet based system has been compared with that supplied by the manufacturer of the detector and we conclude by showing how a complete monitoring system could be constructed in a scalable manner." } @InProceedings{JacobsonJadud04, title = "{T}he {T}ransterpreter: {A} {T}ransputer {I}nterpreter", author= "Jacobsen, Christian L. and Jadud, Matthew C.", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "99--106", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "We have written the Transterpreter, a virtual machine for executing the transputer instruction set. This interpreter is a small, portable, and extensible run-time, intended to be easily ported to handheld computers, mobile phones, and other embedded contexts. In striving for this level of portability, occam programs compiled to Transputer byte-code can currently be run on desktop computers, handhelds, and even the LEGO Mindstorms robotics kit." } @InProceedings{Schweigle04, title = "{A}dding {M}obility to {N}etworked {C}hannel-{T}ypes", author= "Schweigler, Mario", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "107--126", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "This paper reports the specification of a sound concept for the mobility of network-channel-types in KROC.net. The syntax and semantics of KROC.net have also been modified in order to integrate it more seamlessly into the occam-pi language. These new features are currently in the process of being implemented. Recent developments in occam-pi and KROC (such as mobile processes and live / dead channel-type-ends) are described, together with their impact on KROC.net. This paper gives an overview of the recent developments in KROC.net, and presents its proposed final semantics, as well as the proposed interface between the KROC.net infrastructure and the KROC compiler." } @InProceedings{VinterBj\orndalen04, title = "{A} {C}omparison of {T}hree {MPI} {I}mplementations", author= "Vinter, Brian and Bjørndalen, John Markus", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "127--136", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "Various implementations of MPI are becoming available as MPI is slowly emerging as the standard API for parallel programming on most platforms. The open source implementations LAM-MPI and MPICH are the most widely used, while commercial implementations are usually tied to special hardware platforms. This paper compares these two open-source MPI-implementations to one of the commercially available implementations, MESH-MPI from MESH-Technologies. We find that the commercial implementation is significantly faster than the open-source implementations, though LAM-MPI does come out on top in some benchmarks." } @InProceedings{HappeVinter04, title = "{A}n {E}valuation of {I}nter-{S}witch {C}onnections", author= "Happe, Hans Henrik and Vinter, Brian", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "137--146", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "In very large clusters it is not possible to get Ethernet switches that are large enough to support the whole cluster, thus a configuration with multiple switches are needed. This work seeks to evaluate the interconnection strategies for a new 300+ CPU cluster at the University of Southern Denmark. The focal point is a very inexpensive switch from D-Link which unfortunately offers only 24 Gb ports. We investigate different inter-switch connections and their impact at application level." } @InProceedings{Lawrence04a, title = "{O}bserving {P}rocesses", author= "Lawrence, Adrian E.", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "147--156", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "This paper discusses the sorts of observations of processes that are appropriate to capture priority. The standard denotational semantics for CSP are based around observations of traces and refusals. Choosing to record a little more detail allows extensions of CSP which describe some very general processes including those that include priority. A minimal set of observations yields a language and semantics remarkably close to the standard Failures-Divergences model of CSP which is described in a companion paper. A slightly richer set of observations yields a somewhat less abstract language." } @InProceedings{Lawrence04b, title = "{T}riples", author= "Lawrence, Adrian E.", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "157--184", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "The most abstract form of acceptance semantics for a variant of CSPP is outlined. It encompasses processes which may involve priority, but covers a much wider class of systems including real time behaviour. It shares many of the features of the standard Failures-Divergences treatment: thus it is only a Complete Partial Order when the alphabet of events is finite." } @InProceedings{Brown04, title = "{C}++{CSP} {N}etworked", author= "Brown, Neil C.C.", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "185--200", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "One year ago, the Kent C++CSP Library was presented at this conference. C++CSP is an implementation of CSP ideas in C++. After it was presented, C++CSP was released to the world at large under the Lesser GNU Public Licence. It had always been the author's intention to develop a network capability in the library. This paper details the development of a network capability for the library and the results of benchmarks, which are encouragingly fast." } @InProceedings{BarnesWelch04, title = "{C}ommunicating {M}obile {P}rocesses", author= "Barnes, Frederick R. M. and Welch, Peter H.", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "201--218", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "This paper presents a new model for mobile processes in occam-pi. A process, embedded anywhere in a dynamically evolving network, may suspend itself mid-execution, be safely disconnected from its local environment, moved (by communication along a channel), reconnected to a new environment and reactivated. Upon reactivation, the process resumes execution from the same state (i.e. data values and code positions) it held when it suspended. Its view of its environment is unchanged, since that is abstracted by its synchronisation (e.g. channels and barriers) interface and that remains constant. The environment behind that interface will (usually) be completely different. The mobile process itself may contain any number of levels of dynamic sub-network. This model is simpler and, in some ways, more powerful than our earlier proposal, which required a process to terminate before it could be moved. Its formal semantics and implementation, however, throw up extra challenges. We present details and performance of an initial implementation." } @InProceedings{MartinTiskin04, title = "{D}ynamic {BSP}: {T}owards a {F}lexible {A}pproach to {P}arallel {C}omputing over the {G}rid", author= "Martin, Jeremy M. R. and Tiskin, Alex V.", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "219--226", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "The Bulk Synchronous model of parallel programming has proved to be a successful paradigm for developing portable, scalable, high performance software. Originally developed for use with traditional supercomputers, it was later applied to networks of workstations. Following the emergence of grid computing, new programming models are needed to exploit its potential. We consider the main issues relating to adapting BSP for this purpose, and propose a new model Dynamic BSP, which brings together many elements from previous work in order to deal with quality-of-service and heterogeneity issues. Our approach uses a task-farmed implementation of supersteps." } @InProceedings{Goldsmith04, title = "{CSP}: {T}he {B}est {C}oncurrent-{S}ystem {D}escription {L}anguage in the {W}orld - {P}robably!", author= "Goldsmith, Michael", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "227--232", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "CSP, Hoare's Communicating Sequential Processes, is one of the formalisms that underpins the antecedents of CPA, and this year celebrates its Silver Jubilee. Formal Systems' own FDR refinement checker is among the most powerful explicit exhaustive finite-state exploration tools, and is tailored specifically to the CSP semantics. The CSPm ASCII form of CSP, in which FDR scripts are expressed, is the de-facto standard for CSP tools. Recent work has experimentally extended the notation to include a probabilistic choice construct, and added functionality into FDR to produce models suitable for analysis by the Birmingham University PRISM tool." } @InProceedings{BroeninkJovanovic04, title = "{G}raphical {T}ool for {D}esigning {CSP} {S}ystems", author= "Broenink, Jan F. and Jovanovic, Dusko S.", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "233--252", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "For a broad acceptance of an engineering paradigm, a graphical notation and supporting design tool seem inevitable. This paper discusses certain issues of developing a design environment for building systems based on CSP. Some of the issues discussed depend specifically on the underlying theory of CSP, while a number of them are common for any graphical notation and supporting tools, such as provisions for complexity management and design overview." } @InProceedings{East04b, title = "{T}owards a {S}emantics for {P}rioritized {A}lternation", author= "East, Ian R.", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "253--264", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "A new prioritised alternation programming construct and CSP operator have previously been suggested by the author to express behaviour that arises with machine-level prioritised vectored interruption. The semantics of each is considered, though that of prioritisation is deferred given the current lack of consensus regarding a suitable domain. Defining axioms for the operator are tentatively proposed, along with possible laws regarding behaviour. Lastly, the issue of controlled termination of component and construct is explored. This is intended as only a first step towards a complete semantics." } @InProceedings{OliveiraCavalcant04, title = "{R}efining {I}ndustrial {S}cale {S}ystems in {C}ircus", author= "Oliveira, Marcel and Cavalcanti, Ana and Woodcock, Jim", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "281--310", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "Circus is a new notation that may be used to specify both data and behaviour aspects of a system, and has an associated refinement calculus. Although a few case studies are already available in the literature, the industrial fire control system presented in this paper is, as far as we know, the largest case study on the Circus refinement strategy. We describe the refinement and present some new laws that were needed. Our case study makes extensive use of mutual recursion; a simplified notation for specifying such systems and proving their refinements is proposed here." } @InProceedings{Sputh04, title = "{K}-{CSP} {C}omponent {B}ased {D}evelopment of {K}ernel {E}xtensions", author= "Sputh, Bernhard H.C.", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "311--324", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "Kernel extension development suffers from two problems. Firstly, there is little to no code reuse. This is caused by the fact that most kernel extensions are coded in the C programming language. This language only allows code reuse either by using `copy and paste' or by using libraries. Secondly, the poor separation of synchronisation and functionality code makes it difficult to change one without affecting the other. It is, therefore, difficult to use the synchronisation mechanisms correctly. The approach proposed in this paper tries to solve these problems by introducing a component based programming model for kernel extensions, and a system based on this proposal is implemented for the Linux kernel. The language used for the implementation is Objective-C, and as a synchronisation mechanism Communicating Sequential Processes is used. This model allows the functionality and synchronisation of a component to be developed separately. Furthermore, due to the use of Communicating Sequential Processes it is possible to verify the correctness of the synchronisation. An example given in this paper illustrates how easy it is to use the K-CSP environment for development." } @InProceedings{FaustSputh04, title = "{C}haining {C}ommunications {A}lgorithms with {CSP}", author= "Faust, Oliver and Sputh, Bernhard H.C. and Endler, David", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "325--338", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "Software Defined Radio (SDR) requires a reliable, fast and flexible method to chain parameterisable algorithms. Communicating Sequential Processes (CSP) is a design methodology, which offers exactly these properties. This paper explores the idea of using a Java implementation of CSP (JCSP) to model a flexible algorithm chain for Software Defined Radio. JCSP offers the opportunity to distribute algorithms on different processors in a multiprocessor environment, which gives a speed up and keeps the system flexible. If more processing power is required another processor can be added. In order to cope with the high data rate requirement of SDR, optimized data transfer schemes were developed. The goal was to increase the overall system efficiency by reducing the synchronisation overhead of a data transfer between two algorithms. To justify the use of CSP in SDR, a system incorporating CSP was compared with a conventional system, in single and multiprocessor environments." } @InProceedings{PeelJavier04, title = "{U}sing {CSP} to {V}erify {A}spects of an {O}ccam-to-{FPGA} {C}ompiler", author= "Peel, Roger M. A. and Javier, Wong Han Feng", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "339--352", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "This paper reports on the progress made in developing techniques for the verification of an occam to FPGA compiler.The compiler converts occam programs into logic circuits that are suitable for loading into field-programmable gate arrays (FPGAs). Several levels of abstraction of these circuits provide links to conventional hardware implementations. Communicating Sequential Processes (CSP) has then been used to model these circuits. This CSP has been subjected to tests for deadlock and livelock freedom using the Failures-Divergence Refinement tool (FDR). In addition, FDR has been used to prove that the circuits emitted have behaviours equivalent to CSP specifications of the original occam source codes." } @InProceedings{Smith04, title = "{F}ocussing on {T}races to {L}ink {VCR} and {CSP}", author= "Smith, Marc L.", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "353--360", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "View-Centric Reasoning (VCR) replaces CSP's perfect observer with multiple, possibly imperfect observers. To employ view-centric reasoning within existing CSP models requires a bookkeeping change. Specifically, VCR introduces parallel events as a new primitive for constructing traces, and distinguishes two types of event traces: histories and views. Previously, we gave the operational semantics of VCR, and demonstrated the utility of parallel event traces to reason for the first time unambiguously about the meaning of the Linda predicate operations rdp() and inp(). The choice of using an operational semantics to describe VCR makes direct comparison with CSP difficult; therefore, work is ongoing to recast VCR denotationally, then link it with the other CSP models within Hoare and He's Unifying Theories of Programming. Initial efforts in this direction led to a comparison of VCR with Lawrence's HCSP. In this paper, we present some recent insights and abstractions - inspired by modern quantum physics - that have emerged whilst contemplating parallel event traces in light of the unifying theories. These insights lead to a more natural expression of VCR traces, in the sense that they more closely resemble CSP traces, thus forming a basis for linking VCR and CSP." } @InProceedings{TanakaFukuchi04, title = "{D}esign of a {T}ransputer {C}ore and {I}mplementation in an {FPGA}", author= "Tanaka, Makoto and Fukuchi, Naoya and Ooki, Yutaka and Fukunaga, Chikara", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "361--372", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "We have made an IP (Intellectual Property) core for the T425 transputer. The same machine instructions as the transputer are executable in this IP core (we call it TPCORE). To create an IP code for the transputer has two aspects. On one hand, if we could succeed in building our own one and put it in an FPGA, we could apply it as a core processor in a distributed system. We also intend to put it in a VLSI chip. On the other hand, if we can extend our transputer development starting from a very conventional one to more sophisticated ones, as Inmos proceeded to the T9000, we will eventually find our technological breakthrough for the bottlenecks that the original transputer had, such as the restriction of the number of communication channels. It is important to have an IP core for the transputer. Although TPCORE uses the same register set with the same functionality as transputer and follows the same mechanisms for link communication between two processes and interrupt handling, the implementation must be very different from original transputer. We have extensively used the micro-code ROM to describe any states that TPCORE must take. Using this micro code ROM for the state transition description, we could implement TPCORE economically on FPGA space and achieve efficient performance." } @InProceedings{AbdallahDamaj04, title = "{R}econfigurable {H}ardware {S}ynthesis of the {IDEA} {C}ryptographic {A}lgorithm", author= "Abdallah, Ali E. and Damaj, I. W.", editor= "East, Ian R. and Duce, David and Green, Mark and Martin, Jeremy M. R. and Welch, Peter H.", pages = "387--416", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2004", isbn= "1 58603 458 8", year= "2004", month= "sep", abstract= "The paper focuses on the synthesis of a highly parallel reconfigurable hardware implementation for the International Data Encryption Algorithm (IDEA). Currently, IDEA is well known to be a strong encryption algorithm. The use of such an algorithm within critical applications, such as military, requires efficient, highly reliable and correct hardware implementation. We will stress the affordability of such requirements by adopting a methodology that develops reconfigurable hardware circuits by following a transformational programming paradigm. The development starts from a formal functional specification stage. Then, by using function decomposition and provably correct data refinement techniques, powerful high-order functions are refined into parallel implementations described in Hoare's communicating sequential processes notation(CSP). The CSP descriptions are very closely associated with Handle-C hardware description language (HDL) program fragments. This description language is employed to target reconfigurable hardware as the final stage in the development. The targeted system in this case is the RC-1000 reconfigurable computer. In this paper different designs for the IDEA corresponding to different levels of parallelism are presented. Moreover, implementation, realization, and performance analysis and evaluation are included." } @InProceedings{East05, title = "{I}nterfacing with {H}oneysuckle by {F}ormal {C}ontract", author= "East, Ian R.", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "1--11", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "Honeysuckle is a new programming language that allows systems to be constructed from processes which communicate under service (client-server or master-servant) protocol. The model for abstraction includes a formal definition of both service and service-network (system or component). Any interface between two components thus forms a binding contract which will be statically verified by the compiler. An account is given of how such an interface is constructed and expressed in Honeysuckle, including how it may encapsulate state, and how access may be shared and distributed. Implementation is also briefly discussed." } @InProceedings{Kerridge05, title = "{G}roovy {P}arallel! {A} {R}eturn to the {S}pirit of occam?", author= "Kerridge, Jon and Barclay, Ken and Savage, John", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "13--28", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "For some years there has been much activity in developing CSP-like extensions to a number of common programming languages. In particular, a number of groups have looked at extensions to Java. Recent developments in the Java platform have resulted in groups proposing more expressive problem solving environments. Groovy is one of these developments. Four constructs are proposed that support the writing of parallel systems using the JCSP package. The use of these constructs is then demonstrated in a number of examples, both concurrent and parallel. A mechanism for writing XML descriptions of concurrent systems is described and it is shown how this is integrated into the Groovy environment. Finally conclusions are drawn relating to the use of the constructs, particularly in a teaching and learning environment." } @InProceedings{Jovanovic05, title = "{O}n {I}ssues of {C}onstructing an {E}xception {H}andling {M}echanism for {CSP}-{B}ased {P}rocess-{O}riented {C}oncurrent {S}oftware", author= "Jovanovic, Dusko S. and Orlic, Bojan and Broenink, Jan F.", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "29--41", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "This paper discusses issues, possibilities and existing approaches for fitting an exception handling mechanism (EHM) in CSP-based process-oriented software architectures. After giving a survey on properties desired for a concurrent EHM, specific problems and a few principal ideas for including exception handling facilities in CSP-designs are discussed. As one of the CSP-based frameworks for concurrent software, we extend CT (Communicating Threads) library with the exception handling facilities. The extensions result in two different EHM models whose compliance with the most important demands of concurrent EHMs (handling simultaneous exceptions, the mechanism formalization and efficient implementation) are observed." } @InProceedings{Rem05, title = "{A}utomatic {H}andel-{C} {G}eneration from {MATLAB}® and {S}imulink® for {M}otion {C}ontrol with an {FPGA}", author= "Rem, Bart and Gopalakrishnan, Ajeesh and Geelen, Tom J. H. and Roebbers, Herman", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "43--69", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "In this paper, we demonstrate a structured approach to proceed from development in a high level-modeling environment to testing on the real hardware. The concept is introduced by taking an example scenario that involves automatic code generation of Handel-C for FPGAs. The entire process is substantiated with a prototype that generates Handel-C code from MATLAB®/Simulink® for most common Simulink® blocks. Furthermore, we establish the potential of the notion by generating Handel-C for an FPGA, which controls the flow of paper through the scanning section of a printer/copier. Additionally, we present another method to generate Handel-C from a state-based specification. Finally, to verify and validate the behavior of the generated code, we execute several levels of simulation, including software-in-the-loop and hardware-in-the-loop simulations." } @InProceedings{SputhAllen05, title = "{JCSP}-{P}oison: {S}afe {T}ermination of {CSP} {P}rocess {N}etworks", author= "Sputh, Bernhard H.C. and Allen, Alastair R.", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "71--107", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "This paper presents a novel technique for safe partial or complete process network termination. The idea is to have two types of termination messages / poison: LocalPoison and GlobalPoison. Injecting GlobalPoison into a process network results in a safe termination of the whole process network. In contrast, injected LocalPoison only terminates all processes until it is filtered out by Poison-Filtering Channels. This allows the creation of termination domains inside a process network. To make handling of a termination message easy, it is delivered as an exception and not as a normal message. The necessary Poisonable- and Poison-Filtering-Channels have been modelled in CSP and checked using FDR. A proof of concept implementation for Communicating Sequential Processes for Java (JCSP) has been developed and refined. Previously, JCSP offered no safe way to terminate the process network. When the user terminated the program, the Java Virtual Machine (JVM) simply stops all threads (processes), without giving the processes the chance to perform clean up operations. A similar technique is used to perform partial termination of process networks in JCSP, making it unsafe as well. The technique presented in this paper is not limited to JCSP, but can easily be ported to other CSP environments. Partial process network termination can be applied in the area of Software Defined Radio (SDR), because SDR systems need to be able to change their signal processing algorithms during runtime." } @InProceedings{ChalmersKerridge05, title = "jcsp.mobile: {A} {P}ackage {E}nabling {M}obile {P}rocesses and {C}hannels", author= "Chalmers, Kevin and Kerridge, Jon", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "109--127", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "The JCSPNet package from Quickstone provides the capability of transparently creating a network of processes that run across a TCP/IP network. The package also contains mechanisms for creating mobile processes and channels through the use of filters and the class Dynamic Class Loader, though their precise use is not well documented. The package jcsp.mobile rectifies this position and provides a set of classes and interfaces that facilitates the implementation of systems that use mobile processes and channels. In addition, the ability to migrate processes and channels from one processor to another is also implemented. The capability is demonstrated using a multi-user game running on an ad-hoc wireless network using a workstation and four PDAs." } @InProceedings{Gardner05, title = "{CSP}++: {H}ow {F}aithful to {CSP}m?", author= "Gardner, W. B.", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "129--146", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "CSP++ is a tool that makes specifications written in CSPm executable and extensible. It is the basis for a technique called selective formalism, which allows part of a system to be designed in verifiable CSPm statements, automatically translated into C++, and linked with functions coded in C++. This paper describes in detail the subset of CSPm that can be accurately translated by CSP++, and how the CSP semantics are achieved by the runtime framework. It also explains restrictions that apply to coding in CSPm for software synthesis, and the rationale for those restrictions." } @InProceedings{Schoute05, title = "{F}ast {D}ata {S}haring within a {D}istributed, {M}ultithreaded {C}ontrol {F}ramework for {R}obot {T}eams", author= "Schoute, Albert L. and Seesink, Remco and Dierssen, Werner and Kooij, Niek", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "147--154", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "In this paper a data sharing framework for multi-threaded, distributed control programs is described that is realized in C++ by means of only a few, powerful classes and templates. Fast data exchange of entire data structures is supported using sockets as communication medium. Access methods are provided that preserve data consistency and synchronize the data exchange. The framework has been successfully used to build a distributed robot soccer control system running on as many computers as needed." } @InProceedings{HappeVinter05, title = "{I}mproving {TCP}/{IP} {M}ulticasting with {M}essage {S}egmentation", author= "Happe, Hans Henrik and Vinter, Brian", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "155--163", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "Multicasting is a very important operation in high performance parallel applications. Making this operation efficient in supercomputers has been a topic of great concern. Much effort has gone into designing special interconnects to support the operation. Today\&\#8217;s huge deployment of NoWs (Network of Workstations) has created a high demand for efficient software-based multicast solutions. These systems are often based on low-cost Ethernet interconnects without direct support for group communication. Basically TCP/IP is the only widely supported method of fast reliable communication, though it is possible to improve Ethernet performance at many levels \&\#8211; i.e., by-passing the operating system or using physical broadcasting. Low-level improvements are not likely to be accepted in production environments, which leaves TCP/IP as the best overall choice for group communication. In this paper we describe a TCP/IP based multicasting algorithm that uses message segmentation in order to lower the propagation delay. Experiments have shown that TCP is very inefficient when a node has many active connections. With this in mind we have designed the algorithm so that it has a worst-case propagation path length of O(log n) with a minimum of connections per node. We compare our algorithm with the binomial tree algorithm often used in TCP/IP MPI implementations." } @InProceedings{Sampson05, title = "{L}azy {C}ellular {A}utomata with {C}ommunicating {P}rocesses", author= "Sampson, Adam T. and Welch, Peter H. and Barnes, Frederick R. M.", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "165--175", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "Cellular automata (CAs) are good examples of systems in which large numbers of autonomous entities exhibit emergent behaviour.Using the occam-pi and JCSP communicating process systems, we show how to construct \&\#8220;lazy\&\#8221; and \&\#8220;just-in-time\&\#8221; models of cellular automata, which permit very efficient parallel simulation of sparse CA populations on shared-memory and distributed systems." } @InProceedings{Smith05, title = "{A} {U}nifying {T}heory of {T}rue {C}oncurrency {B}ased on {CSP} and {L}azy {O}bservation", author= "Smith, Marc L.", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "177--188", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "What if the CSP observer were lazy? This paper considers the consequences of altering the behavior of the CSP observer. Specifically, what implications would this new behavior have on CSP\&\#8217;s traces? Laziness turns out to be a useful metaphor. We show how laziness permits transforming CSP into a model of true concurrency (i.e., non-interleaved trace semantics). Furthermore, the notion of a lazy observer supports tenets of view-centric reasoning (VCR): parallel events (i.e., true concurrency), multiple observers (i.e., different views), and the possibility of imperfect observation. We know from the study of programming languages that laziness is not necessarily a negative quality; it provides the possibility of greater expression and power in the programswe write. Similarly, within the context of the Unifying Theories of Programming, a model of true concurrency\&\#8212; VCR \&\#8212; becomes possible by permitting (even encouraging) the CSP observer to be lazy." } @InProceedings{Vinter05, title = "{T}he {A}rchitecture of the {M}inimum intrusion {G}rid ({M}i{G})", author= "Vinter, Brian", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "189--201", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "This paper introduces the philosophy behind a new Grid model, the Minimum intrusion Grid, MiG. The idea behind MiG is to introduce a \&\#8216;fat\&\#8217; Grid infrastructure which will allow much \&\#8216;slimmer\&\#8217; Grid installations on both the user and resource side. This paper presents the ideas of MiG, some initial designs and finally a status report of the implementation." } @InProceedings{Klebanov05, title = "{V}erification of {JCSP} {P}rograms", author= "Klebanov, Vladimir and Rümmer, Philipp and Schlager, Steffen and Schmitt, Peter H.", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "203--218", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "We describe the first proof system for concurrent programs based on Communicating Sequential Processes for Java (JCSP). The system extends a complete calculus for the JavaCard Dynamic Logic with support for JCSP, which is modeled in terms of the CSP process algebra. Together with a novel efficient calculus for CSP, a rule system is obtained that enables JCSP programs to be executed symbolically and to be checked against temporal properties. The proof system has been implemented within the KeY tool and is publicly available." } @InProceedings{Wiggers05, title = "{A}rchitecture {D}esign {S}pace {E}xploration for {S}treaming {A}pplications through {T}iming {A}nalysis", author= "Wiggers, Maarten H. and Kavaldjiev, Nikolay and Smit, Gerard J. M. and Jansen, Pierre G.", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "219--233", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "In this paper we compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN\2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the application\&\#8217;s throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations." } @InProceedings{DimmichJacobsen05, title = "{A} {F}oreign {F}unction {I}nterface {G}enerator for occam-pi", author= "Dimmich, Damian J. and Jacobsen, Christian L.", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "235--248", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "occam-pi is a programming language based on the CSP process algebra and the pi-calculus, and has a powerful syntax for expressing concurrency. occam-pi does not however, come with interfaces to a broad range of standard libraries (such as those used for graphics or mathematics). Programmers wishing to use these must write their own wrappers using occam-pi’s foreign function interface, which can be tedious and time consuming. SWIG offers automatic generation of wrappers for libraries written in C and C++, allowing access to these for the target languages supported by SWIG. This paper describes the occam-pi module for SWIG, which will allow automatic wrapper generation for occam-pi, and will ensure that occam-pi’s library base can be grown in a quick and efficient manner. Access to database, graphics and hardware interfacing libraries can all be provided with relative ease when using SWIG to automate the bulk of the work." } @InProceedings{Barnes05, title = "{I}nterfacing {C} and occam-pi", author= "Barnes, Frederick R. M.", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "249--260", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", } @InProceedings{Bjorndalen05, title = "{I}nteractive {C}omputing with the {M}inimum intrusion {G}rid ({M}i{G})", author= "Bjørndalen, John Markus and Anshus, Otto J. and Vinter, Brian", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "261--273", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "Grid computing is finally starting to provide solutions for capacity computing, that is problem solving where there is a large number of independent tasks for execution. This paper describes the experiences with using Grid for capability computing, i.e. solving a single task efficiently. The chosen capability application is driving a very large display which requires enormous processing power due to its huge graphic resolution (7168 x 3072 pixels). Though we use an advanced Grid middleware, the conclusion is that new features are required to provide such coordinated calculations as the present application requires." } @InProceedings{SaifhashemiBeerel05, title = "{H}igh {L}evel {M}odeling of {C}hannel-{B}ased {A}synchronous {C}ircuits {U}sing {V}erilog", author= "Saifhashemi, Arash and Beerel, Peter A.", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "275--288", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "In this paper we describe a method for modeling channel-based asynchronous circuits using Verilog HDL. We suggest a method to model CSP-like channels in Verilog HDL. This method also describes nonlinear pipelines and high level channel timing properties, such as forward and backward latencies, minimum cycle time, and slack. Using Verilog enables us to describe the circuit at many levels of abstraction and to use the commercially available CAD tools." } @InProceedings{WelchBarnes05, title = "{M}obile {B}arriers for occam-pi: {S}emantics, {I}mplementation and {A}pplication", author= "Welch, Peter H. and Barnes, Frederick R. M.", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "289--316", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "This paper introduces a safe language binding for CSP multiway events (barriers\&\#8212;both static and mobile) that has been built into occam-pi (an extension of the classical occam language with dynamic parallelism, mobile processes and mobile channels). Barriers provide a simple way for synchronising multiple processes and are the fundamental control mechanism underlying both CSP (Communicating Sequential Processes) and BSP (Bulk Synchronous Parallelism). Formal semantics (through modelling in classical CSP), implementation details and early performance benchmarks (16 nanoseconds per process per barrier synchronisation on a 3.2 GHz Pentium IV) are presented, along with some likely directions for future research. Applications are outlined for the fine-grained modelling of dynamic systems, where barriers are used for maintaining simulation time and the phased execution of time steps, coordinating safe and desired patterns of communication between millions (and more) of processes. This work forms part of our TUNA project, investigating emergent properties in large dynamic systems (nanite assemblies)." } @InProceedings{Hilderink05, title = "{E}xception {H}andling {M}echanism in {C}ommunicating {T}hreads for {J}ava", author= "Hilderink, Gerald H.", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "317--334", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "The concept of exception handling is important for building reliable software. An exception construct is proposed in this paper, which implements an exception handling mechanism that is suitable for concurrent software architectures. The aim of this exception construct is to bring exception handling to a high-level of abstraction such that exception handling does scale well with the complexity of the system. This is why the exception construct supports a CSP-based software design approach. The proposed exception construct embraces informal semantics, but which are intuitive and suitable to software engineering. The exception construct is prototyped in the CSP for Java library, called CTJ." } @InProceedings{Jakson05, title = "{R}16: a {N}ew {T}ransputer {D}esign for {FPGA}s", author= "Jakson, John", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "335--362", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "This paper describes the ongoing development of a new FPGA hosted Transputer using a Load Store RISC style Multi Threaded Architecture (MTA). The memory system throughput is emphasized as much as the processor throughput and uses the recently developed Micron 32MByte RLDRAM which can start fully random memory cycles every 3.3ns with 20ns latency when driven by an FPGA controller. The R16 shares an object oriented Memory Manager Unit (MMU) amongst multiple low cost Processor Elements (PEs) until the MMU throughput limit is reached. The PE has been placed and routed at over 300MHz in a Xilinx Virtex-II Pro device and uses around 500 FPGA basic cells and 1 Block RAM. The 15 stage pipeline uses 2 clocks per instruction to greatly simplify the hardware design which allows for twice the clock frequency of other FPGA processors. There are instruction and cycle accurate simulators as well as a C compiler in development. The compiler can now emit optimized small functions needed for further hardware development although compiling itself requires much work. Some occam and Verilog language components will be added to the C base to allow a mixed occam and event driven processing model. Eventually it is planned to allow occam or Verilog source to run as software code or be placed as synthesized co processor hardware attached to the MMU." } @InProceedings{Stewart05, title = "{T}owards {S}trong {M}obility in the {S}hared {S}ource {CLI}", author= "Stewart, Johnston and Nixon, Patrick and Walsh, Tim and Ferguson, Ian", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "363--373", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "Migrating a thread while preserving its state is a useful mechanism to have in situations where load balancing within applications with intensive data processing is required. Strong mobility systems, however, are rarely developed or implemented as they introduce a number of major challenges into the implementation of the system. This is due to the fact that the underlying infrastructure that most computers operate on was never designed to accommodate such a system, and because of this it actually impedes the development of these systems to some degree. Using a system based around a virtual machine, such as Microsoft\&\#8217;s Common Language Runtime (CLR), circumnavigates many of these problems by abstracting away system differences. In this paper we outline the architecture of the threading mechanism in the shared source version of the CLR known as the Shared Source Common Language Infrastructure (SSCLI). We also outline how we are porting strong mobility into the SSCLI, taking advantage of its virtual machine." } @InProceedings{Groothuis05, title = "g{CSP} occam {C}ode {G}eneration for {RM}o{X}", author= "Groothuis, Marcel A. and Liet, Geert K. and Broenink, Jan F.", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "375--383", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "gCSP is a graphical tool for creating and editing CSP diagrams. gCSP is used in our labs to generate the embedded software framework for our control systems. As a further extension to our gCSP tool, an occam code generator has been constructed. Generating occam from CSP diagrams gives opportunities to use the Raw-Metal occam eXperiment (RMoX) as a minimal operating system on the embedded control PCs in our mechatronics laboratory. In addition, all processors supported by KRoC can be reached from our graphical CSP tool. The commstime benchmark is used to show the trajectory for gCSP code generation for the RMoX operating system. The result is a simple means for using RMoX in our laboratory for our control systems. We want to use RMoX for future research on distributed control and for performance comparisons between a minimal operating system and our CTC++/RT-linux systems." } @InProceedings{Ivanovici05, title = "{A}ssessing {A}pplication {P}erformance in {D}egraded {N}etwork {E}nvironments: an {FPGA}-based {A}pproach", author= "Ivanovici, Mihai and Beuran, Razvan and Davies, Neil", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "385--395", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "Network emulation is a technique that allows real-application performance assessment under controllable and reproducible conditions. We designed and implemented a hardware network emulator on an FPGA-based custom-design PCI platform. Implementation was facilitated by the use of the Handel-C programming language, that allows rapid development and fast translation into hardware and has specific constructs for developing systems with concurrent processes. We report on tests performed with web-browsing applications." } @InProceedings{Hofstee05, title = "{C}ommunication and {S}ynchronisation in the {C}ell {P}rocessor", author= "Hofstee, H. Peter", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "397--397", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", } @InProceedings{Stravers05, title = "{H}omogeneous {M}ultiprocessing for {C}onsumer {E}lectronics", author= "Stravers, Paul", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "399--399", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", } @InProceedings{Peeters05, title = "{H}andshake {T}echnology: {H}igh {W}ay to {L}ow {P}ower", author= "Peeters, Ad", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "401--401", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", } @InProceedings{Broadfoot05, title = "{I}f {C}oncurrency in {S}oftware is {S}o {S}imple, {W}hy is it {S}o {H}ard?", author= "Broadfoot, Guy", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "403--403", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", } @InProceedings{CookWalker06, title = "{S}pace{W}ire - {DS}-{L}inks {R}eborn", author= "Cook, Barry M. and Walker, Paul", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "1--12", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "DS-links were created to provide a low-latency, high performance data link between parallel processors. When the primary processor using them was withdrawn these links largely disappeared from view but were, in fact, still being used (albeit not for parallel computing) in the Space industry. The potential for these links, with their simple implementation, led to their adoption, in modified form, for a growing range of data communication applications. In 2003, the European Space Agency published a definition of DS-links known as SpaceWire. We briefly describe the original DS-links and detail how SpaceWire has kept or modified them to produce a now popular technology with a rapidly increasing number of implementations and wide take-up." } @InProceedings{LehmbergOlsen06, title = "{A}n {I}ntroduction to {CSP}.{NET}", author= "Lehmberg, Alex and Olsen, Martin N.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "13--30", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "This paper reports on CSP.NET, developed over the last three months at the University of Copenhagen. CSP.NET is an object oriented CSP library designed to ease concurrent and distributed programming in Microsoft.NET 2.0. The library supports both shared memory multiprocessor systems and distributed-memory multicomputers and aims towards making the architecture transparent to the programmer. CSP.NET exploits the power of .NET Remoting to provide the distributed capabilities and like JCSP, CSP.NET relies exclusively on operating system threads. A Name Server and a workerpool are included in the library, both implemented as Windows Services. This paper presents CSP.NET from a users perspective and provides a tutorial along with some implementation details and performance tests." } @InProceedings{Chalmers06, title = "{P}erformance {E}valuation of {JCSP} {M}icro {E}dition: {JCSP}me", author= "Chalmers, Kevin and Kerridge, Jon and Romdhani, Imed", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "31--40", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "Java has become a development platform that has migrated from its initial focus for small form devices, to large full scale desktop and server applications and finally back to the small in the form of Java enabled mobile phones. Here we discuss the necessary requirements to convert the existing JCSP framework so that it can be used in these resource constrained systems. We also provide some performance comparisons on various platforms to evaluate this implementation." } @InProceedings{KerridgeChalmers06, title = "{U}biquitous {A}ccess to {S}ite {S}pecific {S}ervices by {M}obile {D}evices: the {P}rocess {V}iew.", author= "Kerridge, Jon and Chalmers, Kevin", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "41--58", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "The increasing availability of tri-band mobile devices with mobile phone, wi-fi and Bluetooth capability means that the opportunities for increased access by mobile devices to services provided within a smaller locality becomes feasible. This increase in availability might, however, be tempered by users switching off their devices as they are overloaded with a multitude of messages from a variety of sources. A wide range of opportunities can be realised if we can provide a managed environment in which people can access wireless services specific to a particular physical site or location in a ubiquitous manner, independent of the service, and they can also choose from which services they are willing to receive messages. These opportunities range from retail promotions as a person walks down the street, to shopper specific offers as people enter stores that utilise reward card systems, to information about bus arrivals at a bus stop, additional curatorial information within a museum and access to health records within a hospital environment. The CPA paradigm offers a real opportunity to provide such capability with mobile processes, rather than the current approach that, typically, gives users access to web pages." } @InProceedings{ChalmersClayton06, title = "{CSP} for .{NET} {B}ased on {JCSP}", author= "Chalmers, Kevin and Clayton, Sarah", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "59--76", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "We present a CSP framework developed for the .NET platform, building upon the ideas developed for the JCSP library. Discussing the development of the core functionality and then onto extra features in .NET that can be taken advantage of, we have created an initial platform that can provide simple development of CSP style process networks. However, we demonstrate that the Microsoft .NET implementation is more resource hungry for multi-threaded applications than other approaches considered in this paper." } @InProceedings{SchweiglerSampson06, title = "pony - {T}he occam-pi {N}etwork {E}nvironment", author= "Schweigler, Mario and Sampson, Adam T.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "77--108", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "Although concurrency is generally perceived to be a hard subject, it can in fact be very simple, provided that the underlying model is simple. The occam-pi parallel processing language provides such a simple yet powerful concurrency model that is based on CSP and the pi-calculus. This paper presents pony, the occam-pi Network Environment. occam-pi and pony provide a new, unified, concurrency model that bridges inter- and intra-processor concurrency. This enables the development of distributed applications in a transparent, dynamic and highly scalable way. The first part of this paper discusses the philosophy behind pony, explains how it is used, and gives a brief overview of its implementation. The second part evaluates pony's performance by presenting a number of benchmarks." } @InProceedings{Faust06, title = "{A} {S}tudy of {P}ercolation {P}henomena in {P}rocess {N}etworks", author= "Faust, Oliver and Sputh, Bernhard H.C. and Allen, Alastair R.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "109--121", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "Percolation theory provides models for a wide variety of natural phenomena. One of these phenomena is the dielectric breakdown of composite materials. This paper describes how we implemented the percolation model for dielectric breakdown in a massively parallel processing environment. To achieve this we modified the breadth-first search algorithm such that it works in probabilistic process networks. Formal methods were used to reason about this algorithm. Furthermore, this algorithm provides the basis for a JCSP implementation which models dielectric breakdowns in composite materials. The implementation model shows that it is possible to apply formal methods in probabilistic processing environments." } @InProceedings{Sputh06, title = "{P}ortable {CSP} {B}ased {D}esign for {E}mbedded {M}ulti-{C}ore {S}ystems", author= "Sputh, Bernhard H.C. and Faust, Oliver and Allen, Alastair R.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "123--134", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "Modern lifestyle depends on embedded systems. They are everywhere: sometimes they are hidden and at other times they are handled as a fashion accessory. In order to serve us better they have to do more and more tasks at the same time. This calls for sophisticated mechanisms to handle concurrency. In this paper we present CSP (Communicating Sequential Processes) as a method which helps to solve a number of problems of embedded concurrent systems. To be specific, we describe implementations of the commstime benchmark in multithreaded, multiprocessor and architecture fusion systems. An architecture fusion system combines machine and hardware-logic architectures. Our results are twofold. First, architecture fusion systems outperform all the other systems we tested. Second, we implemented all the systems without a change in the design philosophy. The second point is the more important result, because it shows the power of CSP based design methods." } @InProceedings{KumarStiles06, title = "{A} {JCSP}.net {I}mplementation of a {M}assively {M}ultiplayer {O}nline {G}ame", author= "Kumar, Shyam and Stiles, G. S.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "135--149", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "We have developed a simple massively multiplayer online game system as a test bed for evaluating the usefulness and performance of JCSP.net. The system consists of a primary login server, secondary servers managing play on geographically distinct playing fields, and an arbitrary number of players. The basic structure of the game system is fairly simple, and has been verified to be free from deadlock and livelock using CSP and FDR. The JCSP.net implementation is straight-forward and includes over-writing buffers so that disconnected players will not block the servers and other players. Performance tests on local area networks under Windows demonstrate that five secondary servers easily support 1,000 machine-generated players making moves every two to five seconds. The player move end-to-end time was about 65 milliseconds, which is considered fast enough to support fast-action online games. Conversion from Windows to Linux required minimal effort; limited tests confirmed that versions using Linux alone, and Windows and Linux together, were also successful." } @InProceedings{OrlicBroenink06a, title = "{S}ystem{CSP} - {V}isual {N}otation", author= "Orlic, Bojan and Broenink, Jan F.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "151--177", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "This paper introduces SystemCSP - a design methodology based on a visual notation that can be mapped onto CSP expressions. SystemCSP is a graphical design specification language aimed to serve as a basis for the specification of formally verifiable component-based designs of distributed real-time systems. It aims to be a graphical formalism that covers various aspects needed for the design of distributed real-time systems in single framework." } @InProceedings{OrlicBroenink06b, title = "{I}nteracting {C}omponents", author= "Orlic, Bojan and Broenink, Jan F.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "179--202", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "SystemCSP is a graphical modeling language based on both CSP and concepts of component-based software development. The component framework of SystemCSP enables specification of both interaction scenarios and relative execution ordering among components. Specification and implementation of interaction among participating components is formalized via the notion of interaction contract. The used approach enables incremental design of execution diagrams by adding restrictions in different interaction diagrams throughout the process of system design. In this way all different diagrams are related into a single formally verifiable system. The concept of reusable formally verifiable interaction contracts is illustrated by designing set of design patterns for typical fault tolerance interaction scenarios." } @InProceedings{Happe06, title = "{TCP} {I}nput {T}hreading in {H}igh {P}erformance {D}istributed {S}ystems", author= "Happe, Hans Henrik", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "203--213", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "TCP is the only widely supported protocol for reliable communication. Therefore, TCP is the obvious choice when developing distributed systems that need to work on a wide range of platforms. Also, for this to work a developer has to use the standard TCP interface provided by a given operating system. This work explores various ways to use TCP in high performance distributed systems. More precisely, different ways to use the standard Unix TCP API efficiently are explored, but the findings apply to other operating systems as well. The main focus is how various threading models affect TCP input in a process that has to handle both computation and I/O. The threading models have been evaluated in a cluster of Linux workstations and the results show that a model with one dedicated I/O thread generally is good. It is at most 10\% slower than the best model in all tests, while the other models are between 30 to 194\% slower in specific tests." } @InProceedings{Dimmich06, title = "{A} {C}ell {T}ransterpreter", author= "Dimmich, Damian J. and Jacobsen, Christian L. and Jadud, Matthew C.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "215--224", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "The Cell Broadband Engine is a hybrid processor which consists of a PowerPC core and eight vector co-processors on a single die. Its unique design poses a number of language design and implementation challenges. To begin exploring these challenges, we have ported the Transterpreter to the Cell Broadband Engine. The Transterpreter is a small, portable runtime for concurrent languages and can be used as a platform for experimenting with language concepts. This paper describes a preliminary attempt at porting the Transterpreter runtime to the Cell Broadband Engine and explores ways to program it using a concurrent language." } @InProceedings{Simpson06, title = "{M}obile {R}obot {C}ontrol: {T}he {S}ubsumption {A}rchitecture and occam-pi", author= "Simpson, Jonathan and Jacobsen, Christian L. and Jadud, Matthew C.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "225--236", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "Brooks' subsumption architecture is a design paradigm for mobile robot control that emphasises re-use of modules, decentralisation and concurrent, communicating processes. Through the use of occam-pi the subsumption architecture can be put to use on general purpose modern robotics hardware, providing a clean and robust development approach for the creation of robot control systems." } @InProceedings{Brown06a, title = "{R}ain: {A} {N}ew {C}oncurrent {P}rocess-{O}riented {P}rogramming {L}anguage", author= "Brown, Neil C.C.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "237--251", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "This paper details the design of a new concurrent process-oriented programming language, Rain. The language borrows heavily from occam-p and C++ to create a new language based on process-oriented programming, marrying channel-based communication, a clear division between statement and expression, and elements of functional programming. An expressive yet simple type system, coupled with templates, underpins the language. Modern features such as Unicode support and 64-bit integers are included from the outset, and new ideas involving permissions and coding standards are also proposed. The language targets a new virtual machine, which is detailed in a companion paper along with benchmarks of its performance." } @InProceedings{Brown06b, title = "{R}ain {VM}: {P}ortable {C}oncurrency through {M}anaging {C}ode", author= "Brown, Neil C.C.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "253--267", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "A long-running recent trend in computer programming is the growth in popularity of virtual machines. However, few have included good support for concurrency - a natural mechanism in the Rain programming language. This paper details the design and implementation of a secure virtual machine with support for concurrency, which enables portability of concurrent programs. Possible implementation ideas of many-to-many threading models for the virtual machine kernel are discussed, and initial benchmarks are presented. The results show that while the virtual machine is slow for standard computation, it is much quicker at running communication-heavy concurrent code - within an order of magnitude of the same native code." } @InProceedings{Jacobsen06, title = "{N}ative {C}ode {G}eneration using the {T}ransterpreter.", author= "Jacobsen, Christian L. and Dimmich, Damian J. and Jadud, Matthew C.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "269--280", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "We are interested in languages that provide powerful abstractions for concurrency and parallelism that execute everywhere, efficiently. Currently, the existing runtime environments for the occam-pi programming language provide either one of these features (portability) or some semblance of the other (performance). We believe that both can be achieved through the careful generation of C from occam-pi, and demonstrate that this is possible using the Transterpreter, a portable interpreter for occam-pi, as our starting point." } @InProceedings{BurginSmith06, title = "{C}ompositions of {C}oncurrent {P}rocesses", author= "Burgin, Mark and Smith, Marc L.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "281--296", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "Using the extended model for view-centric reasoning, EVCR, we focus on the many possibilities for concurrent processes to be composed. EVCR is an extension of VCR, both models of true concurrency; VCR is an extension of CSP, which is based on an interleaved semantics for modeling concurrency. VCR, like CSP, utilizes traces of instantaneous events, though VCR permits recording parallel events to preserve the perception of simultaneity by the observer(s). But observed simultaneity is a contentious issue, especially for events that are supposed to be instantaneous. EVCR addresses this issue in two ways. First, events are no longer instantaneous; they occur for some duration of time. Second, parallel events need not be an all-or-nothing proposition; it is possible for events to partially overlap in time. Thus, EVCR provides a more realistic and appropriate level of abstraction for reasoning about concurrent processes. With EVCR, we begin to move from observation to the specification of concurrency, and the compositions of concurrent processes. As one example of specification, we introduce a description of I/O-PAR composition that leads to simplified reasoning about composite I/O-PAR processes." } @InProceedings{Hilderink06, title = "{S}oftware {S}pecification {R}efinement and {V}erification {M}ethod with {I}-{M}athic {S}tudio.", author= "Hilderink, Gerald H.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "297--310", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "A software design usually manifests a composition of software specifications. It consists of hierarchies of black box and white box specifications which are subject to refinement verification. Refinement verification is a model-checking process that proves the correctness of software specifications using formal methods. Although this is a powerful tool for developing reliable and robust software, the applied mathematics causes a serious gap between academics and software engineers. I-Mathic comprehends a software specification refinement and verification method and a supporting toolset, which aims at eliminating the gap through hiding the applied mathematics by practical modelling concepts. The model-checker FDR is used for refinement verification and detecting deadlocks and livelocks in software specifications. We have improved the method by incorporating CSP programming concepts into the specification language. These concepts make the method suitable for a broader class of safety-critical concurrent systems. The improved I-Mathic is illustrated in this paper." } @InProceedings{Ritson06, title = "{V}ideo {P}rocessing in occam-pi", author= "Ritson, Carl G. and Sampson, Adam T. and Barnes, Frederick R. M.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "311--329", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "The occam-pi language provides many novel features for concurrent software development. This paper describes a video processing framework that explores the use of these features for multimedia applications. Processes are used to encapsulate operations on video and audio streams; mobile data types are used to transfer data between them efficiently, and mobile channels allow the process network to be dynamically reconfigured at runtime. We present demonstration applications including an interactive video player. Preliminary benchmarks show that the framework has comparable overhead to multimedia systems programmed using traditional methods." } @InProceedings{Teig06, title = "{N}o {B}locking on {Y}esterday's {E}mbedded {CSP} {I}mplementation (the {R}ubber {B}and of {G}etting it {R}ight and {S}imple)", author= "Teig, Øyvind", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "331--338", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "This article is a follow-up after the paper \textquotedblFrom message queue to ready queue\textquotedbl, presented at the ERCIM Workshop last year. A (mostly) synchronous layer had been implemented on top of an existing asynchronous run-time system. After that workshop, we discovered that the initial implementation contained two errors: both concerning malignant process rescheduling associated with timers and 'reuse' of the input side of a channel. Also, the set of process/dataflow patterns was not sufficient. To keep complexity low, we have made two new patterns to reflect better the semantic needs inherent in the application. Our assumption of correctness is also, this time, based both on heuristics and 'white-board reasoning'. However, both the previous and this paper have been produced before any first shipment of the product, and well within full-scale testing. Our solutions and way of attacking the problems have been in an industrial tradition." } @InProceedings{McEwan06, title = "{A} {C}ircus {D}evelopment and {V}erification of an {I}nternet {P}acket {F}ilter.", author= "McEwan, Alistair A.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "339--362", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "In this paper, we present the results of a significant and large case study in Circus. Development is top-down - from a sequential abstract specification about which safety properties can be verified, to a highly concurrent implementation on a Field Programmable Gate Array. Development steps involve applying laws of Circus allowing for the refinement of specifications; confidence in the correctness of the development is achieved through the applicability of the laws applied; proof obligations are discharged using the model-checker for CSP, FDR, and the theorem prover for Z, Z/Eves. An interesting feature of this case study is that the design of the implementation is guided by domain knowledge of the application - the application of this domain knowledge is supported by, rather than constrained by the calculus. The design is not what would have been expected had the calculus been applied without this domain knowledge. Verification highlights a curious error made in early versions of the implementation that were not detected by testing." } @InProceedings{Pedersen06, title = "{C}lassification of {P}rogramming {E}rrors in {P}arallel {M}essage {P}assing {S}ystems", author= "Pedersen, Jan Bækgaard", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "363--376", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "In this paper we investigate two major topics; firstly, through a survey given to graduate students in a parallel message passing programming class, we categorize the errors they made (and the ways they fixed the bugs) into a number of categories. Secondly, we analyze these answers and provide some insight into how software could be built to aid the development, deployment, and debugging of parallel message passing systems. We draw parallels to similar studies done for sequential programming, and finally show how the idea of multilevel debugging relates to the results from the survey." } @InProceedings{Barnes06, title = "{C}ompiling {CSP}", author= "Barnes, Frederick R. M.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "377--388", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", abstract= "CSP, Hoare's Communicating Sequential Processes, is a formal language for specifying, implementing and reasoning about concurrent processes and their interactions. Existing software tools that deal with CSP directly are largely concerned with assisting formal proofs. This paper presents an alternative use for CSP, namely the compilation of CSP systems to executable code. Themain motivation for this work is in providing a means to experimentwith relatively large CSP systems, possibly consisting millions of concurrent processes - something that is hard to achieve with the tools currently available." } @InProceedings{Welch06, title = "{A} {F}ast {R}esolution of {C}hoice between {M}ultiway {S}ynchronisations", author= "Welch, Peter H.", editor= "Welch, Peter H. and Kerridge, Jon and Barnes, Frederick R. M.", pages = "389--389", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2006", isbn= "978-1-58603-671-3", year= "2006", month= "sep", } @InProceedings{Hoare07, title = "{F}ine-grain {C}oncurrency", author= "Hoare, Tony", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "1--20", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "I have been interested in concurrent programming since about 1963, when its associated problems contributed to the failure of the largest software project that I have managed. When I moved to an academic career in 1968, I hoped that I could find a solution to the problems by my research. Quite quickly I decided to concentrate on coarse-grained concurrency, which does not allow concurrent processes to share main memory. The only interaction between processes is confined to explicit input and output commands. This simplification led eventually to the exploration of the theory of Communicating Sequential Processes. Since joining Microsoft Research in 1999, I have plucked up courage at last to look at fine-grain concurrency, involving threads which interleave their access to main memory at the fine granularity of single instruction execution. By combining the merits of a number of different theories of concurrency, one can paint a relatively simple picture of a theory for the correct design of concurrent systems. Indeed, pictures are a great help in conveying the basic understanding. This paper presents some on-going directions of research that I have been pursuing with colleagues in Cambridge \&\#8211; both at Microsoft Research and in the University Computing Laboratory." } @InProceedings{May07, title = "{C}ommunicating {P}rocess {A}rchitecture for {M}ulticores", author= "May, David", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "21--32", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "Communicating process architecture can be used to build efficient multicore chips scaling to hundreds of processors. Concurrent processing, communications and input-output are supported directly by the instruction set of the cores and by the protocol used in the on-chip interconnect. Concurrent programs are compiled directly to the chip exploiting novel compiler optimisations. The architecture supports a variety of programming techniques, ranging from statically configured process networks to dynamic reconfiguration and mobile processes." } @InProceedings{BrookePaige07, title = "{L}azy {E}xploration and {C}hecking of {CSP} {M}odels with {CSP}sim", author= "Brooke, Philip J and Paige, Richard F.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "33--50", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "We have recently constructed a model, and carried out an analysis, of a concurrent extension to an object-oriented language at a level of abstraction above threads. The model was constructed in CSP. We subsequently found that existing CSP tools were unsuitable for reasoning about and analysing this model, so it became necessary to create a new tool to handle CSP models: CSPsim. We describe this tool, its capabilities and algorithms, and compare it with the related tools, FDR2 and ProBE. We illustrate CSPsim's usage with examples from the model. The tool's on-the-fly construction of successor states is important for exhaustive and non-exhaustive state exploration. Thus we found CSPsim to be particularly useful for parallel compositions of components with infinite states that reduce to finite-state systems." } @InProceedings{Huntbach07, title = "{T}he {C}ore {L}anguage of {A}ldwych", author= "Huntbach, Matthew", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "51--66", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "Aldwych is a general purpose programming language which we have developed in order to provide a mechanism for practical programming which can be thought of in an inherently concurrent way. We have described Aldwych elsewhere in terms of a translation to a concurrent logic language. However, it would be more accurate to describe it as translating to a simple operational language which, while able to be represented in a logic-programming like syntax, has lost much of the baggage associated with \&\#8220;logic programming\&\#8221;. This language is only a little more complex than foundational calculi such as the pi-calculus. Its key feature is that all variables are moded with a single producer, and some are linear allowing a reversal of polarity and hence interactive communication." } @InProceedings{YangPoppleton07, title = "{JCSP}ro{B}: {I}mplementing {I}ntegrated {F}ormal {S}pecifications in {C}oncurrent {J}ava", author= "Yang, Letu and Poppleton, Michael R.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "67--88", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "The ProB model checker provides tool support for an integrated formal specification approach, combining the classical state-based B language with the event based process algebra CSP. In this paper, we present a developing strategy for implementing such a combined ProB specification as a concurrent Java program. A Java implementation of the combined B and CSP model has been developed using a similar approach to JCSP. A set of translation rules relates the formal model to its Java implementation, and we also provide a translation tool JCSProB to automatically generate a Java program from a ProB specification. To demonstrate and exercise the tool, several B/CSP models, varying both in syntactic structure and behavioural/concurrency properties, are translated by the tool. The models manifest the presence and absence of various safety, deadlock, and bounded fairness properties; the generated Java code is shown to faithfully reproduce them. Run-time safety and bounded fairness checking is also demonstrated. The Java programs are discussed to demonstrate our implementation of the abstract B/CSP concurrencymodel in Java. In conclusion we consider the effectiveness and generality of the implementation strategy." } @InProceedings{Fernandes07, title = "{C}omponents with {S}ymbolic {T}ransition {S}ystems: a {J}ava {I}mplementation of {R}endezvous", author= "Fernandes, Fabricio and Passama, Robin and Royer, Jean-Claude", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "89--108", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "Component-based software engineering is becoming an important approach for system development. A crucial issue is to fill the gap between high-level models, needed for design and verification, and implementation. This paper introduces first a component model with explicit protocols based on symbolic transition systems. It then presents a Java implementation for it that relies on a rendezvous mechanism to synchronize events between component protocols. This paper shows how to get a correct implementation of a complex rendezvous in presence of full data types, guarded transitions and, possibly, guarded receipts." } @InProceedings{East07, title = "{C}oncurrent/{R}eactive {S}ystem {D}esign with {H}oneysuckle", author= "East, Ian R.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "109--118", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "Honeysuckle is a language in which to describe systems with prioritized service architecture (PSA), whereby processes communicate values and (mobile) objects deadlock-free under client-server protocol. A novel syntax for the description of service (rather than process) composition is presented and the relation to implementation discussed. In particular, the proper separation of design and implementation becomes possible, allowing independent abstraction and verification." } @InProceedings{OrlicBroenink07a, title = "{CSP} and {R}eal-{T}ime: {R}eality or {I}llusion?", author= "Orlic, Bojan and Broenink, Jan F.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "119--148", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "This paper deals with the applicability of CSP in general and SystemCSP, as a notation and design methodology based on CSP, in particular in the application area of real-time systems. The paper extends SystemCSP by introducing time-related operators as a way to specify time properties. Since SystemCSP aims to be used in practice of real-time systems development, achieving real-time in practice is also addressed. The mismatch between the classical scheduling theories and CSP paradigm is explored. Some practical ways to deal with this mismatch are presented." } @InProceedings{Kerridge07, title = "{T}esting and {S}ampling {P}arallel {S}ystems", author= "Kerridge, Jon", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "149--162", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "The testing of systems using tools such as JUnit is well known to the sequential programming community. It is perhaps less well known to the parallel computing community because it relies on systems terminating so that system outputs can be compared with expected outputs. A highly parallel architecture is described that allows the JUnit testing of non-terminating MIMD process based parallel systems. The architecture is then extended to permit the sampling of a continuously running system. It is shown that this can be achieved using a small number of additional components that can be easily modified to suit a particular sampling situation. The system architectures are presented using a Groovy implementation of the JCSP and JUnit packages." } @InProceedings{Chalmers07, title = "{M}obility in {JCSP}: {N}ew {M}obile {C}hannel and {M}obile {P}rocess {M}odels", author= "Chalmers, Kevin and Kerridge, Jon and Romdhani, Imed", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "163--182", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "The original package developed for network mobility in JCSP, although useful, revealed some limitations in the underlying models permitting code mobility and channel migration. In this paper, we discuss these limitations, as well as describe the new models developed to overcome them. The models are based on two different approaches to mobility in other fields, mobile agents and Mobile IP, providing strong underlying constructs to build upon, permitting process and channel mobility in networked JCSP systems in a manner that is transparent to the user." } @InProceedings{Brown07, title = "{C}++{CSP}2: {A} {M}any-to-{M}any {T}hreading", author= "Brown, Neil C.C.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "183--206", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "The advent of mass-market multicore processors provides exciting new opportunities for parallelism on the desktop. The original C++CSP \&\#8211; a library providing concurrency in C++ \&\#8211; used only user-threads, which would have prevented it taking advantage of this parallelism. This paper details the development of C++CSP2, which has been built around a many-to-many threading model that mixes user-threads and kernel-threads, providing maximum flexibility in taking advantage of multicore and multi-processor machines. New and existing algorithms are described for dealing with the run-queue and implementing channels, barriers and mutexes. The latter two are benchmarked to motivate the choice of algorithm.Most of these algorithms are based on the use of atomic instructions, to gain maximal speed and efficiency. Other issues related to the new design and related to implementing concurrency in a language like C++ that has no direct support for it, are also described. The C++CSP2 library will be publicly released under the LGPL before CPA 2007." } @InProceedings{OrlicBroenink07b, title = "{D}esign {P}rinciples of the {S}ystem{CSP} {S}oftware {F}ramework", author= "Orlic, Bojan and Broenink, Jan F.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "207--228", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "SystemCSP is a graphical design specification language aimed to serve as a basis for the specification of formally verifiable component-based designs. This paper defines a mapping from SystemCSP designs to a software implementation. The possibility to reuse existing practical implementations was analyzed. Comparison is given for different types of execution engines usable in implementing concurrent systems. The main part of the text introduces and explains the design principles behind the software implementation. A synchronization mechanism is introduced that can handle CSP kind of events with event ends possibly scattered on different nodes and OS threads, and with any number of participating event ends, possibly guarded by alternative constructs." } @InProceedings{Bjorndalen07, title = "{P}y{CSP} - {C}ommunicating {S}equential {P}rocesses for {P}ython", author= "Bjørndalen, John Markus and Vinter, Brian and Anshus, Otto J.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "229--248", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "The Python programming language is effective for rapidly specifying programs and experimenting with them. It is increasingly being used in computational sciences, and in teaching computer science. CSP is effective for describing concurrency. It has become especially relevant with the emergence of commodity multi-core architectures. We are interested in exploring how a combination of Python and CSP can benefit both the computational sciences and the hands-on teaching of distributed and parallel computing in computer science. To make this possible, we have developed PyCSP, a CSP library for Python. PyCSP presently supports the core CSP abstractions. We introduce the PyCSP library, its implementation, a few performance benchmarks, and show example code using PyCSP. An early prototype of PyCSP has been used in this year\&\#8217;s Extreme Multiprogramming Class at the CS department, university of Copenhagen with promising results." } @InProceedings{RitsonWelch07, title = "{A} {P}rocess-{O}riented {A}rchitecture for {C}omplex {S}ystem {M}odelling", author= "Ritson, Carl G. and Welch, Peter H.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "249--266", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "A fine-grained massively-parallel process-oriented model of platelets (potentially artificial) within a blood vessel is presented. This is a CSP inspired design, expressed and implemented using the occam-pi language. It is part of the TUNA pilot study on nanite assemblers at the universities of York, Surrey and Kent. The aim for this model is to engineer emergent behaviour fromthe platelets, such that they respond to a wound in the blood vessel wall in a way similar to that found in the human body \&\#8211; i.e. the formation of clots to stem blood flow from the wound and facilitate healing. An architecture for a three dimensional model (relying strongly on the dynamic and mobile capabilities of occam-pi) is given, along with mechanisms for visualisation and interaction. The biological accuracy of the current model is very approximate. However, its process-oriented nature enables simple refinement (through the addition of processes modelling different stimulants/inhibitors of the clotting reaction, different platelet types and other participating organelles) to greater and greater realism. Even with the current system, simple experiments are possible and have scientific interest (e.g. the effect of platelet density on the success of the clotting mechanism in stemming blood flow: too high or too low and the process fails). General principles for the design of large and complex system models are drawn. The described case study runs to millions of processes engaged in ever-changing communication topologies. It is free from deadlock, livelock, race hazards and starvation by design, employing a small set of synchronisation patterns for which we have proven safety theorems." } @InProceedings{Razavi07, title = "{C}oncurrency {C}ontrol and {R}ecovery {M}anagement for {O}pen e-{B}usiness {T}ransactions", author= "Razavi, Amir R. and Moschoyiannis, Sotiris K. and Krause, Paul J.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "267--286", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "Concurrency control mechanisms such as turn-taking, locking, serialization, transactional locking mechanism, and operational transformation try to provide data consistency when concurrent activities are permitted in a reactive system. Locks are typically used in transactional models for assurance of data consistency and integrity in a concurrent environment. In addition, recovery management is used to preserve atomicity and durability in transaction models. Unfortunately, conventional lock mechanisms severely (and intentionally) limit concurrency in a transactional environment. Such lock mechanisms also limit recovery capabilities. Finally, existing recovery mechanisms themselves afford a considerable overhead to concurrency. This paper describes a new transaction model that supports release of early results inside and outside of a transaction, decreasing the severe limitations of conventional lock mechanisms, yet still warranties consistency and recoverability of released resources (results). This is achieved through use of a more flexible locking mechanism and by using two types of consistency graph. This provides an integrated solution for transaction management, recovery management and concurrency control. We argue that these are necessary features for management of long-term transactions within \"digital ecosystems\" of small to medium enterprises." } @InProceedings{JorgensenSuenson07, title = "trancell - an {E}xperimental {ETC} to {C}ell {BE} {T}ranslator", author= "Jørgensen, Ulrik Schou and Suenson, Espen", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "287--298", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "This paper describes trancell, a translator and associated runtime environment that allows programs written in the occam programming language to be run on the Cell BE microarchitecture. trancell cannot stand alone, but requires the front end from the KRoC/Linux compiler for generating Extended Transputer Code (ETC), which is then translated into native Cell SPU assembly code and linked with the trancell runtime. The paper describes the difficulties in implementing occam on the Cell, notably the runtime support required for implementing channel communications and true parallelism. Various benchmarks are examined to investigate the success of the approach." } @InProceedings{Sputh07, title = "{A} {V}ersatile {H}ardware-{S}oftware {P}latform for {I}n-{S}itu {M}onitoring {S}ystems", author= "Sputh, Bernhard H.C. and Faust, Oliver and Allen, Alastair R.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "299--312", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "In-Situ Monitoring systems measure and relay environmental parameters. From a system design perspective such devices represent one node in a network. This paper aims to extend the networking idea from the system level towards the design level. We describe In-Situ Monitoring systems as network of components. In the proposed design these components can be implemented in either hardware or software. Therefore, we need a versatile hardware-software platform to accommodate the particular requirements of a wide range of In-Situ Monitoring systems. The ideal testing ground for such a versatile hardware-software platform are FPGAs (Field Programmable Gate Arrays) with embedded CPUs. The CPUs execute software processes which represent software components. The FPGA part can be used to implement hardware components in the form of hardware processes and it can be used to interface to other hardware components external to the processor. In effect this setup constitutes a network of communicating sequential processes within a chip. This paper presents a design flow based on the theory of CSP. The idea behind this design flow is to have a CSP model which is turned into a network of hardware and software components. With the proposed design flow we have extended the networking aspect of sensor networks towards the system design level. This allows us to treat In-Situ Measurement systems as sub-networks within a sensor network. Furthermore, the CSP based approach provides abstract models of the functionality which can be tested. This yields more reliable system designs." } @InProceedings{Teig07, title = "{H}igh {C}ohesion and {L}ow {C}oupling: the {O}ffice {M}apping {F}actor", author= "Teig, Øyvind", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "313--322", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "This case observation describes how an embedded industrial software architecture was \&\#8220;mapped\&\#8221; onto an office layout. It describes a particular type of program architecture that does this mapping rather well. The more a programmer knows what to do, and so may withdraw to his office and do it, the higher the cohesion or completeness. The less s/he has to know about what is going on in other offices, the lower the coupling or disturbance. The project, which made us aware of this, was an embedded system built on the well-known process data-flow architecture. All interprocess communication that carried data was on synchronous, blocking channels. In this programming paradigm, it is possible for a process to refuse to \&\#8220;listen\&\#8221; on a channel while it is busy doing other things. We think that this in a way corresponds to closing the door to an office. When another process needs to communicate with such a process, it will simply be blocked (and descheduled). No queuing is done. The process, or the programmer, need not worry about holding up others. The net result seems to be good isolation of work and easier implementation. The isolation also enables faster pinpointing of where an error may be and, hence, in fixing the error in one place only. Even before the product was shipped, it was possible to keep the system with close to zero known errors. The paradigm described here has become a valuable tool in our toolbox. However, when this paradigm is used, one must also pay attention should complexity start to grow beyond expectations, as it may be a sign of too high cohesion or too little coupling." } @InProceedings{RitsonBarnes07, title = "{A} {P}rocess {O}riented {A}pproach to {USB} {D}river {D}evelopment", author= "Ritson, Carl G. and Barnes, Frederick R. M.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "323--338", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "Operating-systems are the core software component of many modern computer systems, ranging from small specialised embedded systems through to large distributed operating-systems. The demands placed upon these systems are increasingly complex, in particular the need to handle concurrency: to exploit increasingly parallel (multi-core) hardware; support increasing numbers of user and system processes; and to take advantage of increasingly distributed and decentralised systems. The languages and designs that existing operating-systems employ provide little support for concurrency, leading to unmanageable programming complexities and ultimately errors in the resulting systems; hard to detect, hard to remove, and almost impossible to prove correct.Implemented in occam-p, a CSP derived language that provides guarantees of freedom from race-hazards and aliasing error, the RMoX operating-system represents a novel approach to operating-systems, utilising concurrency at all levels to simplify design and implementation. This paper presents the USB (universal serial bus) device-driver infrastructure used in the RMoX system, demonstrating that a highly concurrent process-orientated approach to device-driver design and implementation is feasible, efficient and results in systems that are reliable, secure and scalable." } @InProceedings{Simpson07, title = "{A} {N}ative {T}ransterpreter for the {LEGO} {M}indstorms {RCX}", author= "Simpson, Jonathan and Jacobsen, Christian L. and Jadud, Matthew C.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "339--348", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "The LEGO Mindstorms RCX is a widely deployed educational robotics platform. This paper presents a concurrent operating environment for the Mindstorms RCX, implemented natively using occam-pi running on the Transterpreter virtual machine. A concurrent hardware abstraction layer aids both the developer of the operating system and facilitates the provision of process-oriented interfaces to the underlying hardware for students and hobbyists interested in small robotics platforms." } @InProceedings{Welch07, title = "{I}ntegrating and {E}xtending {JCSP}", author= "Welch, Peter H. and Brown, Neil C.C. and Moores, James and Chalmers, Kevin and Sputh, Bernhard H.C.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "349--369", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "This paper presents the extended and re-integrated JCSP library of CSP packages for Java. It integrates the differing advances made by Quickstone's JCSP Network Edition and the \"core\" library maintained at Kent. A more secure API for connecting networks and manipulating channels is provided, requiring significant internal re-structuring. This mirrors developments in the occam-pi language for mandated direction specifiers on channel-ends. For JCSP, promoting the concept of channel-ends to first-class entities has both semantic benefit (the same as for occampi) and increased safety. Major extensions include alting barriers (classes supporting external choice over multiple multi-way synchronisations), channel output guards (straightforward once we have the alting barriers), channel poisoning (for the safe and simple termination of networks or sub-networks) and extended rendezvous on channel communications (that simplify the capture of several useful synchronisation design patterns). Almost all CSP systems can now be directly captured with the new JCSP. The new library is available under the LGPL open source license." } @InProceedings{Singh07, title = "{H}ardware/{S}oftware {S}ynthesis and {V}erification {U}sing {E}sterel", author= "Singh, Satnam", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "371--378", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "The principal contribution of this paper is the demonstration of a promising technique for the synthesis of hardware and software from a single specification which is also amenable to formal analysis. We also demonstrate how the notion of synchronous observers may provide a way for engineers to express formal assertions about circuits which may be more accessible then the emerging grammar based approaches. We also report that the semantic basis for the system we evaluate pays dividends when formal static analysis is performed using model checking." } @InProceedings{McEwanSchneider07, title = "{M}odeling and {A}nalysis of the {AMBA} {B}us {U}sing {CSP} and {B}", author= "McEwan, Alistair A. and Schneider, Steve", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "379--398", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "In this paper, we present a formal model and analysis of the AMBA Advanced High-performance Bus (AHB) on-chip bus. The model is given in CSP\textbar\textbarB\&\#8212;an integration of the process algebra CSP and the state-based formalism B. We describe the theory behind the integration of CSP and B. We demonstrate how the model is developed from the informal ARM specification of the bus. Analysis is performed using the model-checker ProB. The contribution of this paper may be summarised as follows: presentation of work in progress towards a formal model of the AMBA AHB protocol such that it may be used for inclusion in, and analysis of, co-design systems incorporating the bus, an evaluation of the integration of CSP and B in the production of such a model, and a demonstration and evaluation of the ProB tool in performing this analysis. The work in this paper was carried out under the Future Technologies for Systems Design Project at the University of Surrey, sponsored by AWE." } @InProceedings{IfillSchneider07, title = "{A} {S}tep {T}owards {R}efining and {T}ranslating {B} {C}ontrol {A}nnotations to {H}andel-{C}", author= "Ifill, Wilson and Schneider, Steve", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "399--424", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "Research augmenting B machines presented at B2007 has demonstrated how fragments of control flow expressed as annotations can be added to associated machine operations, and shown to be consistent. This enables designers\&\#8217; understanding about local relationships between successive operations to be captured at the point the operations are written, and used later when the controller is developed. This paper introduces several new annotations and I/O into the framework to take advantage of hardware\&\#8217;s parallelism and to facilitate refinement and translation. To support the new annotations additional CSP control operations are added to the control language that now includes: recursion, prefixing, external choice, if-then-else, and sequencing. We informally sketch out a translation to Handel-C for prototyping." } @InProceedings{GrantEvans07, title = "{T}owards the {F}ormal {V}erification of a {J}ava {P}rocessor in {E}vent-{B}", author= "Grant, Neil and Evans, Neil", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "425--442", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "Formal verification is becoming more and more important in the production of high integrity microprocessors. The general purpose formal method called Event-B is the latest incarnation of the B Method: it is a proof-based approach with a formal notation and refinement technique for modelling and verifying systems. Refinement enables implementation-level features to be proven correct with respect to an abstract specification of the system. In this paper we demonstrate an initial attempt to model and verify Sandia National Laboratories' Score processor using Event-B. The processor is an (almost complete) implementation of a Java Virtual Machine in hardware. Thus, refinement-based verification of the Score processor begins with a formal specification of Java bytecode. Traditionally, B has been directed at the formal development of software systems. The use of B in hardware verification could provide a means of developing combined software/hardware systems, i.e. codesign." } @InProceedings{Wickstrom07, title = "{A}dvanced {S}ystem {S}imulation, {E}mulation and {T}est ({ASSET})", author= "Wickstrom, Gregory", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "443--464", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "Maturing embeddable real-time concepts into deployable high consequence systems faces numerous challenges. Although overcoming these challenges can be aided by commercially available processes, toolsets, and components, they often fall short of meeting the needs at hand. This paper will review the development of a framework being assembled to address many of the shortcomings while attempting to leverage commercial capabilities as appropriate." } @InProceedings{Duller07, title = "{D}evelopment of a {F}amily of {M}ulti-{C}ore {D}evices {U}sing {H}ierarchical {A}bstraction", author= "Duller, Andrew and Gray, Alan and Towner, Daniel and Iles, Jamie and Panesar, Gajinder and Robbins, Will", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "465--478", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "picoChip has produced a range of commercially deployed multi-core devices, all of which have the same on-chip deterministic communications structure (the picoBus) but vary widely in the number and type of cores which make up the devices. Systems are developed from processes connected using unidirectional signals. Individual processes are described using standard C or assembly language and are grouped together in a hierarchical description of the overall system. This paper discusses how families of chips may be developed by \"hardening\" structures in the hierarchy of an existing software system. Hardening is the process of replacing sets of communicating processes with an equivalent hardware accelerator, without changing the interface to that sub-system. Initial development is performed using a completely software implementation, which has advantages in terms of \"time to market\". When cost/power reductions are required, the proposed hardening process can be used to convert certain parts of a design into fixed hardware. These can then be included in the next generation of the device. The same tool chain is used for all devices and this means that verification of the hardware accelerator against the original system is simplified. The methodology discussed has been used to produce a family of devices which have been deployed in a wide range of wireless applications around the world." } @InProceedings{TodmanLuk07, title = "{D}omain {S}pecific {T}ransformations for {H}ardware {R}ay {T}racing", author= "Todman, Tim and Luk, Wayne", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "479--492", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "We present domain-specific transformations of the ray-tracing algorithm targeting reconfigurable hardware devices. Ray tracing is a computationally intensive algorithm used to produce photorealistic images of three-dimensional scenes.We show how the proposed transformations can adapt the basic ray-tracing algorithm to a breadth-first style, and give estimates for the hardware needed for realtime raytracing." } @InProceedings{VladimirovaWu07, title = "{A} {R}econfigurable {S}ystem-on-{C}hip {A}rchitecture for {P}ico-{S}atellite {M}issions", author= "Vladimirova, Tanya and Wu, Xiaofeng", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "493--502", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "Spacecraft operate in the unique space environment and are exposed to various types of radiation. Radiation effects can damage the on-board electronic circuits, particularly silicon devices. There is a pressing need for a remote upgrading capability which will allow electronic circuits on-board satellites to self-repair and evolve their functionality. One approach to addressing this need is to utilize the hardware reconfigurability of Field Programmable Gate Arrays. FPGAs nowadays are suitable for implementation of complex on-board system-on-chip designs. Leading-edge technology enables innovative solutions, permitting lighter picosatellite systems to be designed. This paper presents a reconfigurable system-onchip architecture for pico-satellite on-board data processing and control. The SoC adopts a modular bus-centric architecture using the AMBA bus and consists of soft intellectual property cores. In addition the SoC is capable of remote partial reconfiguration at run time." } @InProceedings{CassarAbela07, title = "{T}ransactional {CSP} {P}rocesses", author= "Cassar, Gail and Abela, Patrick", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "503--504", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "Long-lived transactions (LLTs) are transactions intended to be executed over an extended period of time ranging from seconds to days. Traditional transactions maintain data integrity through ACID properties which ensure that: a transaction will achieve an \"all-or-nothing\" effect (atomicity); system will be in a legal state before a transaction begins and after it ends (consistency); a transaction is treated independently from any other transactions (isolation); once a transaction commits, its effects are not lost (durability). However, it is impractical and undesirable to maintain full ACID properties throughout the whole duration of a long lived transaction. Transaction models for LLTs, relax the ACID properties by organizing a long-lived transaction as a series of activities. Each activity is a discrete transactional unit of work which releases transactional locks upon its execution. Activities are executed in sequence and can either commit, rollback or suspend execution of the transaction. The long-lived transaction commits if all its activities complete successfully. If any of the activities fail, the long lived transaction should roll back by undoing any work done by already completed activities. Unless an activity requires the result of a previously committed activity, there is no constraint which specifies that the various activities belonging to a long lived transaction execute sequentially. Our proposed research focuses on combining long lived transactions and CSP such that independent activities execute in parallel thus achieving flexibility and better performance for long lived transactions. Very much as the occam CSP-based constructs, SEQ and PAR, allow processes to be executed sequentially or concurrently, the proposed SEQ\_LLT and PAR\_LLT constructs can be used to specify the sequential or concurrent execution of transactions. Two activities that are coordinated with the SEQ\_LLT construct are evaluated in such a way that the second activity is executed only after the first activity commits. This corresponds to the SEQ construct which, from a concurrency perspective, executes in such a way that the second process starts its execution after the first process is complete. Similarly, PAR\_LLT specifies that activities can start their execution, independently from whether any other activities have committed their transaction or not. We also use the same synchronization mechanisms provided by CSP to have concurrent activities communicate with one another. An activity which \"waits\" on a channel for communication with another concurrent activity is automatically suspended (and its transactional locks released) until it receives a message from another activity. A prototype implementation of the described constructs and some example applications have been implemented on SmartPay LLT (a platform loosely based on JSR95 developed by Ixaris Systems). This work has been part of an undergraduate dissertation at the University of Malta." } @InProceedings{BurginSmith07, title = "{A}lgebras of {A}ctions in {C}oncurrent {P}rocesses", author= "Burgin, Mark and Smith, Marc L.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "505--506", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "We introduce a high-level metamodel, EAP (event-action-process), for reasoning about concurrent processes. EAP shares with CSP notions of observable events and processes, but as its name suggests, EAP is also concerned with actions. Actions represent an intermediate level of event composition that provide the basis for a hierarchical structure that builds up from individual, observable events, to processes that may themselves be units of composition. EAP\&\#8217;s composition hierarchy corresponds to the reality that intermediate units of composition exist, and that these intermediate units don\&\#8217;t always fall neatly within process boundaries. One prominent example of an intermediate unit of composition, or action, is threads. Threads of execution are capable of crossing process boundaries, and one popular programming paradigm, object-oriented programming, encourages this approach to concurrent program design. While we may advocate for more disciplined, process-oriented design, the demand for better models for reasoning about threads remains. On a more theoretical level, traces of a computation are also actions. Traces are event structures, composed by the CSP observer, according to a set of rules for recording the history of a computation. In one of the author\&\#8217;s model for viewcentric reasoning (VCR), the CSP observer is permitted to record simultaneous events without interleaving; and in previous joint work by the authors, the extended VCR (EVCR) model permits the CSP observer to record events with duration, so that events may overlap entirely, partially, or not at all. Sequential composition may be viewed as a special case of parallel composition\&\#8212;one of many forms of composition we wish to be better able to reason about. Since such diverse types of composition exist, at the event, action, and process levels; and because such problematic actions as threads exist in real systems, we must find more appropriate models to reason about such systems. To this end, we are developing algebras at different levels of compositionality to address these goals. In particular, we are interested in a corresponding hierarchy of algebras, at the event, action, and process levels. The present focus of our efforts is at the action level, since these are the least well understood. This talk presents fundamental notions of actions and examples of actions in the context of real systems. A diversity of possible compositions at the action level will be revealed and discussed, as well as our progress on the action algebra itself." } @InProceedings{Dimmich07, title = "{U}sing occam-pi {P}rimitives with the {C}ell {B}roadband {E}ngine", author= "Dimmich, Damian J.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "507--508", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "The Cell Broadband Engine has a unique non-heterogeneous archi- tecture, consisting of an on-chip network of one general purpose PowerPC pro- cessor (the PPU), and eight dedicated vector processing units (the SPUs). These processors are interconnected by a high speed ring bus, enabling the use of different logical network topologies. When programming the Cell Broadband Engine using languages such as C, a developer is faced with a number of chal- lenges. For instance, parallel execution and synchronisation between proces- sors, as well as concurrency on individual processors, must be explicitly, and carefully, managed. It is our belief that languages explicitly supporting concur- rency are able to offer much better abstractions for programming architectures such as the Cell Broadband Engine. Support for running occam- programs on the Cell Broadband Engine has existed in the Transterpreter for some time. This support has however not featured efficient inter-processor communication and barrier synchronisation, or automatic deadlock detection. We discuss some of the changes required to the occam- scheduler to support these features on the Cell Broadband Engine. The underlying on-chip communication and synchronisation mechanisms are explored in the development of these new scheduling algorithms. Benchmarks of the communications performance are provided, as well as a discussion of how to use the occam- language to distribute a program onto a Cell Broadband Engine\&\#8217;s processors. The Transterpreter runtime, which already has support for the Cell Broadband Engine, is used as the platform for these experiments. The Transterpreter can be found at www.transterpreter.org." } @InProceedings{Ritson07, title = "{S}hared-{M}emory {M}ulti-{P}rocessor {S}cheduling {A}lgorithms for {CCSP}", author= "Ritson, Carl G.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "509--510", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "CCSP is a monolithic C library which acts as the run-time kernel for occam- programs compiled with the Kent Retargetable occam Compiler (KRoC). Over the past decade, it has grown to encompass many new and powerful features to support the occam-pi language as that has evolved \&\#8211; and continues to evolve \&\#8211; from classical occam. However, despite this wealth of development, the general methodology by which processes are scheduled and executed has changed little from its transputer inspired origins. This talk looks at applying previous research and new ideas to the CCSP scheduler in an effort to exploit fully the potential of new mass-market multicore processor systems. The key objective is to introduce support for shared-memory multicore systems, whilst maintaining the low scheduling overheads that occam-pi users have come to expect. Fundamental to this objective are wait-free data-structures, per-processor run-queues, and a strong will to consolidate and simplify the existing code base." } @InProceedings{Sampson07, title = "{C}ompiling occam to {C} with {T}ock", author= "Sampson, Adam T.", editor= "McEwan, Alistair A. and Schneider, Steve and Ifill, Wilson and Welch, Peter H.", pages = "511--512", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2007", isbn= "978-1-58603-767-3", year= "2007", month= "jul", abstract= "Tock is a new occam compiler from the University of Kent, the latest result of many years\&\#8217; research into compiling concurrent languages. The existing occam compiler generates bytecode which is then translated into native instructions; this reduces opportunities for native code optimisation and limits portability. Tock translates occam into C using the CIF concurrent runtime interface, which can be compiled to efficient native code by any compiler supporting the C99 language standard. The resulting programs combine the safety and featherweight concurrency of occam with the performance and portability of C. Unlike previous attempts at translating occam to C, Tock\&\#8217;s output resembles handwritten CIF code; this eases debugging and takes better advantage of the C compiler\&\#8217;s optimisation facilities. Written in the purely functional language Haskell, Tock uses monadic combinator parsing and generic data structure traversal to provide a flexible environment for experimenting with new compiler and language features." } @InProceedings{Kerridge08d, title = "{S}anta's {G}roovy {H}elper", author= "Kerridge, Jon", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "This talk is prompted by the work on the Santa Claus problem presented elsewhere in this conference by Jason Hurt and Matt Pedersen. A compact version of their solution, using the Groovy macro-extensions to Java and JCSP, will be shown. Listeners should first have attended the presentation of the referenced paper." } @InProceedings{Dixon08, title = "{D}esigning with {S}oftware {D}efined {S}ilicon", author= "Dixon, A.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "This talk will introduce the XMOS XS1-G4 multi-core device and the associated development kit. The design tools and the XC language which can be used to write concurrent software, including direct access to physical input and output pins, will be presented. The concurrency support in XC has its roots in CSP and occam. The flexibility of the XS1 architecture will be shown by demonstrating a number of applications; these include interfacing, communications, motor control and media processing." } @InProceedings{Warren08, title = "{PICOMS}: {P}rioritised {I}nferred {C}hoice {O}ver {M}ultiway {S}ynchronisation", author= "Warren, Douglas N.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "The ability to make a choice over multiway synchronisations (COMS) has always been an integral part of CSP. However, it is something that has been conspicuous by its absence from many concurrent languages, limiting their expressive power. Implementation of a 2-phase commit protocol to resolve such choice can result in large overheads, caused by synchronisation offers having to be withdrawn. The recent Oracle (single-phase) algorithm resolves COMS efficiently, for shared memory concurrency at least. However, the Oracle only deals with \textlessi\textgreaterarbitrary\textless/i\textgreater choice and does not obviously extend to \textlessi\textgreaterprioritised\textless/i\textgreater choice (where we assume the priorities of the participating processes are not in conflict). PICOMS is a proposed efficient method for resolving COMS that honours non-conflicting priorities, with only a modest increase in complexity over the Oracle method." } @InProceedings{Barnes08, title = "{T}owards {G}uaranteeing {P}rocess {O}riented {P}rogram {B}ehaviour", author= "Barnes, Frederick R. M.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "Though we have language guarantees for avoiding race-hazards, and design-rules and formal-methods for guaranteeing freedom from deadlock, livelock and starvation, the work involved in checking the latter typically discourages their use. This talk briefly examines a new approach to guaranteeing process behaviour in occam-\π, that removes most, if not all, of the leg-work involved in checking programs manually \– a process that itself is error prone. Behaviour specifications are given in-program, that our experimental compiler checks against the actual implementation. Furthermore, the compiler is capable of generating the behavioural specification of any process, which it does using a CSP-like language, for use with separate compilation or for other formal verification." } @InProceedings{Roebbers08, title = "{H}andel-{C} {S}ource {L}evel {D}ebugging", author= "Roebbers, Herman", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "Until now, there has been no real source level debugger for Handel-C on the FPGA, such as we are used to having for standard CPUs. As the result of a student graduation project, we now have a possibility to do just that: setting/removing breakpoints, inspecting variables, etc. The talk will provide an impression of what has been achieved and looks a little into the future." } @InProceedings{Kerridge08c, title = "{L}ego {R}obots {U}sing {JCSP}", author= "Kerridge, Jon", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "This talk will demonstrate Lego Mindstorms (TM) robots programmed using leJOS, JCSP and Java. It previews the presentation of \textlessq\textgreaterJCSPre: the Robot Edition To Control LEGO NXT Robots\textless/q\textgreater later in the conference." } @InProceedings{Abramsky08, title = "{T}ypes, {O}rthogonality and {G}enericity: {S}ome {T}ools for {C}ommunicating {P}rocess {A}rchitectures", author= "Abramsky, Samson", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "1--13", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "We shall develop a simple and natural formalization of the idea of \textlessi\textgreaterclient-server\textless/i\textgreater architectures, and, based on this, define a notion of \textlessi\textgreaterorthogonality\textless/i\textgreater between clients and servers, which embodies strong correctness properties, and exposes the rich logical structure inherent in such systems. Then we generalize from pure clients and servers to \textlessi\textgreatercomponents\textless/i\textgreater, which provide some services to the environment, and require others from it. We identify the key notion of \textlessi\textgreatercomposition\textless/i\textgreater of such components, in which some of the services required by one component are supplied by another. This allows complex systems to be built from ultimately simple components. We show that this has the logical form of the \textlessi\textgreaterCut rule\textless/i\textgreater, a fundamental principle of logic, and that it can be enriched with a suitable notion of \textlessi\textgreaterbehavioural types\textless/i\textgreater based on orthogonality, in such a way that correctness properties are preserved by composition. We also develop the basic ideas of how logical constructions can be used to develop \textlessi\textgreaterstructured interfaces\textless/i\textgreater for systems, with operations corresponding to logical rules. Finally, we show how the setting can be enhanced, and made more robust and expressive, by using \textlessi\textgreaternames\textless/i\textgreater (as in the \π-calculus) to allow clients to bind dynamically to generic instances of services." } @InProceedings{OHalloran08, title = "{H}ow to {S}oar with {CSP}", author= "O'Halloran, Colin", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "15--15", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "In this talk, I shall discuss work on the necessary technology required for flight clearance of Autonomous Aircraft employing Agents by reducing the certification problem to small verifiable steps that can be carried out by a machine. The certification of such Agents falls into two parts: the validation of the safety of the Agent; and the verification of the implementation of the agent. The work focuses on the Soar agent language and the main results are: \textlessul\textgreater \textlessli\textgreatera language subset for Soar, designed for formal analysis; \textlessli\textgreatera formal model of the Soar subset written in CSP; \textlessli\textgreatera prototype translator \textquotedblSoar2Csp\textquotedbl from Soar to the CSP model; \textlessli\textgreatera framework for static analysis of Soar agents through model checking using FDR2; \textlessli\textgreaterthe identification of \textquotedblhealthiness conditions\textquotedbl required of any Soar Agent; \textlessli\textgreatera verifiable implementation of the CSP based Soar agents on an FPGA. \textless/ul\textgreater" } @InProceedings{WelchBarnes08, title = "{A} {CSP} {M}odel for {M}obile {C}hannels", author= "Welch, Peter H. and Barnes, Frederick R. M.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "17--33", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "CSP processes have a static view of their environment \— a \textlessi\textgreaterfixed\textless/i\textgreater set of events through which they synchronise with each other. In contrast, the \π-calculus is based on the dynamic construction of events (channels) and their distribution over pre-existing channels. In this way, process networks can be constructed dynamically with processes acquiring new connectivity. For the construction of complex systems, such as Internet trading and the modeling of living organisms, such capabilities have an obvious attraction. The occam-\π multiprocessing language is built upon classical occam, whose design and semantics are founded on CSP. To address the dynamics of complex systems, occam-\π extensions enable the movement of channels (and multiway synchronisation barriers) through channels, with constraints in line with previous occam discipline for safe and efficient programming. This paper reconciles these extensions by building a formal (operational) semantics for mobile channels entirely within CSP. These semantics provide two benefits: formal analysis of occam-\π systems using mobile channels and formal specification of implementation mechanisms for mobiles used by the occam-\π compiler and run-time kernel." } @InProceedings{Sufrin08, title = "{C}ommunicating {S}cala {O}bjects", author= "Sufrin, Bernard", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "35--54", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "In this paper we introduce the core features of CSO (Communicating Scala Objects) \— a notationally convenient embedding of the essence of occam in a modern, generically typed, object-oriented programming language that is compiled to Java Virtual Machine (JVM) code. Initially inspired by an early release of JCSP, CSO goes beyond JCSP expressively in some respects, including the provision of a unitary extended rendezvous notation and appropriate treatment of subtype variance in channels and ports. Similarities with recent versions of JCSP include the treatment of channel ends (we call them ports) as parameterized types. Ports and channels may be transmitted on channels (including inter-JVM channels), provided that an obvious design rule \— the ownership rule \— is obeyed. Significant differences with recent versions of JCSP include a treatment of network termination that is significantly simpler than the \textlessq\textgreaterpoisoning\textless/q\textgreater approach (perhaps at the cost of reduced programming convenience), and the provision of a family of type-parameterized channel implementations with performance that obviates the need for the special-purpose scalar-typed channel implementations provided by JCSP. On standard benchmarks such as Commstime, CSO communication performance is close to or better than that of JCSP and Scala's Actors library." } @InProceedings{KorsgaardHendseth08, title = "{C}ombining {EDF} {S}cheduling with occam using the {T}oc {P}rogramming {L}anguage", author= "Korsgaard, Martin and Hendseth, Sverre", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "55--66", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "A special feature of the occam programming language is that its concurrency support is at the very base of the language. However, its ability to specify scheduling requirements is insufficient for use in some real-time systems. Toc is an experimental programming language that builds on occam, keeping occam's concurrency mechanisms, while fundamentally changing its concept of time. In Toc, deadlines are specified directly in code, replacing occam's priority constructs as themethod for controlling scheduling. Processes are scheduled lazily, in that code is not executed without an associated deadline. The deadlines propagate through channel communications, which means that a task blocked by a channel that is not ready will transfer its deadline through the channel to the dependent task. This allows the deadlines of dependent tasks to be inferred, and also creates a scheduling effect similar to priority inheritance. A compiler and run-time system has been implemented to demonstrate these principles." } @InProceedings{Brown08a, title = "{C}ommunicating {H}askell {P}rocesses: {C}omposable {E}xplicit {C}oncurrency {U}sing {M}onads", author= "Brown, Neil C.C.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "67--83", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "Writing concurrent programs in languages that lack explicit support for concurrency can often be awkward and difficult. Haskell's monads provide a way to explicitly specify sequence and effects in a functional language, and monadic combinators allow composition of monadic actions, for example via parallelism and choice \— two core aspects of Communicating Sequential Processes (CSP).We show how the use of these combinators, and being able to express processes as first-class types (monadic actions) allow for easy and elegant programming of process-oriented concurrency in a new CSP library for Haskell: Communicating Haskell Processes." } @InProceedings{Sampson08, title = "{T}wo-{W}ay {P}rotocols for occam-\π", author= "Sampson, Adam T.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "85--97", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "In the occam-\π programming language, the client-server communication pattern is generally implemented using a pair of unidirectional channels. While each channel's protocol can be specified individually, no mechanism is yet provided to indicate the relationship between the two protocols; it is therefore not possible to statically check the safety of client-server communications. This paper proposes two-way protocols for individual channels, which would both define the structure of messages and allow the patterns of communication between processes to be specified.We show how conformance to two-way protocols can be statically checked by the occam-\π compiler using Honda's session types. These mechanisms would considerably simplify the implementation of complex, dynamic client-server systems." } @InProceedings{East08, title = "{P}rioritized {S}ervice {A}rchitecture: {R}efinement and {V}isual {D}esign", author= "East, Ian R.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "99--113", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "Concurrent/reactive systems can be designed free of deadlock using prioritized service architecture (PSA), subject to simple, statically verified, design rules. The Honeysuckle Design Language (HDL) enables such service-oriented design to be expressed purely in terms of communication, while affording a process-oriented implementation, using the Honeysuckle Programming Language (HPL). A number of enhancements to the service model for system abstraction are described, along with their utility. Finally, a new graphical counterpart to HDL (HVDL) is introduced that incorporates all these enhancements, and which facilitates interactive stepwise refinement." } @InProceedings{Schneider08, title = "{E}xperiments in {T}ranslating {CSP}\textbar\textbar{B} to {H}andel-{C}", author= "Schneider, Steve and Treharne, Helen and McEwan, Alistair A. and Ifill, Wilson", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "115--133", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "This paper considers the issues involved in translating specifications described in the CSP\textbar\textbarB formal method into Handel-C. There have previously been approaches to translating CSP descriptions to Handel-C, and the work presented in this paper is part of a programme of work to extend it to include the B component of a CSP\textbar\textbarB description. Handel-C is a suitable target language because of its capability of programming communication and state, and its compilation route to hardware. The paper presents two case studies that investigate aspects of the translation: a buffer case study, and an abstract arbiter case study. These investigations have exposed a number of issues relating to the translation of the B component, and have identified a range of options available, informing more recent work on the development of a style for CSP\textbar\textbarB specifications particularly appropriate to translation to Handel-C." } @InProceedings{Groothuis08, title = "{FPGA} {B}ased {C}ontrol of a {P}roduction {C}ell {S}ystem", author= "Groothuis, Marcel A. and Van Zuijlen, Jasper J.P. and Broenink, Jan F.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "135--148", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "Most motion control systems for mechatronic systems are implemented on digital computers. In this paper we present an FPGA based solution implemented on a low cost Xilinx Spartan III FPGA. A Production Cell setup with multiple parallel operating unit is chosen as test case. The embedded control software for this system is designed in gCSP using a reusable layered CSP based software structure. gCSP is extended with automatic Handel-C code generation for configuring the FPGA. Many motion control systems use floating point calculations for the loop controllers. Low cost general purpose FPGAs do not implement hardware-based floating point units. The loop controllers for this system are converted from floating point to integer-based calculations using a stepwise refinement approach. The result is a completely FPGAbased motion control system with better performance figures than previous CPUbased implementations." } @InProceedings{Athaide08, title = "{S}hared-{C}lock {M}ethodology for {T}ime-{T}riggered {M}ulti-{C}ores", author= "Athaide, Keith F. and Pont, Michael J. and Ayavoo, Devaraj", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "149--162", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "The co-operative design methodology has significant advantages when used in safety-related systems. Coupled with the time-triggered architecture, the methodology can result in robust and predictable systems. Nevertheless, use of a co-operative design methodology may not always be appropriate especially when the system possesses tight resource and cost constraints. Under relaxed constraints, it might be possible to maintain a co-operative design by introducing additional software processing cores to the same chip. The resultant multi-core microcontroller then requires suitable design methodologies to ensure that the advantages of time-triggered co-operative design are maintained as far as possible. This paper explores the application of a time-triggered distributed-systems protocol, called \textlessq\textgreatershared-clock\textless/q\textgreater, on an eight-core microcontroller. The cores are connected in a mesh topology with no hardware broadcast capabilities and three implementations of the shared-clock protocol are examined. The custom multi-core system and the network interfaces used for the study are also described. The network interfaces share higher level serialising logic amongst channels, resulting in low hardware overhead when increasing the number of channels." } @InProceedings{Faust08a, title = "{T}ransfer {R}equest {B}roker: {R}esolving {I}nput-{O}utput {C}hoice", author= "Faust, Oliver and Sputh, Bernhard H.C. and Allen, Alastair R.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "163--177", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "The refinement of a theoretical model which includes external choice over output and input of a channel transaction into an implementation model is a longstanding problem. In the theory of communicating sequential processes this type of external choice translates to resolving input and output guards. The problem arises from the fact that most implementation models incorporate only input guard resolution, known as alternation choice. In this paper we present the transaction request broker process which allows the designer to achieve external choice over channel ends by using only alternation. The resolution of input and output guards is refined into the resolution of input guards only. To support this statement we created two models. The first model requires resolving input and output guards to achieve the desired functionality. The second model incorporates the transaction request broker to achieve the same functionality by resolving only input guards.We use automated model checking to prove that both models are trace equivalent. The transfer request broker is a single entity which resolves the communication between multiple transmitter and receiver processes." } @InProceedings{Badban08, title = "{M}echanical {V}erification of a {T}wo-{W}ay {S}liding {W}indow {P}rotocol", author= "Badban, Bahareh and Fokkink, Wan and Van De Pol, Jaco", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "179--202", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "We prove the correctness of a two-way sliding window protocol with piggybacking, where the acknowledgments of the latest received data are attached to the next data transmitted back into the channel. The window size of both parties are considered to be finite, though they can be of different sizes. We show that this protocol is equivalent (branching bisimilar) to a \textlessi\textgreaterpair of FIFO\textless/i\textgreater queues of finite capacities. The protocol is first modeled and manually proved for its correctness in the process algebraic language of \μCRL. We use the theorem prover PVS to formalize and to mechanically prove the correctness. This implies both safety and liveness (under the assumption of fairness)." } @InProceedings{Sputh08, title = "{RRABP}: {P}oint-to-{P}oint {C}ommunication over {U}nreliable {C}omponents", author= "Sputh, Bernhard H.C. and Faust, Oliver and Allen, Alastair R.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "203--217", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "This paper establishes the security, stability and functionality of the resettable receiver alternating bit protocol. This protocol creates a reliable and blocking channel between sender and receiver over unreliable non-blocking communication channels. Furthermore, this protocol permits the sender to be replaced at any time, but not under all conditions without losing a message. The protocol is an extension to the alternating bit protocol with the ability for the sender to synchronise the receiver and restart the transmission. The resulting protocol uses as few messages as possible to fulfil its duty, which makes its implementation lightweight and suitable for embedded systems. An unexpected outcome of this work is the large number of different messages needed to reset the receiver reliably." } @InProceedings{Faust08b, title = "{IC}2{IC}: a {L}ightweight {S}erial {I}nterconnect {C}hannel for {M}ultiprocessor {N}etworks", author= "Faust, Oliver and Sputh, Bernhard H.C. and Allen, Alastair R.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "219--235", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "IC2IC links introduce blocking functionality to a low latency high performance data link between independent processors. The blocking functionality was achieved with the so-called alternating bit protocol. Furthermore, the protocol hardens the link against message loss and message duplication. This paper provides a detailed discussion of the link signals and the protocol layer. The practical part shows an example implementation of the IC2IC serial link. This example implementation establishes an IC2IC link between two configurable hardware devices. Each device incorporates a process network which implements the IC2IC transceiver functionality. This example implementation helped us to explore the practical properties of the IC2IC serial interconnect. First, we verified the blocking capability of the link and second we analysed different reset conditions, such as disconnect and bit-error." } @InProceedings{OpreanPedersen08, title = "{A}synchronous {A}ctive {O}bjects in {J}ava", author= "Oprean, George and Pedersen, Jan Bækgaard", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "237--254", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "Object Oriented languages have increased in popularity over the last two decades. The OO paradigm claims to model the way objects interact in the real world. All objects in the OO model are passive and all methods are executed synchronously in the thread of the caller. Active objects execute their methods in their own threads. The active object queues method invocations and executes them one at a time. Method invocations do not overlap, thus the object cannot be put into or seen to be in an inconsistent state. We propose an active object system implemented by extending the Java language with four new keywords: \textlesscode\textgreateractive\textless/code\textgreater, \textlesscode\textgreaterasync\textless/code\textgreater, \textlesscode\textgreateron\textless/code\textgreater and \textlesscode\textgreaterwaitfor\textless/code\textgreater. We have modified Sun's open-source compiler to accept the new keywords and to translate them to regular Java code during desugaring phase. We achieve this through the use of RMI, which as a side effect, allows us to utilize a cluster of work stations to perform distributed computing" } @InProceedings{Kerridge08a, title = "{JCSP}re: the {R}obot {E}dition {T}o {C}ontrol {LEGO} {NXT} {R}obots", author= "Kerridge, Jon and Panayotopoulos, Alex and Lismore, Patrick", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "255--270", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "JCSPre is a highly reduced version of the JCSP (Communicating Sequential Processes for Java) parallel programming environment. JCSPre has been implemented on a LEGO Mindstorms NXT brick using the LeJOS Java runtime environment. The LeJOS environment provides an abstraction for the NXT Robot in terms of Sensors, Sensor Ports and Motors, amongst others. In the implementation described these abstractions have been converted into the equivalent active component that is much easier to incorporate into a parallel robot controller. Their use in a simple line following robot is described, thereby demonstrating the ease with which robot controllers can be built using parallel programming principles. As a further demonstration we show how the line following robot controls a slave robot by means of Bluetooth communications." } @InProceedings{Chalmers08a, title = "{A} {C}ritique of {JCSP} {N}etworking", author= "Chalmers, Kevin and Kerridge, Jon and Romdhani, Imed", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "271--291", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "We present a critical investigation of the current implementation of JCSP Networking, examining in detail the structure and behavior of the current architecture. Information is presented detailing the current architecture and how it operates, and weaknesses in the implementation are raised, particularly when considering resource constrained devices. Experimental work is presented that illustrate memory and computational demand problems and an outline on how to overcome these weaknesses in a new implementation is described. The new implementation is designed to be lighter weight and thus provide a framework more suited for resource constrained devices which are a necessity in the field of ubiquitous computing." } @InProceedings{RitsonSimpson08, title = "{V}irtual {M}achine {B}ased {D}ebugging for occam-\π", author= "Ritson, Carl G. and Simpson, Jonathan", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "293--307", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "While we strive to create robust language constructs and design patterns which prevent the introduction of faults during software development, an inevitable element of human error still remains.We must therefore endeavor to ease and accelerate the process of diagnosing and fixing software faults, commonly known as debugging. Current support for debugging occam-\π programs is fairly limited. At best the developer is presented with a reference to the last known code line executed before their program abnormally terminated. This assumes the program does in fact terminate, and does not instead live-lock. In cases where this support is not sufficient, developers must instrument their own tracing support, \textlessq\textgreater\textlesscode\textgreaterprintf\textless/code\textgreater style\textless/q\textgreater. An exercise which typically enlightens one as to the true meaning of concurrency ... In this paper we explore previous work in the field of debugging occam programs and introduce a new method for run-time monitoring of occam-\π applications, based on the Transterpreter virtual machine interpreter. By adding a set of extensions to the Transterpreter, we give occam-\π processes the ability to interact with their execution environment. Use of a virtual machine allows us to expose program execution state which would otherwise require non-portable or specialised hardware support. Using a model which bears similarities to that applied when debugging embedded systems with a JTAG connection, we describe debugging occam-\π by mediating the execution of one execution process from another." } @InProceedings{BjorndalenSampson08, title = "{P}rocess-{O}riented {C}ollective {O}perations", author= "Bjørndalen, John Markus and Sampson, Adam T.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "309--328", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "Distributing process-oriented programs across a cluster of machines requires careful attention to the effects of network latency. The MPI standard, widely used for cluster computation, defines a number of collective operations: efficient, reusable algorithms for performing operations among a group of machines in the cluster. In this paper, we describe our techniques for implementing MPI communication patterns in process-oriented languages, and how we have used them to implement collective operations in PyCSP and occam-\π on top of an asynchronous messaging framework. We show how to make use of collective operations in distributed processoriented applications. We also show how the process-oriented model can be used to increase concurrency in existing collective operation algorithms." } @InProceedings{BrownSmith08, title = "{R}epresentation and {I}mplementation of {CSP} and {VCR} {T}races", author= "Brown, Neil C.C. and Smith, Marc L.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "329--345", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "Communicating Sequential Processes (CSP) was developed around a formal algebra of processes and a semantics based on traces (and failures and divergences). A trace is a record of the events engaged in by a process. Several programming languages use, or have libraries to use, CSP mechanisms to manage their concurrency. Most of these lack the facility to record the trace of a program. A standard trace is a flat list of events but structured trace models are possible that can provide more information such as the independent or concurrent engagement of the process in some of its events. One such trace model is View-Centric Reasoning (VCR), which offers an additional model of tracing, taking into account the multiple, possibly imperfect views of a concurrent computation. This paper also introduces \textlessq\textgreaterstructural\textless/q\textgreater traces, a new type of trace that reflects the nested parallelism in a CSP system. The paper describes the automated generation of these three trace types in the Communicating Haskell Processes (CHP) library, using techniques which could easily be applied in other libraries such as JCSP and C++CSP2. The ability to present such traces of a concurrent program assists in understanding the behaviour of real CHP programs and for debugging when the trace behaviours are wrong. These ideas and tools promote a deeper understanding of the association between practicalities of real systems software and the underlying CSP formalism." } @InProceedings{FriborgVinter08, title = "{CSPB}uilder - {CSP} based {S}cientific {W}orkflow {M}odeling", author= "Friborg, Rune Møllegard and Vinter, Brian", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "347--363", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "This paper introduces a framework for building CSP based applications, targeted for clusters and next generation CPU designs. CPUs are produced with several cores today and every next CPU generation will feature even more cores, resulting in a requirement for concurrency not previously demanded. The framework is CSP-presented as a scientific workflow model, specialized for scientific computing application. The purpose of the framework is to enable scientists to gain access to large parallel computation resources, which have been off limits because of the difficulty of concurrent programming using threads and locks." } @InProceedings{SimpsonJacobsen08, title = "{V}isual {P}rocess-{O}riented {P}rogramming for {R}obotics", author= "Simpson, Jonathan and Jacobsen, Christian L.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "365--380", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "When teaching concurrency, using a \textlessi\textgreaterprocess-oriented language\textless/i\textgreater, it is often introduced through a visual representation of programs in the form of \textlessi\textgreaterprocess network diagrams\textless/i\textgreater. These diagrams allow the design of and abstract reasoning about programs, consisting of concurrently executing communicating processes, without needing any syntactic knowledge of the eventual implementation language. Process network diagrams are usually drawn on paper or with general-purpose diagramming software, meaning the program must be implemented as syntactically correct program code before it can be run. This paper presents \textlessi\textgreaterPOPed\textless/i\textgreater, an introductory parallel programming tool leveraging process network diagrams as a visual language for the creation of process-oriented programs. Using only visual layout and connection of pre-created components, the user can explore process orientation without knowledge of the underlying programming language, enabling a \textlessq\textgreaterprocesses first\textless/q\textgreater approach to parallel programming. POPed has been targeted specifically at basic robotic control, to provide a context in which introductory parallel programming can be naturally motivated." } @InProceedings{HurtPedersen08, title = "{S}olving the {S}anta {C}laus {P}roblem: a {C}omparison of {V}arious {C}oncurrent {P}rogramming {T}echniques", author= "Hurt, Jason and Pedersen, Jan Bækgaard", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "381--396", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "The Santa Claus problem provides an excellent exercise in concurrent programming. It can be used to show the simplicity or complexity of solving problems using a particular set of concurrency mechanisms and offers a comparison of these mechanisms. Shared-memory constructs, message passing constructs, and process oriented constructs will be used in various programming languages to solve the Santa Claus Problem. Various concurrency mechanisms available will be examined and analyzed as to their respective strengths and weaknesses." } @InProceedings{Kerridge08b, title = "{M}obile {A}gents and {P}rocesses using {C}ommunicating {P}rocess {A}rchitectures", author= "Kerridge, Jon and Haschke, Jens-Oliver and Chalmers, Kevin", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "397--410", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "The mobile agent concept has been developed over a number of years and is widely accepted as one way of solving problems that require the achievement of a goal that cannot be serviced at a specific node in a network. The concept of a mobile process is less well developed because implicitly it requires a parallel environment within which to operate. In such a parallel environment a mobile agent can be seen as a specialization of a mobile process and both concepts can be incorporated into a single application environment, where both have well defined requirements, implementation and functionality. These concepts are explored using a simple application in which a node in a network of processors is required to undertake some processing of a piece of data for which it does not have the required process. It is known that the required process is available somewhere in the network. The means by which the required process is accessed and utilized is described. As a final demonstration of the capability we show how a mobile meeting organizer could be built that allows friends in a social network to create meetings using their mobile devices given that they each have access to the others' on-line diaries." } @InProceedings{TateBate08, title = "{YASS}: a {S}calable {S}ensornet {S}imulator for {L}arge {S}cale {E}xperimentation", author= "Tate, Jonathan and Bate, Iain", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "411--430", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "Sensornets have been proposed consisting of thousands or tens of thousands of nodes. Economic and logistical considerations imply predeployment evaluation must take place through simulation rather than field trials. However, most current simulators are inadequate for networks with more than a few hundred nodes. In this paper we demonstrate some properties of sensornet application and protocols that only emerge when considered at scale, and cannot be effectively addressed by representative small-scale simulation. We propose a novel multi-phase approach to radio propagation modelling which substantially reduces computational overhead without significant loss in accuracy." } @InProceedings{Kosek08, title = "{M}odelling a {M}ulti-{C}ore {M}edia {P}rocessor {U}sing {JCSP}", author= "Kosek, Anna and Kerridge, Jon and Syed, Aly", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "431--443", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "Manufacturers are creating multi-core processors to solve specialized problems. This kind of processor can process tasks faster by running them in parallel. This paper explores the usability of the Communicating Sequential Processes model to create a simulation of a multi-core processor aimed at media processing in hand-held mobile devices. Every core in such systems can have different capabilities and can generate different amounts of heat depending on the task being performed. Heat generated reduces the performance of the core. We have used mobile processes in JCSP to implement the allocation of tasks to cores based upon the work the core has done previously." } @InProceedings{Brown08b, title = "{H}ow to {M}ake a {P}rocess {I}nvisible", author= "Brown, Neil C.C.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "445--445", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "Sometimes it is useful to be able to invisibly splice a process into a channel, allowing it to observe (log or present to a GUI) communications on the channel without breaking the synchronous communication semantics. occam-\π's extended rendezvous when reading from a channel made this possible; the invisible process could keep the writer waiting until the real reader had accepted the forwarded communication. This breaks down when it is possible to have choice on outputs (also known as output guards). An extended rendezvous for writing to a channel fixes this aspect but in turn does not support choice on the input. It becomes impossible to keep your process invisible in all circumstances. This talk explains the problem, and proposes a radical new feature that would solve it." } @InProceedings{vanderSteen08, title = "{D}esigning {A}nimation {F}acilities for g{CSP}", author= "van der Steen, Hans T.J. and Groothuis, Marcel A. and Broenink, Jan F.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "447--447", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "To improve feedback on how concurrent CSP-based programs run, the graphical CSP design tool (gCSP) has been extended with animation facilities. The state of processes, constructs, and channel ends are indicated with colours both in the gCSP diagrams and in the composition tree (hierarchical tree showing the structure of the total program). Furthermore, the contents of the channels are also shown. In this Fringe session, we will present and demonstrate this prototype animation facility, being the result of the MSc project of Hans van der Steen, and ask for feedback." } @InProceedings{SampsonBrown08, title = "{T}ock: {O}ne {Y}ear {O}n", author= "Sampson, Adam T. and Brown, Neil C.C.", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "449--449", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "Tock is a compiler for concurrent programming languages under development at the University of Kent. It translates occam-\π and Rain into portable, high-performance C or C++. It is implemented in Haskell using the nanopass approach, and aims to make it easy to experiment with new language and compiler features. Since our initial presentation of Tock at CPA 2007, we have added new frontends and backends, implemented a parallel usage checker based on the Omega test, improved the effectiveness of Tock's test suite, developed more efficient tree traversals using generic programming \– and more besides! In this fringe session, we will describe our recent work on Tock, discuss our plans for the project, and show how it can be of use to other process-oriented programming researchers." } @InProceedings{Chalmers08b, title = "{I}ntroducing {JCSP} {N}etworking 2.0", author= "Chalmers, Kevin", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "451--451", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "The original implementation of JCSP Networking is based on the T9000 model of virtual channels across a communications mechanism, and can be considered sufficiently adequate for applications which are not resource constrained or liable to connection failure. However, work undertaken has revealed a number of limitations due to excessive resource usage, lack of sufficient error handling, reliance on Java serialization, and reliance on now deprecated features of JCSP. These problems reflect badly when considering JCSP Networking in a broader sense beyond the normal desktop. In this talk, a brief overview on how these problems have been overcome is presented. This will be followed by some tutorial examples on how to use JCSP Networking 2.0. This should be familiar to current JCSP Networking users, but new additions to the library should make it easier for novices to get started. The new underlying protocol is also presented, which should enable interoperability between various platforms beyond the Java desktop environment. The new version of JCSP Networking is currently available from the JCSP Subversion repository, under the Networking-2 branch. Details are available at \textlesstt\textgreaterhttp://www.cs.kent.ac.uk/projects/ofa/jcsp/\textless/tt\textgreater." } @InProceedings{Bonnici08, title = "{M}obile {P}rocesses in an {A}nt {S}imulation", author= "Bonnici, Eric", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "453--453", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "The term self-organisation, or emergent behaviour, may be used to describe behaviour structures that emerge at the global level of a system due to the interactions between lower level components. Components of the system have no knowledge about global state; each component has only private internal data and data that it can observe from its immediate locality (such as environmental factors and the presence of other components). Resulting global phenomena are, therefore, an emergent property of the system as a whole. An implication of this when creating artificial systems is that we should not attempt to program such kinds of complex behaviour explicitly into the system. It may also help if the programmer approaches the design from a radically different perspective than that found in traditional methods of software engineering. This talk outlines a process-oriented approach, using massive fine-grained concurrency, and explores the use of occam-\π's mobile processes in the simulation of a classical ant colony." } @InProceedings{WelchPedersen08, title = "{S}anta {C}laus - with {M}obile {R}eindeer and {E}lves", author= "Welch, Peter H. and Pedersen, Jan Bækgaard", editor= "Welch, Peter H. and Stepney, S. and Polack, F.A.C and Barnes, Frederick R. M. and McEwan, Alistair A. and Stiles, G. S. and Broenink, Jan F. and Sampson, Adam T.", pages = "455--455", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2008", isbn= "978-1-58603-907-3", year= "2008", month= "sep", abstract= "Mobile processes, along with mobile channels, enable process networks to be dynamic: they may change their size (number of processes, channels, barriers) and shape (connection topology) as they run much like living organisms. One of the benefits is that all connections do not have to be established statically, in advance of when they are needed and open to abuse. In classical occam, care had to be taken by processes not to use channels when they were not in the right state to use them. With occam-\π mobiles, we can arrange that processes simply do not have those channels until they get into the right state \– and not having such channels means that their misuse cannot even be expressed! Of course, it is a natural consequence of mobile system design that the arrivals of channels (or barriers or processes) are the very events triggering their exploitation. In our explorations so far with occam-\π, we have taken advantage of the mobility of data, channels and barriers and seen very good results. Very little work has been done with mobile processes: the ability to send and receive processes through channels, plug them into local networks, fire them up, stand them down and move them on again. This talk illustrates mobile process design through a solution to Trono's classical \textlessi\textgreaterSanta Claus Problem\textless/i\textgreater. The reindeer and elves are modeled as mobile processes that move through holiday resorts, stables, work, waiting rooms, Santa's Grotto and back again. All those destinations are also processes \– though static ones. As the reindeer and elves arrive at each stage, they plug in and do business. We will show the occam-\π mechanisms supporting mobile processes, confess to one weakness and consider remedies. The occam-\π solution did, of course, run correctly the first time it passed the stringent safety checks of the compiler and is available as open source (\textlesstt\textgreaterhttp://www.santaclausproblem.net\textless/tt\textgreater)." } @InProceedings{Roebbers09, title = "{CPA} {S}urvival {G}uide", author= "Roebbers, Herman", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "For those new to CPA, this may be helpful to get an overview of what the various acronyms used during the conference mean and how they are related. This talk should provide you with a good start of the conference." } @InProceedings{Broadfoot09, title = "{A}n {O}verview of {ASD} - {F}ormal {M}ethods in {D}aily {U}se", author= "Broadfoot, Guy", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "Analytical Software Design (ASD) is an example of how formal methods can be introduced into the industrial workplace and routinely used on a daily basis. In this talk, I will give a quick overview of the underlying concepts and techniques employed." } @InProceedings{Sampson09, title = "occam on the {A}rduino", author= "Sampson, Adam T. and Jadud, Matthew C. and Jacobsen, Christian L.", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "The Arduino is an open-source \textquotedblphysical computing\textquotedbl development system with a large, active user community. Arduino applications are usually developed in a subset of C++ with no concurrency facilities, which makes it difficult to build systems that must respond to a variety of external stimuli. We present an implementation of occam for the Arduino based on the Transterpreter portable runtime, adapted to make efficient use of the small Harvard-architecture microcontrollers typically used on devices like the Arduino. In addition, we describe the library of processes -- \textquotedblPlumbing\textquotedbl -- that we provide to ease the development of physical computing applications." } @InProceedings{OguzBroenink09, title = "{U}se of {F}ormal {M}odels in {M}odel-driven {D}esign of {E}mbedded software", author= "Oguz, Oguzcan and Broenink, Jan F.", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", } @InProceedings{Welch09a, title = "{C}oncurrency {F}irst (but we'd better get it right!)", author= "Welch, Peter H.", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "This talk considers how and when concurrency should be taught in an undergraduate curriculum. It is to provoke discussion, which may later (if there is interest) become a theme for the Panel Session at the end of the conference (Wednesday morning). My presentation will focus on what we are doing at Kent (where concurrency has been taught as a full module for the past 23 years). Our belief is that concurrency is fundamental to most aspects of computer science (regardless of the push arising from the onset of multicore processors). It can and should be taught at the beginning at the same time as and a necessary and natural complement to sequential programming. But the concurrency model being taught better be right ... and threads-and-locks won't hack it!" } @InProceedings{SampsonBrown09, title = "{C}locks", author= "Sampson, Adam T. and Brown, Neil C.C.", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "As part of the CoSMoS project, we have implemented a variety of complex systems simulations using occam-pi. occam-pi is unusual in that it provides built-in support for synchronisation against a real-time clock, but simulations generally need to run faster or slower than real time. We describe the idea of a \textquotedblclock\textquotedbl -- a new synchronisation primitive for process-oriented programming, similar to a barrier but extended with a sense of time. Clocks can be used to provide simulated time in a complex systems simulation, and can also be used to implement efficient phase synchronisation for controlling access to shared resources." } @InProceedings{Brown09b, title = "{T}races for {T}esting", author= "Brown, Neil C.C.", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "CHP, the Haskell concurrency library, has recently been augmented with new testing capabilities. When a test case fails, its recorded event traces are automatically printed out -- with support for CSP, VCR and Structural trace styles." } @InProceedings{Mir09, title = "{A} {S}tudy {I}nto the {M}odelling and {A}nalysis of {R}eal-{T}ime {FPGA} {B}ased {S}ystems", author= "Mir, Irfan", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "High-integrity systems are those where failure can cause loss of life, injury, environmental damage or financial loss. The reliability of these systems is very important, so we need verification techniques that ensure the reliability and understanding of these systems. The aim of this research is to develop techniques and a tool for verifying real-time constraints in high level languages for FPGA based high-integrity systems. Further a novel methodology using Timed CSP is to be proposed to ensure the temporal correctness of these systems. The outcome of this research is to design the constraint meta-language and implement a tool which automates the analysis and verification process. Further this research will investigate the implementation of Timed CSP in Handel-C, augmented with the constraint meta-language." } @InProceedings{Slipper09, title = "{S}ystems {M}odelling and {I}ntegration", author= "Slipper, Dan", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "As systems increase in complexity and become combinations of hardware, software and physical components, the methods of integrating these become difficult. In safety critical systems, reliability is a key factor so we want faults to be predictable or mitigated wherever possible. This research aims to discover techniques of applying formal methods for software to a full system incorporating hardware and physical components, expecting to result in improvements in the way interfaces are defined, such that updates and maintenance in the system will not affect its reliability or performance. Another aim alongside this is to review the processes followed in industry throughout the design and development cycle, to find methods of keeping focus on meeting the requirements along all stages of the process." } @InProceedings{Cole09, title = "{H}ardware/{S}oftware {C}o-{D}esign {L}anguage {D}evelopment, {A}n {E}ng{D} {I}ntroduction", author= "Cole, Alex", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "A short introduction to a new Engineering Doctorate and planned areas of study. This presentation covers a bit of basic background, an overview of the whole research topic and lists a few proposed projects, looking in some minor detail at one specifically." } @InProceedings{YalcinBroenink09, title = "{R}obust {R}obot {S}oftware using {P}rocess {O}rientation", author= "Yalcin, Cagri and Broenink, Jan F.", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", } @InProceedings{Goldsmith09, title = "{B}eyond {M}obility - {W}hat {N}ext {A}fter {CSP}/pi?", author= "Goldsmith, Michael", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "1--6", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "Process algebras like CSP and CCS inspired the original occam model of communication and process encapsulation. Later the pi-calculus and various treatments handling mobility in CSP added support for mobility, as realised in practical programming systems such as occam-pi, JCSP, CHP and Sufrin's CSO, which allow a rather abstract notion of motion of processes and channel ends between parents or owners. Milner's Space and Motion of Communicating Agents on the other hand describes the bigraph framework, which makes location more of a first-class citizen of the calculus and evolves through reaction rules which rewrite both place and link graphs of matching sections of a system state, allowing more dramatic dynamic reconfigurations of a system than simple process spawning or migration. I consider the tractability of the notation, and to what extent the additional flexibility reflects or elicits desirable programming paradigms." } @InProceedings{Torshizi09, title = "{T}he {SCOOP} {C}oncurrency {M}odel in {J}ava-like {L}anguages", author= "Torshizi, Faraz and Ostroff, Jonathan S. and Paige, Richard F. and Chechik, Marsha", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "7--27", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "SCOOP is a minimal extension to the sequential object-oriented programming model for concurrency. The extension consists of one keyword (separate) that avoids explicit thread declarations, synchronized blocks, explicit waits, and eliminates data races and atomicity violations by construction, through a set of compiler rules. SCOOP was originally described for the Eiffel programming language. This paper makes two contributions. Firstly, it presents a design pattern for SCOOP, which makes it feasible to transfer SCOOP's concepts to different object-oriented programming languages. Secondly, it demonstrates the generality of the SCOOP model by presenting an implementation of the SCOOP design pattern for Java. Additionally, we describe tools that support the SCOOP design pattern, and give a concrete example of its use in Java." } @InProceedings{VanderMeulenPecheur09, title = "{C}ombining {P}artial {O}rder {R}eduction with {B}ounded {M}odel {C}hecking", author= "Vander Meulen, José and Pecheur, Charles", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "29--48", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "Model checking is an efficient technique for verifying properties on reactive systems. Partial-order reduction (POR) and symbolic model checking are two common approaches to deal with the state space explosion problem in model checking. Traditionally, symbolic model checking uses BDDs which can suffer from space blow-up. More recently bounded model checking (BMC) using SAT-based procedures has been used as a very successful alternative to BDDs. However, this approach gives poor results when it is applied to models with a lot of asynchronism. This paper presents an algorithm which combines partial order reduction methods and bounded model checking techniques in an original way that allows efficient verification of temporal logic properties (LTL\_X) on models featuring asynchronous processes. The encoding to a SAT problem strongly reduces the complexity and non-determinism of each transition step, allowing efficient analysis even with longer execution traces. The starting-point of our work is the Two-Phase algorithm (Namalesu and Gopalakrishnan) which performs partial-order reduction on process-based models. At first, we adapt this algorithm to the bounded model checking method. Then, we describe our approach formally and demonstrate its validity. Finally, we present a prototypal implementation and report encouraging experimental results on a small example." } @InProceedings{Murakami09, title = "{O}n {C}ongruence {P}roperty of {S}cope {E}quivalence for {C}oncurrent {P}rograms with {H}igher-{O}rder {C}ommunication", author= "Murakami, Masaki", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "49--66", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "Representation of scopes of names is important for analysis and verification of concurrent systems. However, it is difficult to represent the scopes of channel names precisely with models based on process algebra. We introduced a model of concurrent systems with higher-order communication based on graph rewriting in our previous work. A bipartite directed acyclic graph represents a concurrent system that consists of a number of processes and messages in that model. The model can represent the scopes of local names precisely. We defined an equivalence relation such that two systems are equivalent not only in their behavior but in extrusion of scopes of names. This paper shows that the equivalence relation is a congruence relation wrt tau-prefix, new-name, replication and composition even if higher-order communication is allowed. And we also show the equivalence relation is not congruent wrt input-prefix though it is congruent wrt input prefix in first-order case." } @InProceedings{Bezemer09, title = "{A}nalysing g{CSP} {M}odels {U}sing {R}untime and {M}odel {A}nalysis {A}lgorithms", author= "Bezemer, Maarten M. and Groothuis, Marcel A. and Broenink, Jan F.", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "67--88", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "This paper presents two algorithms for analysing gCSP models in order to improve their execution performance. Designers tend to create many small separate processes for each task, which results in many (resource intensive) context switches. The research challenge is to convert the model created from a design point of view to models which have better performance during execution, without limiting the designers in their ways of working. The first algorithm analyses the model during run-time execution in order to find static sequential execution traces that allow for optimisation. The second algorithm analyses the gCSP model for multi-core execution. It tries to find a resource-efficient placement on the available cores for the given target systems. Both algorithms are implemented in two tools and are tested. We conclude that both algorithms complement each other and the analysis results are suitable to create optimised models." } @InProceedings{BrownSmith09, title = "{R}elating and {V}isualising {CSP}, {VCR} and {S}tructural {T}races", author= "Brown, Neil C.C. and Smith, Marc L.", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "89--103", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "As well as being a useful tool for formal reasoning, a trace can provide insight into a concurrent program's behaviour, especially for the purposes of run-time analysis and debugging. Long-running programs tend to produce large traces which can be difficult to comprehend and visualise. We examine the relationship between three types of traces (CSP, VCR and Structural), establish an ordering and describe methods for conversion between the trace types. Structural traces preserve the structure of composition and reveal the repetition of individual processes, and are thus well-suited to visualisation. We introduce the Starving Philosophers to motivate the value of structural traces for reasoning about behaviour not easily predicted from a program's specification. A remaining challenge is to integrate structural traces into a more formal setting, such as the Unifying Theories of Programming -- however, structural traces do provide a useful framework for analysing large systems." } @InProceedings{Klomp09, title = "{D}esigning a {M}athematically {V}erified {I}2{C} {D}evice {D}river using {ASD}", author= "Klomp, Arjen and Roebbers, Herman and Derwig, Ruud and Bouwmeester, Leon", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "105--116", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "This paper describes the application of the Analytical Software Design methodology to the development of a mathematically verified I2C device driver for Linux. A model of an I2C controller from NXP is created, against which the driver component is modelled. From within the ASD tool the composition is checked for deadlock, livelock and other concurrency issues by generating CSP from the models and checking these models with the CSP model checker FDR. Subsequently C code is automatically generated which, when linked with a suitable Linux kernel run-time, provides a complete defect-free Linux device driver. The performance and footprint are comparable to handwritten code." } @InProceedings{Barnes09, title = "{M}obile {E}scape {A}nalysis for occam-pi", author= "Barnes, Frederick R. M.", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "117--134", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "Escape analysis is the process of discovering boundaries of dynamically allocated objects in programming languages. For object-oriented languages such as C++ and Java, this analysis leads to an understanding of which program objects interact directly, as well as what objects hold references to other objects. Such information can be used to help verify the correctness of an implementation with respect to its design, or provide information to a run-time system about which objects can be allocated on the stack (because they do not \textquotedblescape\textquotedbl the method in which they are declared). For existing object-oriented languages, this analysis is typically made difficult by aliasing endemic to the language, and is further complicated by inheritance and polymorphism. In contrast, the occam-pi programming language is a process-oriented language, with systems built from layered networks of communicating concurrent processes. The language has a strong relationship with the CSP process algebra, that can be used to reason formally about the correctness of occam-pi programs. This paper presents early work on a compositional escape analysis technique for mobiles in the occam-pi programming language, in a style not dissimilar to existing CSP analyses. The primary aim is to discover the boundaries of mobiles within the communication graph, and to determine whether or not they escape any particular process or network of processes. The technique is demonstrated by analysing some typical occam-pi processes and networks, giving a formal understanding of their mobile escape behaviour." } @InProceedings{TeigVannebo09, title = "{N}ew {ALT} for {A}pplication {T}imers and {S}ynchronisation {P}oint {S}cheduling", author= "Teig, Øyvind and Vannebo, Per Johan", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "135--144", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "During the design of a small channel-based concurrency runtime system (ChanSched, written in ANSI C), we saw that application timers (which we call egg and repeat timers) could be part of its supported ALT construct, even if their states live through several ALTs. There are no side effects into the ALT semantics, which enable waiting for channels, channel timeout and, now, the new application timers. Application timers are no longer busy polled for timeout by the process. We show how the classical occam language may benefit from a spin-off of this same idea. Secondly, we wanted application programmers to be freed from their earlier practice of explicitly coding communication states at channel synchronisation points, which was needed by a layered in-house scheduler. This led us to develop an alternative to the non-ANSI C \textquotedblcomputed goto\textquotedbl (found in gcc). Instead, we use a switch/case with goto line-number-tags in a synch-point-table for scheduling. We call this table, one for each process, a proctor table. The programmer does not need to manage this table, which is generated with a script, and hidden within an \#include file." } @InProceedings{Ritson09, title = "{T}ranslating {ETC} to {LLVM} {A}ssembly", author= "Ritson, Carl G.", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "145--158", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "The LLVM compiler infrastructure project provides a machine independent virtual instruction set, along with tools for its optimisation and compilation to a wide range of machine architectures. Compiler writers can use the LLVM's tools and instruction set to simplify the task of supporting multiple hardware/software platforms. In this paper we present an exploration of translation from stack-based Extended Transputer Code (ETC) to SSA-based LLVM assembly language. This work is intended to be a stepping stone towards direct compilation of occam-pi and similar languages to LLVM's instruction set." } @InProceedings{PedersenKauke09, title = "{R}esumable {J}ava {B}ytecode - {P}rocess {M}obility for {P}rocess{J} targeting the {JVM}", author= "Pedersen, Jan Bækgaard and Kauke, Brian", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "159--172", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "This paper describes an implementation of resumable and mobile processes for a new process-oriented language called ProcessJ. ProcessJ is based on CSP and the pi-calculus; it is structurally very close to occam-pi, but the syntax is much closer to the imperative part of Java (with new constructs added for process orientation). One of the targets of ProcessJ is Java bytecode to be executed on the Java Virtual Machine (JVM), and in this paper we describe how to implement the process mobility features of ProcessJ with respect to the Java Virtual Machine. We show how to add functionality to support resumability (and process mobility) by a combination of code rewriting (adding extra code to the generated Java target code), as well as bytecode rewriting." } @InProceedings{Sputh09, title = "{O}pen{C}om{RTOS}: {A} {R}untime {E}nvironment for {I}nteracting {E}ntities", author= "Sputh, Bernhard H.C. and Faust, Oliver and Verhulst, Eric and Mezhuyev, Vitaliy", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "173--184", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "OpenComRTOS is one of the few Real-Time Operating Systems for embedded systems that was developed using formal modelling techniques. The goal was to obtain a proven dependable component with a clean architecture that delivers high performance on a wide variety of networked embedded systems, ranging from a single processor to distributed systems. The result is a scalable relibable communication system with real-time capabilities. Besides, a rigorous formal verification of the kernel algorithms led to an architecture which has several properties that enhance safety and real-time properties of the RTOS. The code size in particular is very small, typically 10 times less than a typical equivalent single processor RTOS. The small code size allows a much better use of the on-chip memory resources, which increases the speed of execution due to the reduction of wait states caused by the use of external memory. To this point we ported OpenComRTOS to the MicroBlaze processor from Xilinx, the Leon3 from ESA, the ARM Cortex-M3, the Melexis MLX16, and the XMOS. In this paper we concentrate on the Microblaze port, which is an environment where OpenComRTOS competes with a number of different operating systems, including the standard operating system Xilinx Micro Kernel. This paper reports code size figures of the OpenComRTOS on a MicroBlaze target. We found that this code size is considerably smaller compared with published code sizes of other operating systems." } @InProceedings{Martin09, title = "{E}conomics of {C}loud {C}omputing: a {S}tatistical {G}enetics {C}ase {S}tudy", author= "Martin, Jeremy M. R. and Barrett, Steven J. and Thornber, Simon J. and Bacanu, Silviu-Alin and Dunlap, Dale and Weston, Steve", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "185--195", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "We describe an experiment which aims to reduce significantly the costs of running a particular large-scale grid-enabled application using commercial cloud computing resources. We incorporate three tactics into our experiment: improving the serial performance of each work unit, seeking the most cost-effective computation cycles, and making use of an optimized resource manager and scheduler. The application selected for this work is a genetics association analysis and is representative of a common class of embarrassingly parallel problems." } @InProceedings{Clayton09, title = "{A}n {A}pplication of {C}o{SM}o{S} {D}esign {M}ethods to {P}edestrian {S}imulation", author= "Clayton, Sarah and Urquhart, Neil and Kerridge, Jon", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "197--204", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "In this paper, we discuss the implementation of a simple pedestrian simulation that uses a multi agent based design pattern developed by the CoSMoS research group. Given the nature of Multi Agent Systems (MAS), parallel processing techniques are inevitably used in their implementation. Most of these approaches rely on conventional parallel programming techniques, such as threads, Message Passing Interface (MPI) and Remote Method Invocation (RMI). The CoSMoS design patterns are founded on the use of Communicating Sequential Processes (CSP), a parallel computing paradigm that emphasises a process oriented rather than object oriented programming perspective." } @InProceedings{ChalmersKerridge09, title = "{A}n {I}nvestigation into {D}istributed {C}hannel {M}obility {S}upport for {C}ommunicating {P}rocess {A}rchitectures", author= "Chalmers, Kevin and Kerridge, Jon", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "205--223", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "Localised mobile channel support is now a feature of Communicating Process Architecture (CPA) based frameworks, from JCSP and C++CSP to occam-pi. Distributed mobile channel support has also been attempted in JCSP Networking and occam-pi via the pony framework, although the capabilities of these two separate approaches is limited and has not led to the widespread usage of distributed mobile channel primitives. In this paper, an initial investigation into possible models that can support distributed channel mobility are presented and analysed for features such as transmission time, robustness and reachability. The goal of this work is to discover a set of models which can be used for channel mobility and also supported within the single unified protocol for distributed CPA frameworks. From the analysis presented in this paper, it has been determined that there are models which can be implemented to support channel end mobility within a single unified protocol which provide suitable capabilities for certain application scenarios." } @InProceedings{Brown09a, title = "{A}uto-{M}obiles: {O}ptimised {M}essage-{P}assing", author= "Brown, Neil C.C.", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "225--238", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "Some message-passing concurrent systems, such as occam 2, prohibit aliasing of data objects. Communicated data must thus be copied, which can be time-intensive for large data packets such as video frames. We introduce automatic mobility, a compiler optimisation that performs communications by reference and deduces when these communications can be performed without copying. We discuss bounds for speed-up and memory use, and benchmark the automatic mobility optimisation. We show that in the best case it can transform an operation from being linear with respect to packet size into constant-time." } @InProceedings{BialkiewiczPeschanski09, title = "{A} {D}enotational {S}tudy of {M}obility", author= "Bialkiewicz, Joël-Alexis and Peschanski, Frederic", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "239--261", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "This paper introduces a denotational model and refinement theory for a process algebra with mobile channels. Similarly to CSP, process behaviours are recorded as trace sets. To account for branching-time semantics, the traces are decorated by structured locations that are also used to encode the dynamics of channel mobility in a denotational way. We present an original notion of split-equivalence based on elementary trace transformations. It is first characterised coinductively using the notion of split-relation. Building on the principle of trace normalisation, a more denotational characterisation is also proposed. We then exhibit a preorder underlying this equivalence and motivate its use as a proper refinement operator. At the language level, we show refinement to be tightly related to a construct of delayed sums, a generalisation of non-deterministic choices." } @InProceedings{Vinter09, title = "{P}y{CSP} {R}evisited", author= "Vinter, Brian and Bjørndalen, John Markus and Friborg, Rune Møllegard", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "263--276", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "PyCSP was introduced two years ago and has since been used by a number of programmers, especially students. The original motivation behind PyCSP was a conviction that both Python and CSP are tools that are especially well suited for programmers and scientists in other fields than computer science. Working under this premise the original PyCSP was very similar to JCSP and the motivation was simply to provide CSP to the Python community in the JCSP tradition. After two years we have concluded that PyCSP is indeed a usable tool for the target users; however many of them have raised some of the same issues with PyCSP as with JCSP. The many channel types, lack of output guards and external choice wrapped in the select-then-execute mechanism were frequent complaints. In this work we revisit PyCSP and address the issues that have been raised. The result is a much simpler PyCSP with only one channel type, support for output guards, and external choice that is closer to that of occam than JCSP." } @InProceedings{Friborg09, title = "{T}hree {U}nique {I}mplementations of {P}rocesses for {P}y{CSP}", author= "Friborg, Rune Møllegard and Bjørndalen, John Markus and Vinter, Brian", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "277--292", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "In this work we motivate and describe three unique implementations of processes for PyCSP: process, thread and greenlet based. The overall purpose is to demonstrate the feasibility of Communicating Sequential Processes as a framework for different application types and target platforms. The result is a set of three implementations of PyCSP with identical interfaces to the point where a PyCSP developer need only change which implementation is imported to switch to any of the other implementations. The three implementations have different strengths; processes favors parallel processing, threading portability and greenlets favor many processes with frequent communication. The paper includes examples of applications in all three categories." } @InProceedings{Mount09, title = "{CSP} as a {D}omain-{S}pecific {L}anguage {E}mbedded in {P}ython and {J}ython", author= "Mount, Sarah and Hammoudeh, Mohammad and Wilson, Sam and Newman, Robert", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "293--309", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "Recently, much discussion has taken place within the Python programming community on how best to support concurrent programming. This paper describes a new Python library, python-csp, which implements synchronous, message-passing concurrency based on Hoare's Communicating Sequential Processes. Although other CSP libraries have been written for Python, python-csp has a number of novel features. The library is implemented both as an object hierarchy and as a domain-specific language, meaning that programmers can compose processes and guards using infix operators, similar to the original CSP syntax. The language design is intended to be idiomatic Python and is therefore quite different to other CSP libraries. python-csp targets the CPython interpreter and has variants which reify CSP process as Python threads and operating system processes. An equivalent library targets the Jython interpreter, where CSP processes are reified as Java threads. jython-csp also has Java wrappers which allow the library to be used from pure Java programs. We describe these aspects of python-csp, together with performance benchmarks and a formal analysis of channel synchronisation and choice, using the model checker SPIN." } @InProceedings{TristramBradshaw09, title = "{H}ydra: {A} {P}ython {F}ramework for {P}arallel {C}omputing", author= "Tristram, Waide B. and Bradshaw, Karen", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "311--324", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "This paper investigates the feasibility of developing a CSP to Python translator using a concurrent framework for Python. The objective of this translation framework, developed under the name of Hydra, is to produce a tool that helps programmers implement concurrent software easily using CSP algorithms. This objective was achieved using the ANTLR compiler generator tool, Python Remote Objects and PyCSP. The resulting Hydra prototype takes an algorithm defined in CSP, parses and converts it to Python and then executes the program using multiple instances of the Python interpreter. Testing has revealed that the Hydra prototype appears to function correctly, allowing simultaneous process execution. Therefore, it can be concluded that converting CSP to Python using a concurrent framework such as Hydra is both possible and adds flexibility to CSP with embedded Python statements." } @InProceedings{Lowe09, title = "{E}xtending {CSP} with {T}ests for {A}vailability", author= "Lowe, Gavin", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "325--347", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "We consider the language of CSP extended with a construct that allows processes to test whether a particular event is available (without actually performing the event). We present an operational semantics for this language, together with two congruent denotational semantic models. We also show how this extended language can be simulated using standard CSP, so as to be able to analyse systems using the model checker FDR." } @InProceedings{KorsgaardHendseth09, title = "{D}esign {P}atterns for {C}ommunicating {S}ystems with {D}eadline {P}ropagation", author= "Korsgaard, Martin and Hendseth, Sverre", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "349--361", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "Toc is an experimental programming language based on occam that combines CSP-based concurrency with integrated specification of timing requirements. In contrast to occam with strict round-robin scheduling, the Toc scheduler is lazy and does not run a process unless there is a deadline associated with its execution. Channels propagate deadlines to dependent tasks. These differences from occam necessitate a different approach to programming, where a new concern is to avoid dependencies and conflicts between timing requirements. This paper introduces client-server design patterns for Toc that allow the programmer precise control of timing. It is shown that if these patterns are used, the deadline propagation graph can be used to provide sufficient conditions for schedulability. An alternative definition of deadlock in deadline-driven systems is given, and it is demonstrated how the use of the suggested design patterns allow the absence of deadlock to be proven in Toc programs. The introduction of extended rendezvous into Toc is shown to be essential to these patterns." } @InProceedings{Kosek09, title = "{JCSP} {A}gents-{B}ased {S}ervice {D}iscovery for {P}ervasive {C}omputing", author= "Kosek, Anna and Kerridge, Jon and Syed, Aly and Armitage, Alistair", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "363--373", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "Device and service discovery is a very important topic when considering pervasive environments. The discovery mechanism is required to work in networks with dynamic topology and on limited software, and be able to accept different device descriptions. This paper presents a service and device discovery mechanism using JCSP agents and the JCSP network package jcsp.net2." } @InProceedings{SimpsonRitson09, title = "{T}oward {P}rocess {A}rchitectures for {B}ehavioural {R}obotics", author= "Simpson, Jonathan and Ritson, Carl G.", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "375--386", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "Building robot control programs which function as intended is a challenging task. Roboticists have developed architectures to provide principles, constraints and primitives which simplify the building of these correct, well structured systems. A number of established and prevalent behavioural architectures for robot control make use of explicit parallelism with message passing. Expressing these architectures in terms of a process-oriented programming language, such as occam-pi, allows us to distil design rules, structures and primitives for use in the development of process architectures for robot control." } @InProceedings{GroothuisBroenink09, title = "{HW}/{SW} {D}esign {S}pace {E}xploration on the {P}roduction {C}ell {S}etup", author= "Groothuis, Marcel A. and Broenink, Jan F.", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "387--402", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "This paper describes and compares five CSP based and two CSP related process-oriented motion control system implementations that are made for our Production Cell demonstration setup. Five implementations are software-based and two are FPGA hardware-based. All implementations were originally made with different purposes and investigating different areas of the design space for embedded control software resulting in an interesting comparison between approaches, tools and software and hardware implementations. Common for all implementations is the usage of a model-driven design method, a communicating process structure, the combination of discrete event and continuous time and that real-time behaviour is essential. This paper shows that many small decisions made during the design of all these embedded control software implementations influence our route through the design space for the same setup, resulting in seven different solutions with different key properties. None of the implementations is perfect, but they give us valuable information for future improvements of our design methods and tools." } @InProceedings{Welch09b, title = "{E}ngineering {E}mergence: an occam-pi {A}dventure", author= "Welch, Peter H. and Wallnau, Kurt and Klein, Mark", editor= "Welch, Peter H. and Roebbers, Herman and Broenink, Jan F. and Barnes, Frederick R. M. and Ritson, Carl G. and Sampson, Adam T. and Stiles, G. S. and Vinter, Brian", pages = "403--403", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2009", isbn= "978-1-60750-065-0", year= "2009", month= "nov", abstract= "Future systems will be too complex to design and implement explicitly. Instead, we will have to learn to engineer complex behaviours indirectly: through the discovery and application of local rules of behaviour, applied to simple process components, from which desired behaviours predictably emerge through dynamic interactions between massive numbers of instances. This talk considers such indirect engineering of emergence using a process-oriented architecture. Different varieties of behaviour may emerge within a single application, with interactions between them provoking ever-richer patterns ­ almost social systems. We will illustrate with a study based on Reynolds' boids: emergent behaviours include flocking (of course), directional migration (with waves), fear and panic (of hawks), orbiting (points of interest), feeding frenzy (when in a large enough flock), turbulent flow and maze solving. With this kind of engineering, a new problem shows up: the suppression of the emergence of undesired behaviours. The panic reaction within a flock to the sudden appearance of a hawk is a case in point. With our present rules, the flock loses cohesion and scatters too quickly, making individuals more vulnerable. What are the rules that will make the flock turn almost-as-one and maintain most of its cohesion? There are only the boids to which these rules may apply (there being, of course, no design or programming entity corresponding to a flock). More importantly, how do we set about finding such rules in the first place? Our architecture and models are written in occam-pi, whose processes are sufficiently lightweight to enable a sufficiently large mass to run and be interacted with for real-time experiments on emergent behaviour. This work is in collaboration with the Software Engineering Institute (at CMU) and is part of the CoSMoS project (at the Universities of Kent and York in the UK)." } @InProceedings{Sampson11a, title = "{T}his is a {P}arallel {P}arrot", author= "Sampson, Adam T.", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", } @InProceedings{Cook11, title = "{P}arallel {U}sage {C}hecking - an {O}bservation", author= "Cook, Barry M.", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "One of the great strengths of CSP based concurrent programming languages (such as occam) is the support provided to the programmer in avoiding the creation of erroneous programs. One such support \– \textlessi\textgreaterparallel usage checking\textless/i\textgreater \– detects program behaviours that may leave a variable in an unpredictable state. Current implementations of this check are safe but can lead to inefficient program implementations. In some cases, a simple program transformation can be used to demonstrate the safety of programs that would otherwise fail existing tests. By presenting a simple (but generic) example, I will show that using such a transformation allows the creation of more efficient programs." } @InProceedings{Vella11, title = "{E}xploring {P}eer-to-{P}eer {V}irtualized {M}ultithreaded {S}ervices", author= "Vella, Kevin", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", } @InProceedings{Ellis11, title = "{F}ormal {A}nalysis of {C}oncurrent {OS} ({RM}o{X}) {D}evice {D}rivers", author= "Ellis, Martin", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "Many tools exists for writing safe and correct device drivers for conventional operating systems, from runtime driver management layers (that try to detect errors and recover from them) to static analysis systems like SLAM. Unfortunately, these tools do not map well to the concurrent drivers we write for RMoX. This presentation will look at how we can build safe and correct device drivers, using traditional occam analysis approaches (such as CSP) and tools (such as FDR). Experiments in generating formal models of hardware/driver interfaces from our occam implementations will be described, along with how we intend to use these models to prove correctness properties for our drivers." } @InProceedings{Barnes11, title = "{G}uppy", author= "Barnes, Frederick R. M.", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", } @InProceedings{Sampson11b, title = "{D}istributing {C}oncurrent {S}imulation", author= "Sampson, Adam T.", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", } @InProceedings{Wilterdink11, title = "{D}emonstration of the {LUNA} {F}ramework", author= "Wilterdink, Robert J.W. and Bezemer, Maarten M. and Broenink, Jan F.", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "In this demonstration of the LUNA hard real-time, multi-threaded, CSP-capable execution framework, we use the JIWY-II pan-tilt camera robotic setup. The webcam can rotate horizontally and vertically, driven by two electromotors, controlled by software written as LUNA concurrent processes. The loop control algorithms are designed and generated by 20-sim, a tool for modeling and designing (controlled) mechatronic systems. This way, all code is generated, i.e. a model-driven approach. The demo will show that the LUNA library is capable of controlling setups in hard real-time, and that the implemented real-time logger provides valuable insight in the applications behaviour, i.e. control algorithms and LUNA framework." } @InProceedings{Lowe11, title = "{I}mplementing {G}eneralised {A}lt", author= "Lowe, Gavin", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "1--34", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "In this paper we describe the design and implementation of a generalised alt operator for the Communicating Scala Objects library. The alt operator provides a choice between communications on different channels. Our generalisation removes previous restrictions on the use of alts that prevented both ends of a channel from being used in an alt. The cost of the generalisation is a much more difficult implementation, but one that still gives very acceptable performance. In order to support the design, and greatly increase our confidence in its correctness, we build CSP models corresponding to our design, and use the FDR model checker to analyse them." } @InProceedings{FriborgVinter11, title = "{V}erification of a {D}ynamic {C}hannel {M}odel using the {SPIN} {M}odel-{C}hecker", author= "Friborg, Rune Møllegard and Vinter, Brian", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "35--54", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "This paper presents the central elements of a new dynamic channel leading towards a flexible CSP design suited for high-level languages. This channel is separated into three models: a shared-memory channel, a distributed channel and a dynamic synchronisation layer. The models are described such that they may function as a basis for implementing a CSP library, though many of the common features known in available CSP libraries have been excluded from the models. The SPIN model checker has been used to check for the presence of deadlocks, livelocks, starvation, race conditions and correct channel communication behaviour. The three models are separately verified for a variety of different process configurations. This verification is performed automatically by doing an exhaustive verification of all possible transitions using SPIN. The joint result of the models is a single dynamic channel type which supports both local and distributed any-to-any communication. This model has not been verified and the large state-space may make it unsuited for exhaustive verification using a model checker. An implementation of the dynamic channel will be able to change the internal synchronisation mechanisms on-the-fly, depending on the number of channel-ends connected or their location." } @InProceedings{Skovhede11, title = "{P}rogramming the {CELL}-{BE} using {CSP}", author= "Skovhede, Kenneth and Larsen, Morten N. and Vinter, Brian", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "55--70", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "The current trend in processor design seems to focus on using multiple cores, similar to a cluster-on-a-chip model. These processors are generally fast and power efficient, but due to their highly parallel nature, they are notoriously difficult to program for most scientists. One such processor is the CELL broadband engine (CELL-BE) which is known for its high performance, but also for a complex programming model which makes it difficult to exploit the architecture to its full potential. To address this difficulty, this paper proposes to change the programming model to use the principles of CSP design, thus making it simpler to program the CELL-BE and avoid livelocks, deadlocks and race conditions. The CSP model described here comprises a thread library for the synergistic processing elements (SPEs) and a simple channel based communication interface. To examine the scalability of the implementation, experiments are performed with both scientific computational cores and synthetic workloads. The implemented CSP model has a simple API and is shown to scale well for problems with significant computational requirements." } @InProceedings{PedersenSowders11, title = "{S}tatic {S}coping and {N}ame {R}esolution for {M}obile {P}rocesses with {P}olymorphic {I}nterfaces", author= "Pedersen, Jan Bækgaard and Sowders, Matthew", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "71--85", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "In this paper we consider a refinement of the concept of mobile processes in a process oriented language. More specifically, we investigate the possibility of allowing resumption of suspended mobile processes with different interfaces. This is a refinement of the approach taken currently in languages like occam-\π. The goal of this research is to implement varying resumption interfaces in ProcessJ, a process oriented language being developed at UNLV." } @InProceedings{Warren11, title = "{P}rioritised {C}hoice over {M}ultiway {S}ynchronisation", author= "Warren, Douglas N.", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "87--110", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "Previous algorithms for resolving choice over multiway synchronisations have been incompatible with the notion of priority. This paper discusses some of the problems resulting from this limitation and offers a subtle expansion of the definition of priority to make choice meaningful when multiway events are involved. Presented in this paper is a prototype extension to the JCSP library that enables prioritised choice over multiway synchronisations and which is compatible with existing JCSP Guards. Also discussed are some of the practical applications for this algorithm as well as its comparative performance." } @InProceedings{Cole11, title = "{A} {C}omparison {O}f {D}ata-{P}arallel {P}rogramming {S}ystems {W}ith {A}ccelerator", author= "Cole, Alex and McEwan, Alistair A. and Singh, Satnam", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "111--130", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "Data parallel programming provides an accessible model for exploiting the power of parallel computing elements without resorting to the explicit use of low level programming techniques based on locks, threads and monitors. The emergence of GPUs with hundreds or thousands of processing cores has made data parallel computing available to a wider class of programmers. GPUs can be used not only for accelerating the processing of computer graphics but also for general purpose data-parallel programming. Low level data-parallel programming languages based on the CUDA provide an approach for developing programs for GPUs but these languages require explicit creation and coordination of threads and careful data layout and movement. This has created a demand for higher level programming languages and libraries which raise the abstraction level of data-parallel programming and increase programmer productivity. The Accelerator system was developed by Microsoft for writing data parallel code in a high level manner which can execute on GPUs, multicore processors using SSE3 vector instructions and FPGA chips. This paper compares the performance and development effort of the high level Accelerator system against lower level systems which are more difficult to use but may yield better results. Specifically, we compare against the NVIDIA CUDA compiler and sequential C++ code considering both the level of abstraction in the implementation code and the execution models. We compare the performance of these systems using several case studies. For some classes of problems, Accelerator has a performance comparable to CUDA, but for others its performance is significantly reduced however in all cases it provides a model which is easier to use and allows for greater programmer productivity." } @InProceedings{Kerridge11, title = "{E}xperiments in {M}ulticore and {D}istributed {P}arallel {P}rocessing using {JCSP}", author= "Kerridge, Jon", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "131--142", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "It is currently very difficult to purchase any form of computer system be it, notebook, laptop, desktop server or high performance computing system that does not contain a multicore processor. Yet the designers of applications, in general, have very little experience and knowledge of how to exploit this capability. Recently, the Scottish Informatics and Computer Science Alliance (SICSA) issued a challenge to investigate the ability of developers to parallelise a simple Concordance algorithm. Ongoing work had also shown that the use of multicore processors for applications that have internal parallelism is not as straightforward as might be imagined. Two applications are considered: calculating pi using Monte Carlo methods and the SICSA Concordance application. The ease with which parallelism can be extracted from a single application using both single multicore processors and distributed networks of such multicore processors is investigated. It is shown that naive application of parallel programming techniques does not produce the desired results and that considerable care has to be taken if multicore systems are to result in improved performance. Meanwhile the use of distributed systems tends to produce more predictable and reasonable benefits resulting from parallelisation of applications." } @InProceedings{Kosek11, title = "{E}valuating {A}n {E}mergent {B}ehaviour {A}lgorithm for {E}nergy {C}onservation in {L}ighting {S}ystems {U}sing {JCSP}", author= "Kosek, Anna and Syed, Aly and Kerridge, Jon", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "143--156", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "Since the invention of the light bulb, artificial light is accompanying people all around the world every day and night. As the light bulb itself evolved a lot through years, light control systems are still switch-based and require users to make most of the decisions about its behaviour. This paper presents an algorithm for emergent behaviour in a lighting system to achieve stable, user defined light level, while saving energy. The algorithm employs a parallel design and was tested using JCSP." } @InProceedings{Bezemer11, title = "{LUNA}: {H}ard {R}eal-{T}ime, {M}ulti-{T}hreaded, {CSP}-{C}apable {E}xecution {F}ramework", author= "Bezemer, Maarten M. and Wilterdink, Robert J.W. and Broenink, Jan F.", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "157--175", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "Modern embedded systems have multiple cores available. The CTC++ library is not able to make use of these cores, so a new framework is required to control the robotic setups in our lab. This paper first looks into the available frameworks and compares them to the requirements for controlling the setups. It concludes that none of the available frameworks meet the requirements, so a new framework is developed, called LUNA. The LUNA architecture is component based, resulting in a modular structure. The core components take care of the platform related issues. For each supported platform, these components have a different implementation, effectively providing a platform abstraction layer. High-level components take care of platform-independent tasks, using the core components. Execution engine components implement the algorithms taking care of the execution flow, like a CSP implementation. The paper describes some interesting architectural challenges encountered during the LUNA development and their solutions. It concludes with a comparison between LUNA, C++CSP2 and CTC++. LUNA is shown to be more efficient than CTC++ and C++CSP2 with respect to switching between threads. Also, running a benchmark using CSP constructs, shows that LUNA is more efficient compared to the other two. Furthermore, LUNA is also capable of controlling actual robotic setups with good timing properties." } @InProceedings{Jacobsen11, title = "{C}oncurrent {E}vent-driven {P}rogramming in occam-\π for the {A}rduino", author= "Jacobsen, Christian L. and Jadud, Matthew C. and Kilic, Omer and Sampson, Adam T.", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "177--193", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "The success of the Arduino platform has made embedded programming widely accessible. The Arduino has seen many uses, for example in rapid prototyping, hobby projects, and in art installations. Arduino users are often not experienced embedded programmers however, and writing correct software for embedded devices can be challenging. This is especially true if the software needs to use interrupts in order to interface with attached devices. Insight and careful discipline are required to avoid introducing race hazards when using interrupt routines. Instead of programming the Arduino in C or C++ as is the custom, we propose using occam-\π as a language as that can help the user manage the concurrency introduced when using interrupts and help in the creation of modular, well-designed programs. This paper will introduce the Arduino, the software that enables us to run occam-\π on it, and a case study of an environmental sensor used in an Environmental Science course." } @InProceedings{HanlonHollis11, title = "{F}ast {D}istributed {P}rocess {C}reation with the {XMOS} {XS}1 {A}rchitecture", author= "Hanlon, James and Hollis, Simon J.", editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", pages = "195--207", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "The provision of mechanisms for processor allocation in current distributed parallel programming models is very limited. This makes difficult, or even prohibits, the expression of a large class of programs which require a run-time assessment of their required resources. This includes programs whose structure is irregular, composite or unbounded. Efficient allocation of processors requires a process creation mechanism able to initiate and terminate remote computations quickly. This paper presents the design, demonstration and analysis of an explicit mechanism to do this, implemented on the XMOS XS1 architecture, as a foundation for a more dynamic scheme. It shows that process creation can be made efficient so that it incurs only a fractional overhead of the total runtime and that it can be combined naturally with recursion to enable rapid distribution of computations over a system." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Whitehead11, title = "{S}erving {W}eb {C}ontent with {D}ynamic {P}rocess {N}etworks in {G}o", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Whitehead, James", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "209--226", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "This paper introduces webpipes, a compositional web server toolkit written using the Go programming language as part of an investigation of concurrent software architectures. This toolkit utilizes an architecture where multiple functional components respond to requests, rather than the traditional monolithic web server model. We provide a classification of web server components and a set of type definitions based on these insights that make it easier for programmers to create new purpose-built components for their systems. The abstractions provided by our toolkit allow servers to be deployed using several concurrency strategies. We examine the overhead of such a framework, and discuss possible enhancements that may help to reduce this overhead." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Chalmers11, title = "{P}erformance of the {D}istributed {CPA} {P}rotocol and {A}rchitecture on {T}raditional {N}etworks", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Chalmers, Kevin", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "227--242", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "Performance of communication mechanisms is very important in distributed systems frameworks, especially when the aim is to provide a particular type of behavior across a network. In this paper, performance measurements of the distributed Communicating Process Architectures networking protocol and stack is presented. The results presented show that for general communication, the distributed CPA architecture is close to the baseline network performance, although when dealing with parallel speedup for the Mandelbrot set, little performance is gained. A discussion into the future direction of the distributed CPA architecture and protocol in relation to occam-\π and other runtimes is also presented." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Ritson11, title = "{O}bject {S}tore {B}ased {S}imulation {I}nterworking", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Ritson, Carl G. and Andrews, Paul S. and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "243--253", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "The CoSMoS project is building generic modelling tools and simulation techniques for complex systems. As part of this project a number of simulations have been developed in many programming languages. This paper describes a framework for interconnecting simulation components written in different programming languages. These simulation components are synchronised and coupled using a shared object space. This approach allows us to combine highly concurrent agent-based simulations written in occam-\π, with visualisation and analysis components written in flexible scripting languages such as Python and domain specific languages such as MATLAB." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Huntbach11, title = "{A} {M}odel for {C}oncurrency {U}sing {S}ingle-{W}riter {S}ingle-{A}ssignment {V}ariables", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Huntbach, Matthew", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "255--272", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "This is a description of a model for concurrent computation based on single-writer single-assignment variables. The description is primarily graphical, resembling the interaction nets formalism. The model embodies rules in a process which may require two or more communications from other processes to respond. However, these are managed by a partial evaluation response on receiving a single communication." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{KorsgaardHendseth11, title = "{T}he {C}omputation {T}ime {P}rocess {M}odel", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Korsgaard, Martin and Hendseth, Sverre", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "273--286", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "In traditional real-time multiprocessor schedulability analysis it is required that all tasks are entirely serial. This implies that if a task is written in a parallel language such as occam, all parallelism in the task must be suppressed to enable schedulability analysis. Part of the reason for this restriction is the difficulty in analysing execution times of programs with a complex parallel structure. In this paper we introduce an abstract model for reasoning about the temporal properties of such programs. Within this model, we define what it means for a process to be easier to schedule than another, and the notion of upper bounds on execution times. Counterintuitive temporal behaviour is demonstrated to be inherent in all systems where processes are allowed an arbitrary parallel structure. For example, there exist processes that are guaranteed to complete on some schedule, that may not complete if executing less than the expected amount of computation. Not all processes exhibit such counterintuitive behaviour, and we identify a subset of processes that are well-behaved in this respect. The results from this paper is a necessary prerequisite for a complete schedulability analysis of systems with an arbitrary parallel structure." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{SaifhashemiBeerel11, title = "{S}ystem{V}erilog{CSP}: {M}odeling {D}igital {A}synchronous {C}ircuits {U}sing {S}ystem{V}erilog {I}nterfaces", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Saifhashemi, Arash and Beerel, Peter A.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "287--302", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "This paper describes how to model channel-based digital asynchronous circuits using SystemVerilog interfaces that implement CSP-like communication events. The interfaces enable explicit handshaking of channel wires as well as abstract CSP events. This enables abstract connections between modules that are described at different levels of abstraction facilitating both verification and design. We explain how to model one-to-one, one-to-many, one-to-any, any-to-one, and synchronized channels. Moreover, we describe how to split communication actions into multiple parts to more accurately model less concurrent handshaking protocols that are commonly found in many asynchronous pipelines." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Posso11, title = "{P}rocess-{O}riented {S}ubsumption {A}rchitectures in {S}warm {R}obotic {S}ystems", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Posso, Jeremy C. and Sampson, Adam T. and Simpson, Jonathan and Timmis, Jon", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "303--316", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "Previous work has demonstrated the feasibility of using process-oriented programming to implement simple subsumption architectures for robot control. However, the utility and scalability of process-based subsumption architectures for more complex tasks and those involving multiple robots has not been proven. We report our experience of applying these techniques to the implementation of a standard foraging problem in swarm robotics, using occam-\π to implement a subsumption control system. Through building a system with a realistic level of complexity, we have discovered both advantages and disadvantages to the process-oriented subsumption approach for larger robot control systems." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{SlipperMcEwan11, title = "{A} {S}ystems {R}e-engineering {C}ase {S}tudy: {P}rogramming {R}obots with occam and {H}andel-{C}", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Slipper, Dan and McEwan, Alistair A.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "317--327", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "This paper introduces a case study exploring some of the legacy issues that may be faced when redeveloping a system. The case study is a robotics system programmed in occam and Handel-C, allowing us to draw comparisons between software and hardware implementations in terms of program architecture, ease of program code verification, and differences in the behaviour of the robot. The two languages used have been selected because of their model of concurrency and their relation to CSP. The case study contributes evidence that re-implementing a system from an abstract model may present implementation specific issues despite maintaining the same underlying program control structure. The paper identifies these problems and suggests a number of steps that could be taken to help mitigate some of the issues." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Armstrong11, title = "{T}he {F}lying {G}ator: {T}owards {A}erial {R}obotics in occam-\π", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Armstrong, Ian and Pirrone-Brusse, Michael and Smith, A and Jadud, Matthew C.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "329--340", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "The Flying Gator is an unmanned aerial vehicle developed to support investigations regarding concurrent and parallel control for robotic and embedded systems. During ten weeks in the summer of 2010, we designed, built, and tested an airframe, control electronics, and a concurrent firmware capable of sustaining autonomous level flight. Ultimately, we hope to have a robust, open source control system capable of supporting interesting research questions exploring concurrency in real time systems as well as current issues in sustainable agriculture." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Isobe11, title = "{CONPASU}-tool: {A} {C}oncurrent {P}rocess {A}nalysis {S}upport {T}ool based on {S}ymbolic {C}omputation", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Isobe, Yoshinao", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "341--362", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "This paper presents an analysis-method of concurrent processes with value-passing which may cause infinite-state systems. The method consists of two steps: sequentialisation and state-reduction. In the sequentialisation, the symbolic transition graph of a given concurrent process is derived by symbolic operational semantics. In the state-reduction, the number of states in the symbolic transition graph is reduced by removing needless internal transitions. Furthermore, this paper introduces an analysis-tool called CONPASU, which implements the analysis-method, and demonstrates how CONPASU can be used for automatically analyzing concurrent processes. For example, it can extract abstract behaviors, which are useful for understanding complex behaviors, by focusing on some interesting events." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Yamakawa11, title = "{D}evelopment of an {ML} based {V}erification {T}ool for {T}imed {CSP} {P}rocesses", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Yamakawa, Takeshi and Ohashi, Tsuneki and Fukunaga, Chikara", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "363--375", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "We report the development of a verification tool for Timed CSP processes. The tool has been built on the functional programming language ML. The tool interprets processes described in both timed and untimed CSP, converting them to ML functions, and executing those functions for the verification of refinement in the timed traces and timewise traces models. Using the programmability of higher order functionality, the description of CSP processes with ML has been synthesised naturally. The effectiveness of the tool is demonstrated with an example analysing implementations of Fischer's algorithm for the exclusive control of a shared resource in a multi-processor environment." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{BonniciWelch11, title = "{M}obile {P}rocesses and {C}all {C}hannels with {V}ariant {I}nterfaces (a {D}uality)", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Bonnici, Eric and Welch, Peter H.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "377--377", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "The current model of mobile processes in occam-\π implements a \textlessem\textgreatersingle\textless/em\textgreater interface for host processes to use. However, different hosts holding different kinds of resource will naturally require different interfaces to interact with their visitors. So, current occam-\π mobiles have to offer a single union of all the interfaces needed and hosts must provide dummy arguments for those irrelevant to its particular calls. This opens the possibilty of programming errors in both hosts and mobile should those dummies mistakenly be used. This talk considers a revised model for mobile processes that allows \textlessem\textgreatermany\textless/em\textgreater interfaces. The talk also proposes a concept of \textlessem\textgreatervariant call channels\textless/em\textgreater, that expands on a mechanism proposed for the occam3 language, and shows a simple duality between the revised mobile processes and mobile variant call channels. An implementation of mobile variant call channels, via source-code transformation to standard occam-\π mobile channel bundles, has been devised \– which gives an implementation route for the revised mobile process model and an operational semantics. If time, the ideas will be illustrated with a case study based on the Santa Claus problem, where the elves and reindeer are mobile processes." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Welch11, title = "{A}dding {F}ormal {V}erification to occam-\π", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Welch, Peter H. and Pedersen, Jan Bækgaard and Barnes, Frederick R. M. and Ritson, Carl G. and Brown, Neil C.C.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Sampson, Adam T. and Pedersen, Jan Bækgaard and Kerridge, Jon and Broenink, Jan F. and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "379--379", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2011", isbn= "978-1-60750-773-4", year= "2011", month= "jun", abstract= "This is a proposal for the formal verification of occam-\π programs to be managed entirely within occam-\π. The language is extended with qualifiers on types and processes (to indicate relevance for verification and/or execution) and assertions about refinement (including deadlock, livelock and determinism). The compiler abstracts a set of CSPm equations and assertions, delegates their analysis to the FDR2 model checker and reports back in terms related to the occam-\π source. The rules for mapping the extended occam-\π to CSPm are given. The full range of CSPm assertions is accessible, with no knowledge of CSP formalism required by the occam-\π programmer. Programs are proved just by \textlessem\textgreaterwriting\textless/em\textgreater and \textlessem\textgreatercompiling\textless/em\textgreater programs. A case-study analysing a new (and elegant) solution to the \textlessem\textgreaterDining Philosophers\textless/em\textgreater problem is presented. Deadlock-freedom for colleges with \textlessem\textgreaterany\textless/em\textgreater number of philosphers is established by verifying an induction argument (the base and induction steps). Finally, following guidelines laid down by Roscoe, the careful use of \textlessem\textgreatermodel compression\textless/em\textgreater is demonstrated to verify directly the deadlock-freedom of an occam-\π college with 10\^{}2000 philosphers (in around 30 seconds). All we need is a universe large enough to contain the computer on which to run it." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Cole12b, title = "{H}andel-{C}++ - {A}dding {S}yntactic {S}upport to {C}++", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Cole, Alex", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Li12, title = "{I}mplementation of an {A}gent-based {M}odel with {TBB} {T}echnique", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Li, Ye", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Welch12b, title = "{U}nfinished {B}usiness - occam-pi²", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Welch, Peter H.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{BarrocasOliveira12b, title = "{JC}ircus {D}emo", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Barrocas, S.L.M. and Oliveira, Marcel", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Bezemer12b, title = "{D}eveloping {JIWY} using {TERRA}", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Bezemer, Maarten M. and Wilterdink, Robert J.W. and Broenink, Jan F.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Miller12, title = "{P}olyphonic {P}rocessors - {F}antasy on an {FPGA}", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Miller, Richard", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{East12, title = "{A} {CPA} {S}eries", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "East, Ian R.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Welch12a, title = "{C}ancellable {S}ervers - a {P}attern for {C}uriousity", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Welch, Peter H.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "--", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Whitehead12, title = "{D}esigning a {C}oncurrent {F}ile {S}erver", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Whitehead, James", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "1--14", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "In this paper we present a design and architecture for a concurrent file system server. This architecture is a compromise between the fully concurrent V6 UNIX implementation, and the simple sequential implementation in the MINIX operating system. The design of the server is made easier through the use of a disciplined model of concurrency, based on the CSP process algebra. By viewing the problem through this restricted lens, without traditional explicit locking mechanisms, we can construct the system as a process network of components with explicit connections and dependencies. This provides us with insight into the problem domain, and allows us to analyse the issues present in concurrent file system implementation." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{BarrocasOliveira12a, title = "{JC}ircus 2.0: an {E}xtension of an {A}utomatic {T}ranslator from {C}ircus to {J}ava", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Barrocas, S.L.M. and Oliveira, Marcel", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "15--36", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "The use of formal methods in the development of concurrent systems considerably reduces the complexity of specifying their behaviour and verifying properties that are inherent to them. Development, however, targets the generation of executable programs; hence, translating the final specification into a practical programming language becomes imperative. This translation is usually rather problematic due to the high probability of introducing errors in manual translations: the mapping from some of the original concepts in the formal concurrency model into a corresponding construct in the programming language is non-trivial. In recent years, there is a growing effort in providing automatic translation from formal specifications into programming languages. One of these efforts, JCircus, translates specifications written in Circus (a combination of Z and CSP) into Java programs that use JCSP, a library that implements most of the CSP constructs. The subtle differences between JCSP and Circus implementation of concurrency, however, imposed restrictions to the translation strategy and, consequently, to JCircus. In this paper, we extend JCircus by providing: (1) a new optimised translation strategy to multi-way synchronisation; (2) the translation of complex communications, and; (3) the translation of CSP sharing parallel and interleaving. A performance analysis of the resulting code is also in the context of this paper and provides important insights into the practical use of our results." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{KosekGehrke12, title = "{A} {D}istributed {M}ulti-{A}gent {C}ontrol {S}ystem for {P}ower {C}onsumption in {B}uildings", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Kosek, Anna and Gehrke, Oliver", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "37--52", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "This paper presents a distributed controller for adjusting the electrical consumption of a residential building in response to an external power setpoint in Watts. The controller is based on a multi-agent system and has been implemented in JCSP. It is modularly built, capable of self-configuration and adapting to a dynamic environment. The paper describes the overall architecture and the design of the individual agents. Preliminary results from proof-of-concept tests on a real building are included." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Wester12, title = "{S}pecification of {APERTIF} {P}olyphase {F}ilter {B}ank in {C}la{SH}", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Wester, Rinse and Sarakiotis, Dimitrios and Kooistra, Eric and Kuper, Jan", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "53--64", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "ClaSH, a functional hardware description language based on Haskell, has several abstraction mechanisms that allow a hardware designer to describe architectures in a short and concise way. In this paper we evaluate ClaSH on a complex DSP application, a Polyphase Filter Bank as it is used in the ASTRON APERTIF project. The Polyphase Filter Bank is implemented in two steps: first in Haskell as being close to a standard mathematical specification, then in ClaSH which is derived from the Haskell formulation by applying only minor changes. We show that the ClaSH formulation can be directly mapped to hardware, thus exploiting the parallelism and concurrency that is present in the original mathematical specification." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Oguz12, title = "{S}chedulability {A}nalysis of {T}imed {CSP} {M}odels {U}sing the {PAT} {M}odel {C}hecker", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Oguz, Oguzcan and Broenink, Jan F. and Mader, Angelika", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "65--88", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "Timed CSP can be used to model and analyse real-time and concurrent behaviour of embedded control systems. Practical CSP implementations combine the CSP model of a real-time control system with prioritized scheduling to achieve efficient and orderly use of limited resources. Schedulability analysis of a timed CSP model of a system with respect to a scheduling scheme and a particular execution platform is important to ensure that the system design satisfies its timing requirements. In this paper, we propose a framework to analyse schedulability of CSP-based designs for non-preemptive fixed-priority multiprocessor scheduling. The framework is based on the PAT model checker and the analysis is done with dense-time model checking on timed CSP models. We also provide a schedulability analysis workflow to construct and analyse, using the proposed framework, a timed CSP model with scheduling from an initial untimed CSP model without scheduling. We demonstrate our schedulability analysis workflow on a case study of control software design for a mobile robot. The proposed approach provides non-pessimistic schedulability results." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{GardnerSolovyov12, title = "{S}upporting {T}imed {CSP} {O}perators in {CSP}++", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Gardner, W. B. and Solovyov, Yuriy", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "89--106", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "CSP++ is an open-source code synthesis tool consisting of a translator for a subset of CSPm and a C++ run-time framework. Version 5.0 now supports Timed CSP operators--timed interrupt, timed timeout, and timed prefix--as well as untimed variants of interrupt and timeout, with only 1\% additional execution and memory overhead, though using interrupts is more costly. We describe the implementation and performance of the new operators, illustrating their use with a robot-vacuum cleaner case study. The tool thus becomes more useful for specifying the behaviour of soft real-time systems, and generating a timing-enabled executable program from its formal model." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Chalmers12, title = "{A} {C}omparison of {M}essage {P}assing {I}nterface and {C}ommunicating {P}rocess {A}rchitecture {N}etworking {C}ommunication {P}erformance", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Chalmers, Kevin", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "107--120", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "Message Passing Interface (MPI) is a popular approach to enable Single Process, Multiple Data (SPMD) style parallel computing, particularly in cluster computing environments. Communicating Process Architecture (CPA) Networking on the other hand, has been developed to enable channel based semantics across a communication mechanism in a transparent manner. However, in both cases the concept of a message passing infrastructure is fundamental. This paper compares the performance of both of these frameworks at a base communication level, also discussing some of the similarities between the two mechanisms. From the experiments, it can be seen that although MPI is a more mature technology, in many regards CPA Networking can perform comparably if the correct communication is used." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Cole12a, title = "{B}eauty {A}nd {T}he {B}east: {E}xploiting {GPU}s {I}n {H}askell", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Cole, Alex and McEwan, Alistair A. and Mainland, Geoff", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "121--134", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "In this paper we compare a Haskell system that exploits a GPU back end using Obsidian against a number of other GPU/parallel processing systems. Our examples demonstrate two major results. Firstly they show that the Haskell system allows the applications programmer to exploit GPUs in a manner that eases the development of parallel code by abstracting from the hardware. Secondly we show that the performance results from generating the GPU code from Haskell are acceptably comparable to expert hand written GPU code in most cases; and permit very significant performance benefits over single and multi-threaded implementations whilst maintaining ease of development. Where our results differ from expert hand written GPU (CUDA) code we consider the reasons for this and discuss possible developments that may mitigate these differences. We conclude with a discussion of a domain specific example that benefits directly and significantly from these results." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{BateLowe12, title = "{A} {D}ebugger for {C}ommunicating {S}cala {O}bjects", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Bate, Andrew and Lowe, Gavin", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "135--154", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "This paper presents a software tool for visualising and reasoning about the behaviour of message-passing concurrent programs built with the CSO library for the Scala programming language. It describes the models needed to represent the construction of process networks and the runtime behaviour of the resulting program. We detail the manner in which information is extracted from the use of concurrency primitives in order to maintain these models and how these models are diagrammed. Our implementation of dynamic deadlock detection is explained. The tool can produce a sequence diagram of process communications, the communication network depicting the pairs of processes which share a communication channel, and the trees resulting from the composition of processes. Furthermore, it allows for behavioural specifications to be defined and then checked at runtime, and guarantees to detect the illegal usage of concurrency primitives that could otherwise lead to deadlock or data loss. Our implementation imposes only a small overhead on the program under inspection." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Teig12, title = "{XCHAN}s: {N}otes on a {N}ew {C}hannel {T}ype", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Teig, Øyvind", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "155--170", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "This paper proposes a new channel type, XCHAN, for communicating messages between a sender and receiver. Sending on an XCHAN is asynchronous, with the sending process informed as to its success. XCHANs may be buffered, in which case a successful send means the message has got into the buffer. A successful send to an unbuffered XCHAN means the receiving process has the message. In either case, a failed send means the message has been discarded. If sending on an XCHAN fails, a built-in feedback channel (the x-channel, which has conventional channel semantics) will signal to the sender when the channel is ready for input (i.e., the next send will succeed). This x-channel may be used in a select or ALT by the sender side (only input guards are needed), so that the sender may passively wait for this notification whilst servicing other events. When the x-channel signal is taken, the sender should send as soon as possible -- but it is free to send something other than the message originally attempted (e.g. some freshly arrived data). The paper compares the use of XCHAN with the use of output guards in select/ALT statements. XCHAN usage should follow a design pattern, which is also described. Since the XCHAN never blocks, its use contributes towards deadlock- avoidance. The XCHAN offers one solution to the problem of overflow handling associated with a fast producer and slow consumer in message passing systems. The claim is that availability of XCHANs for channel based systems gives the designer and programmer another means to simplify and increase quality." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Mir12, title = "{A} {H}igh {P}erformance {R}econfigurable {A}rchitecture for {F}lash {F}ile {S}ystems", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Mir, Irfan and McEwan, Alistair A. and Perrins, Neil J.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "171--184", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "NAND flash memory is widely adopted as the primary storage medium in embedded systems. The design of the flash translation layer, and exploitation of parallel I/O architectures, are crucial in achieving high performance within a flash file system. In this paper we present our new FPGA based flash management framework using reconfigurable computing that supports high performance flash storage systems. Our implementation is in Verilog, and as such enables us to design a highly concurrent system at a hardware level in both the flash translation layer and the flash controller. Results demonstrate that implementing the flash translation layer and flash controller directly in hardware, by exploiting reconfigurable computing, permits us to exploit a highly concurrent architecture that leads to fast response times and throughput in terms of read/write operations." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Bezemer12a, title = "{D}esign and {U}se of {CSP} {M}eta-{M}odel for {E}mbedded {C}ontrol {S}oftware {D}evelopment", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Bezemer, Maarten M. and Wilterdink, Robert J.W. and Broenink, Jan F.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "185--200", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "Software that is used to control machines and robots must be predictable and reliable. Model-Driven Design (MDD) techniques are used to comply with both the technical and business needs. This paper introduces a CSP meta-model that is suitable for these MDD techniques. The meta-model describes the structure of CSP models that are designed; using this meta-model it is possible to use all regular CSP constructs when constructing a CSP model. The paper also presents a new tool suite, called TERRA, based on Eclipse and its frameworks. TERRA contains a graphical CSP model editor (using the new CSP meta-model), model validation tools and code generation tools. The model validation tools check whether the model conforms to the meta-model definition as well as to additional rules. Models without any validation problems result in proper code generation, otherwise the developer needs to address the found problems to be sure code generation will succeed. The code generation tools are able to generate CSPm code that is readable by FDR and to generate C++/LUNA code that is executable on embedded targets. The meta-model and the TERRA tool suite are tested by designing CSP models for several of our laboratory setups. The generated C++/LUNA code for the laboratory setups is able to control them as expected. Additionally, the paper contains an example model containing all supported CSP constructs to show the CSPm code generation results. So it can be concluded that the meta-model and TERRA are usable for these kind of tasks." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{LarsenVinter12, title = "{E}xception {H}andling and {C}heckpointing in {CSP}", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Larsen, Mads Ohm and Vinter, Brian", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "201--212", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "This paper describes work in progress. It presents a new way of looking at some of the basics of CSP. The primary contributions is exception handling and checkpointing of processes and the ability to roll back to a known checkpoint. Channels are discussed as communication events which is monitored by a supervisor process. The supervisor process is also used to formalise poison and retire events. Exception handling and checkpointing are used as means of recovering from an catastrophe. The supervisor process is central to checkpointing and recovery as well. Three different kind of exception handling is discussed: fail-stop, retire-like fail-stop, and check pointing. Fail-stop works like poison, and retire-like fail-stop works like retire. Checkpointing works by telling the supervisor process to roll back both participants in a communication event, to a state immediately after their last successful communication. Only fail-stop exceptions have been implemented in PyCSP to this point." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Welch12c, title = "occam {O}bviously", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Welch, Peter H.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "213--214", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "This talk explains and tries to justify a range of questions for which its title is the answer. It reviews the history of occam: its underlying philosophy (Occam's Razor), its semantic foundation on Hoare's CSP, its principles of process oriented design and its development over almost three decades into occam-pi (which blends in the concurrency dynamics of Milner's pi-calculus). Also presented will be its urgent need for rationalisation -- occam-pi is an experiment that has demonstrated significant results, but now needs time to be spent on careful review and implementing the conclusions of that review. Finally, the future is considered. In particular, how do we avoid the following question being final: which language had the most theoretically sound semantics, the most efficiently engineered implementation, the simplest and most pragmatic concurrency model for building complex systems ... and was mostly forgotten (even as its ideas are slowly and expensively and painfully being reinvented piece-by-piece, as they must be)?" } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Sampson12, title = "{P}rocess-{O}riented {B}uilding {B}locks", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "215--216", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "Intel's Threading Building Blocks library provides an efficient, work-stealing lightweight task scheduler, along with a high-level task-based API for parallel programming in C++. This presentation shows how TBB's scheduler can be used (without modification) to implement blocking process-oriented concurrent systems, and discusses the advantages and disadvantages of this approach." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{EllisBarnes12, title = "{D}ata {E}scape {A}nalysis for {P}rocess {O}riented {S}ystems", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Ellis, Martin and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "217--218", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "Escape analysis, the technique of discovering the boundaries of dynamically allocated objects, is a well explored technique for object-orientated languages (such as Java and C++) and stems from the functional programming community. It provides an insight into which objects interact directly (and indirectly) and can inform program correctness checking, or be used for directing optimisations (e.g. determining which objects can safely be allocated on a function-local stack). For process-oriented languages such as occam-pi and Google's Go, we have explored mobile escape analysis, that provides concise information about the movement of objects (mobiles) within networks of communicating processes. Because of the distinction between processes (as execution contexts) and objects (dynamically allocated data, channels and processes), combined with strict typing and aliasing rules, the analysis is somewhat simpler then for less strict languages. This analysis is only concerned with dynamically allocated blocks of memory -- it does not give any consideration for the data contained within these. However, knowing the extent to which data (statically or dynamically allocated) escapes within a network of communicating processes is arguably useful -- and is not necessarily a superset of mobile escape. The fringe presentation describes an extension to the mobile escape model that seeks to capture semantic information about the data escape of a process-oriented system. This provides richer semantic information about a process's behaviour (that can be used in verification) and has clear application to security (e.g. by demonstrating that particular data does not escape a set of communicating processes)." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{PerrinsMcEwan12, title = "{SEU} {P}rotection for {H}igh-{R}eliability {F}lash {F}ile {S}ystems", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Perrins, Neil J. and McEwan, Alistair A.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "219--220", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012", isbn= "978-0-9565409-5-9", year= "2012", month= "aug", abstract= "Single Event Upsets (SEU) are a primary reliability concern for electronics in high radiation, highly hostile environments such as space. In the case of Field Programmable Gate Arrays, the concern is firstly that data stored in RAM can be corrupted, and secondly that configurable logic blocks can become damaged or corrupted. In this talk we will present our considerations of this problem in the context of an SRAM-based high reliability flash file system. We will firstly demonstrate our test harness where we simulate the injection of SEUs into our FPGA. We will then discuss how we propose to build a self repairing configuration using triple modular redundancy and partial dynamic reconfiguration. Finally we will discuss how the reliability of the system may be tested and measured such that it can be used with confidence in either data acquisition or control system applications in rad-hard environments." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Michaelson13, title = "{C}osting by {C}onstruction", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Michaelson, Greg", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "1--2", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "Predicting the performance of sequential systems is hard and concurrency brings additional complexities of coordination and timing. However, current models of concurrency tend to be unitary and so conflate computation and coordination. In contrast, the Hume language is based on concurrent generalised finite state boxes linked by wires. Boxes are stateless with transitions driven by pattern matching to select actions in a full strength functional language. This explicit separation of coordination and computation greatly eases concurrent system modelling: classical inductive reasoning may be used to establish properties within boxes, while box coordination may be explored independently through the novel box calculus. This seminar gives an introduction to the Hume language, cost models for Hume, and the box calculus, and considers how they might be integrated in a system to support costing by construction, where the resource implications of design decisions are made manifest as a system evolves." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Turner13, title = "{N}ational {HPC} {F}acilities at {EPCC}: {E}xploiting {M}assively {P}arallel {A}rchitectures for {S}cientific {S}imulation", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Turner, Andrew", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "3--4", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "This presentation gives an overview of the challenges facing scientific software developers in exploiting current and upcoming massively parallel HPC facilities. The different levels of parallelism available in the architectures will be discussed, together with their impact for software design and what the trend is for the future. The discussion will be illustrated with examples from the two national facilities currently hosted at EPCC: HECToR (a Cray XE6) and the DiRAC IBM BlueGene/Q." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{GibsonRobinsonGoldsmith13, title = "{T}he {M}eaning and {I}mplementation of {SKIP} in {CSP}", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Gibson-Robinson, Thomas and Goldsmith, Michael", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "5--20", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "The CSP model checker FDR has long supported Hoare's termination semantics for CSP, but has not supported the more theoretically complete construction of Roscoe's, largely due to the complexity of adding a second termination semantics. In this paper we provide a method of simulating Roscoe's termination semantics using the Hoare termination semantics and then prove the equivalence of the two different approaches. We also ensure that FDR can support the simulation reasonably efficiently." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{HowellsdInverno13a, title = "{S}uccessful {T}ermination in {T}imed {CSP}", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Howells, Paul and d'Inverno, Mark", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "21--38", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "In previous work the authors investigated the inconsistencies of how successful termination was modelled in Hoare, Brookes and Roscoe's original CSP. This led to the definition of a variant of CSP, called CSPt. CSPt presents a solution to these problems by means of adding a termination axiom to the original process axioms. In this paper we investigate how successful process termination is modelled in Reed and Roscoe's Timed CSP, which is the temporal version of Hoare's original untimed CSP. We discuss the issues that need to be considered when selecting termination axioms for Timed CSP, based on our experiences in defining CSPt. The outcome of this investigation and discussion is a collection of candidate successful termination axioms that could be added to the existing Timed CSP models, leading to an improved treatment of successful termination within the Timed CSP framework. We outline how these termination axioms would be added to the family of semantic models for Timed CSP. Finally, we outline what further work needs to be done once these new models for Timed CSP have been defined. For example, it would then be possible to define timed versions of the new more flexible parallel operators introduced in CSPt." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{ChalmersKerridge13, title = "{V}erifying the {CPA} {N}etworking {S}tack using {SPIN}/{P}romela", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Chalmers, Kevin and Kerridge, Jon", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "39--52", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "This paper presents a verification of the CPA Networking Stack, using the SPIN Model Checker. Our work shows that the system developed for general networking within CPA applications works under the conditions defined for it. The model itself focuses on ensuring deadlock freedom, and work still needs to be undertaken to verify expected behaviour of the architecture." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Boode13, title = "{I}mproving the {P}erformance of {P}eriodic {R}eal-time {P}rocesses: a {G}raph {T}heoretical {A}pproach", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Boode, Antoon H. and Broersma, Hajo and Broenink, Jan F.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "57--80", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "In this paper the performance gain obtained by combining parallel periodic real-time processes is elaborated. In certain single-core mono-processor configurations, for example embedded control systems in robotics comprising many short processes, process context switches may consume a considerable amount of the available processing power. For this reason it can be advantageous to combine processes, to reduce the number of context switches and thereby increase the performance of the application. As we consider robotic applications only, often consisting of processes with identical periods, release times and deadlines, we restrict these configurations to periodic real-time processes executing on a single-core mono-processor. By graph theoretical concepts and means, we provide necessary and sufficient conditions so that the number of context switches can be reduced by combining synchronising processes." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Friborg13, title = "{S}caling {P}y{CSP}", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Friborg, Rune Møllegard and Bjørndalen, John Markus and Vinter, Brian", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "81--92", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "PyCSP is intended to help scientists develop correct, maintainable and portable code for emerging architectures. The library uses concepts from Communicating Sequential Processes, CSP, and is implemented in the Python programming language. This paper introduces a new channel implementation and new process types for PyCSP that are intended to simplify writing programs for clusters. The new processes and channels are investigated by running 3 benchmarks on two separate clusters, using up to 512 CPU cores. The results show that PyCSP scales well, with close to linear scaling for some of the benchmarks." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Alam13, title = "{S}ervice {O}riented {P}rogramming in {MPI}", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Alam, Sarwar and Kamal, Humaira and Wagner, Alan", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "93--112", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "In this paper we introduce a service oriented approach to the design of distributed data structures for MPI. Using this approach we present the design of an ordered linked-list structure. The implementation relies on Fine-Grain MPI (FG-MPI) and its support for exposing fine-grain concurrency. We describe the implementation of the service and show how to compose and map it onto a cluster. We experiment with the service to show how its behaviour can be adjusted to match the application and the machine." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Bate13, title = "{S}calable {P}erformance for {S}cala {M}essage-{P}assing {C}oncurrency", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Bate, Andrew", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "113--132", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "This paper presents an embedded domain-specific language for building massively concurrent systems. In particular, we demonstrate how ultra-lightweight cooperatively-scheduled processes and message-passing concurrency can be provided for the Scala programming language on the Java Virtual Machine (JVM). We make use of a well-known continuation-passing style bytecode transformation in order to achieve performance that is several orders of magnitude higher than native JVM threads. Our library is capable of scaling to millions of processes and messages on a single virtual machine instance, and our runtime system will detect deadlock should it occur. Message-passing is over 100 times faster than Erlang, and context switching is 1000 times faster than native Java threads. In benchmarks, the performance of our library is close to compiled code." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{PedersenSmith13, title = "{P}rocess{J}: {A} {P}ossible {F}uture of {P}rocess-{O}riented {D}esign", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Pedersen, Jan Bækgaard and Smith, Marc L.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "133--156", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "We propose ProcessJ as a new, more contemporary programming language that supports process-oriented design, which raises the level of abstraction and lowers the barrier of entry for parallel and concurrent programming. ProcessJ promises verifiability (e.g., deadlock detection), based on Hoare's CSP model of concurrency, and existing model checkers like FDR. Process-oriented means processes compose, unlike thread-based or asynchronous message-passing models of concurrency; this means that programmers can incrementally define larger and larger concurrent processes without concern for undesirable nondeterminism or unexpected side effects. Processes at their lowest, most granular level are sequential programs; there are no global variables, so no race conditions, and the rules of parallel composition are functional in nature, not imperative, and based on the mathematically sound CSP process algebra. Collectively, these ideas raise the level of abstraction for concurrency; they were successful once before with the occam language and the Transputer. We believe their time has come again, and will not go away, in this new age of multi-core processors. Computers have finally caught up with CSP and process-oriented design. We believe that ProcessJ can be the programming language that provides a bridge from today's languages to tomorrow's concurrent programs. Learning or teaching the programming model and language will be greatly supported through the educational part of the proposed project, which includes course templates and an online teaching tool that integrates in-browser programming with teaching material. Our efforts are encouraged by the forthcoming 2013 IEEE and ACM curricula guidelines, which for the first time include concurrent programming as a core knowledge area at the undergraduate level." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{HowellsdInverno13b, title = "{S}pecifying and {A}nalysing {N}etworks of {P}rocesses in {CSP}t (or {I}n {S}earch of {A}ssociativity)", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Howells, Paul and d'Inverno, Mark", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "157--184", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "In proposing theories of how we should design and specify networks of processes it is necessary to show that the semantics of any language we use to write down the intended behaviours of a system has several qualities. First in that the meaning of what is written on the page reflects the intention of the designer; second that there are no unexpected behaviours that might arise in a specified system that are hidden from the unsuspecting specifier; and third that the intention for the design of the behaviour of a network of processes can be communicated clearly and intuitively to others. In order to achieve this we have developed a variant of CSP, called CSPt, designed to solve the problems of termination of parallel processes present in the original formulation of CSP. In CSPt we introduced three parallel operators, each with a different kind of termination semantics, which we call synchronous, asynchronous and race. These operators provide specifiers with an expressive and flexible tool kit to define the intended behaviour of a system in such a way that unexpected or unwanted behaviours are guaranteed not to take place. In this paper we extend out analysis of CSPt and introduce the notion of an alphabet diagram that illustrates the different categories of events that can arise in the parallel composition of processes. These alphabet diagrams are then used to analyse networks of three processes in parallel with the aim of identifying sufficient constraints to ensure associativity of their parallel composition. Having achieved this we then proceed to prove associativity laws for the three parallel operators of CSPt. Next, we illustrate how to design and construct a network of three processes that satisfy the associativity law, using the associativity theorem and alphabet diagrams. Finally, we outline how this could be achieved for more general networks of processes." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{GibsonRobinson13a, title = "{E}fficient {S}imulation of {CSP}-{L}ike {L}anguages", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Gibson-Robinson, Thomas", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "185--204", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "In \textquotedblOn the Expressiveness of CSP\textquotedbl, Roscoe provides a construction that, given the operational semantics rules of a CSP-like language and a process in that language, constructs a strongly bisimilar CSP process. Unfortunately, the construction provided is difficult to use and the scripts produced cannot be compiled by the CSP model-checker, FDR. In this paper, we adapt Roscoe's simulation to make it produce a process that can be checked relatively efficiently by FDR. Further, we extend Roscoe's simulation in order to allow recursively defined processes to be simulated in FDR, which was not supported by the original simulation. We also describe the construction of a tool that can automatically construct the simulation, given the operational semantics of the language and a script to simulate, both in an easy-to-use format." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Teig13a, title = "{S}elective {C}hoice \textquotedbl{F}eathering\textquotedbl with {XCHAN}s", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Teig, Øyvind", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "205--216", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "This paper suggests an additional semantics to XCHANs, where a sender to a synchronous channel that ends up as a component in a receiver's selective choice (like ALT) may (if wanted) become signaled whenever the ALT has been (or is being) set up with the actual channel not in the active channel set. Information about this is either received as the standard return on XCHAN's attempted sending or on the built-in feedback channel (called x-channel) if initial sending failed. This semantics may be used to avoid having to send (and receive) messages that have been seen as uninteresting. We call this scheme feathering, a kind of low level implicit subscriber mechanism. The mechanism may be useful for systems where channels that were not listened to while listening on some other set of channels, will not cause a later including of those channels to carry already declared uninteresting messages. It is like not having to treat earlier bus-stop arrival messages for the wrong direction after you sit on the first arrived bus for the correct direction. The paper discusses the idea as far as possible, since modeling or implementation has not been possible. This paper's main purpose is to present the idea." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{JonesPedersen13, title = "{T}he {D}istributed {A}pplication {D}ebugger", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Jones, Michael Quinn and Pedersen, Jan Bækgaard", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "217--232", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "In this paper we introduce a tool for debugging parallel programs which utilize the popular MPI (message passing interface) C library. The tool is called The Distributed Application Debugger and introduces distinct components around the code being debugged in order to play, record, and replay sessions of the user's code remotely. The GUI component incorporates the popular GDB debugger for stepping through code line by line as it runs on the distributed cluster as well as an analysis tool for stepping through the executed portions of code after the session has completed. While the system is composed of multiple components, the logistics of coordinating them is managed without user interaction; requiring the user to only provide the location of the program to debug before starting." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Rehr13, title = "{BPU} {S}imulator", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Rehr, Martin and Skovhede, Kenneth and Vinter, Brian", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "233--248", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "A number of scientific applications start their life as a Matlab prototype that is later re-implemented in a low level programming language, typically C++ or Fortran for the sake of performance. Bohrium is a project that seeks to eliminate both the cost and the potential errors introduced in that process. Our goal is to support all execution platforms, and in this work we introduce the Bohrium Processing Unit, BPU, which will be the FPGA backend for Bohrium. The BPU is modeled as a PyCSP application, and the clear advantages of using CSP for simulating a new CPU is described. The current PyCSP simulator is able to simulate 2\^{}20 Monte Carlo simulations in less than 35 seconds in the smallest BPU simulation." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Barnes13a, title = "{E}xploring {GPGPU} {A}cceleration of {P}rocess-{O}riented {S}imulations", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Barnes, Frederick R. M. and Pressnell, Thomas and Le Foll, Brendan", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "249--262", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "This paper reports on our experiences of using commodity GPUs to speed-up the execution of fine-grained concurrent simulations. Starting with an existing process-oriented \textquotedblboids\textquotedbl simulation, we explore a variety of techniques aimed at improving performance, gradually refactoring the original code. Successive improvements lead to a 10-fold improvement in performance, which we believe can still be improved upon, allowing us to explore simulations with larger numbers of agents (30,000 rather than 2,000) interactively and without significant performance degradation." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Jones13, title = "{A} {P}ersonal {P}erspective on the {S}tate of {HPC} in 2013", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Jones, Christopher C.R.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "263--270", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "This paper is fundamentally a personal perspective on the sad state of High Performance Computing (HPC, or what was known once as Supercomputing). It arises from the author's current experience in trying to find computing technology that will allow codes to run faster: codes that have been painstakingly adapted to efficient performance on parallel computing technologies since around 1990, and have allowed effective 10-fold increases in computing performance at 5 year HPC up-grade intervals, but for which the latest high-count multi-core processor options fail to deliver improvement. The presently available processors may as well not have the majority of their cores as to use them actually slows the code - hard-won budget must be squandered on cores that will not contribute. The present situation is not satisfactory: there are very many reasons why we need computational response, not merely throughput. There are a host of cases where we need a large, complex simulation to run in a very short time. A simplistic calculation based on the nominal performance of some of the big machines with vast numbers of cores would lead one to believe that such rapid computation would be possible. The nature of the machines and the programming paradigms, however, remove this possibility. Some of the ways in which the computer science community could mitigate the hardware shortfalls are discussed, with a few more off the wall ideas about where greater compute performance might be found." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{RitsonBarnes13, title = "{A}n {E}valuation of {I}ntel's {R}estricted {T}ransactional {M}emory for {CPA}s", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Ritson, Carl G. and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "271--292", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "With the release of their latest processor microarchitecture, codenamed Haswell, Intel added new Transactional Synchronization Extensions (TSX) to their processors' instruction set. These extensions include support for Restricted Transactional Memory (RTM), a programming model in which arbitrary sized units of memory can be read and written in an atomic manner. This paper describes the low-level RTM programming model, benchmarks the performance of its instructions and speculates on how it may be used to implement and enhance Communicating Process Architectures." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Welch13a, title = "{L}ife of occam-{P}i", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Welch, Peter H.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "293--318", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "This paper considers some questions prompted by a brief review of the history of computing. Why is programming so hard? Why is concurrency considered an \textquotedbladvanced\textquotedbl subject? What's the matter with Objects? Where did all the Maths go? In searching for answers, the paper looks at some concerns over fundamental ideas within object orientation (as represented by modern programming languages), before focussing on the concurrency model of communicating processes and its particular expression in the occam family of languages. In that focus, it looks at the history of occam, its underlying philosophy (Ockham's Razor), its semantic foundation on Hoare's CSP, its principles of process oriented design and its development over almost three decades into occam-pi (which blends in the concurrency dynamics of Milner's pi-calculus). Also presented will be an urgent need for rationalisation - occam-pi is an experiment that has demonstrated significant results, but now needs time to be spent on careful review and implementing the conclusions of that review. Finally, the future is considered. In particular, is there a future?" } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Welch13b, title = "{M}utually {A}ssured {D}estruction (or the {J}oy of {S}ync)", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Welch, Peter H. and Pedersen, Jan Bækgaard and Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "319--320", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "In contrast to the Client-Server pattern, Mutually Assured Destruction (MAD) allows the safe opening of communication by either of two processes with the other. Should both processes commit to opening conversation together, both are immediately aware of this and can take appropriate action - there is no deadlock, even though the communications are synchronous. A common need for this pattern is in real-time control systems (e.g. robotics), artificial intelligence, e-commerce, model checking and elsewhere. A typical scenario is when two processes are given a problem to solve; we are satisfied with a solution to either one of them; whichever process solves its problem first kills the other and makes a report; the one that is killed also reports that fact. In this case, the opening communication between the two processes is the only communication (a kill signal). If both solve their problem around the same time and try to kill each other, MAD is the desired outcome (along with making their reports). A simple and safe solution (verified with FDR) for this pattern with occam synchronous communications is presented. This is compared with solutions via asynchronous communications. Although these avoid the potential deadlock that a naive strategy with synchronous communications would present, they leave a mess that has to be tidied up and this tidying adds complexity and run-time cost. The Joy of Sync arises from the extra semantic information provided by synchronous communications - that if a message has been sent, the receiving process has taken it. With this knowledge comes power and with that power comes the ability to implement higher level synchronisation patterns (such as MAD and Non-blocking Syncs) in ways that are simple, verifyably safe and impose very low overheads." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{GibsonRobinson13b, title = "{FDR}3: the {F}uture of {CSP} {M}odel {C}hecking", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Gibson-Robinson, Thomas", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "321--322", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "Over the last couple of years a brand new version of FDR, FDR3, has been under development at Oxford. This includes greatly improved performance (typically 2.5 times faster than FDR2 on a single core) and, for the first time, a parallel model-checking mode that scales almost linearly with the number of available cores. In this talk I will give a demonstration of FDR3, including the new debug viewer, the integrated version of ProBE, and the enhanced error messages. FDR3 is due for general release this October." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{GibsonRobinson13c, title = "{U}sing {FDR} to {M}odel {C}heck {CSP}-{L}ike {L}anguages", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Gibson-Robinson, Thomas", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "323--324", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "This talk presents a demonstration of tyger, a tool that has been constructed to allow a large class of CSP-like languages to be simulated in CSP. In particular, FDR will be used to demonstrate model checking of a simple CCS version of the classic Dining Philosophers problem. The theory behind this demonstration will be presented in the paper \textquotedblEfficient Simulation of CSP-Like Languages\textquotedbl." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Beton13, title = "{A}n {I}ntroduction to {G}o", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Beton, Rick D.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "325--326", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "Go is a new open-source programming language from a team of Google's developers. It provides a modern garbage-collected runtime that has particular support for concurrency. The pattern for this is based on Hoare's CSP, using channels for synchronization and communication, and discouraging the direct sharing of variables. Processes are light-weight co-operative threads that the runtime time-slices onto underlying operating system threads; this allows an application's natural concurrency to be expressed as fully as needed by the natural concurrency of the application domain. The presentation provides an overview of Go's main features, covering in particular the unusual interfaces and duck-typing, the reflection and the concurrency. Focussing on concurrency in detail, as an example, a simple web-crawler application is converted step by step to operate concurrently, and at each stage this allows a particular feature of Go's concurrency to be demonstrated." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Barnes13b, title = "{T}he {G}uppy {L}anguage: an {U}pdate", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Barnes, Frederick R. M.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "327--328", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "As a possible successor and perhaps replacement language for occam-pi, we have been working piecemeal for the past few years on a new language - Guppy. Rather than being a completely new language, it aims to rationalise and simplify the concurrent programming concepts and idioms that we have explored whilst developing occam-pi. This short talk will look at the current state of the language and its implementation, that is now able to compile and run a simple \textquotedblcommstime\textquotedbl benchmark, scheduled by the existing occam-pi run-time system (CCSP)." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Welch13c, title = "{A}n occam {M}odel of {XCHAN}s", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Welch, Peter H.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "329--330", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "Øyvind Teig, in \textquotedblXCHANs: Notes on a New Channel Type\textquotedbl, proposed a higher level channel construct (XCHAN) that attempts to reconcile those wedded to asynchronous message passing with the synchronous form in CSP. Sending a message does not block the sender, but the message may not get sent: the sender receives a success/fail result on each send. The XCHAN provides a conventional feedback channel on which it signals when it is ready to take a message. Being ready means that it has space (if it is buffered) or a reading process has committed to take the message (if it is not buffered). Sending to a ready XCHAN always succeeds; sending to an XCHAN that is not ready always fails. The sender can always wait for the signal from the XCHAN (whilst ALTing on, and processing, other events) before sending. We can model an XCHAN by a process in occam-pi. Buffered XCHANs are easy. Zero-buffered XCHANs are a little harder, because we need to maintain end-to-end synchronisation. However, occam-pi's extended input (??) and output (!!) primitives enable the process implementing the XCHAN to be hidden from its users. Unfortunately, extended outputs are not yet in the language, but their semantics can be simulated by making the receiving process read twice and ignore the first (which is just a signal whose taking must commit the reader to its second read). An important message is that sane higher level synchronisation mechanisms are usually not hard to implement efficiently via the low level CSP primitives offered by occam-pi. Although not yet measured for XCHANs, it is likely that such simulation in occam-pi will have competitive performance with direct implementation elsewhere." } db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
@InProceedings{Teig13b, title = "{N}ames of {XCHAN} {I}mplementations", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
author= "Teig, Øyvind", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
editor= "Welch, Peter H. and Barnes, Frederick R. M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.", db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
pages = "331--332", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2013", isbn= "978-0-9565409-7-3", year= "2013", month= "nov", abstract= "Two names for possible XCHAN implementations are suggested. The original presentation (Teig, CPA-2012) describes the \textquotedblclassic\textquotedbl scheme where the xchan-ready channel is used only if the original sending fails. The occam-pi model (Welch, CPA-2013 fringe) uses the \textquotedblpre-confirmed\textquotedbl scheme, where a signal on xchan-ready is a necessary precondition to any communication. It is believed that \textquotedblfeathering\textquotedbl (Teig, CPA-2013) seems to be possible only with the classic scheme." }